Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141724	1			T79	51		T80	114		T81	2
values[2]	3765	1			T80	1		T251	3		T421	7
values[3]	1661	1			T421	2		T556	80		T554	1
values[4]	1181	1			T556	44		T554	4		T917	1
values[5]	990	1			T556	25		T554	3		T917	1
values[6]	867	1			T556	27		T554	4		T917	1
values[7]	864	1			T556	14		T554	4		T917	1
values[8]	764	1			T556	11		T554	5		T917	1
values[9]	735	1			T556	10		T554	1		T917	1
values[10]	666	1			T556	10		T554	2		T917	1
values[11]	573	1			T556	11		T554	3		T917	1
values[12]	523	1			T556	3		T554	3		T917	1
values[13]	471	1			T556	12		T554	2		T917	1
values[14]	427	1			T556	20		T554	2		T917	1
values[15]	435	1			T556	3		T554	1		T917	1
values[16]	394	1			T554	2		T917	1		T747	30
values[17]	405	1			T554	3		T917	1		T747	6
values[18]	355	1			T554	1		T917	1		T747	1
values[19]	276	1			T554	3		T917	1		T477	1
values[20]	275	1			T554	1		T917	1		T477	1
values[21]	281	1			T554	3		T917	1		T477	1
values[22]	264	1			T554	2		T917	1		T477	1
values[23]	254	1			T554	1		T917	1		T477	1
values[24]	244	1			T554	1		T917	1		T477	1
values[25]	224	1			T554	6		T917	1		T477	1
values[26]	217	1			T554	4		T917	1		T477	1
values[27]	200	1			T554	2		T917	1		T477	1
values[28]	227	1			T554	2		T917	1		T477	1
values[29]	169	1			T554	3		T917	1		T477	1
values[30]	167	1			T554	2		T917	1		T477	1
values[31]	123	1			T554	2		T917	1		T477	1
values[32]	107	1			T554	3		T917	1		T477	1
values[33]	97	1			T554	1		T917	1		T477	1
values[34]	99	1			T554	3		T917	1		T477	1
values[35]	134	1			T554	11		T917	1		T477	1
values[36]	136	1			T554	5		T917	1		T477	1
values[37]	150	1			T554	6		T917	1		T477	1
values[38]	123	1			T554	5		T917	1		T477	1
values[39]	129	1			T554	2		T917	1		T477	1
values[40]	118	1			T554	1		T917	1		T477	1
values[41]	114	1			T554	1		T917	1		T477	1
values[42]	138	1			T554	2		T917	1		T477	1
values[43]	114	1			T554	6		T917	1		T477	1
values[44]	117	1			T554	3		T917	1		T477	1
values[45]	113	1			T554	2		T917	1		T477	1
values[46]	113	1			T554	4		T917	1		T477	1
values[47]	91	1			T554	3		T917	1		T477	1
values[48]	66	1			T554	2		T917	2		T477	1
values[49]	59	1			T554	2		T917	1		T477	1
values[50]	55	1			T554	1		T917	1		T477	1
values[51]	51	1			T554	4		T917	1		T477	1
values[52]	53	1			T554	2		T917	1		T477	1
values[53]	40	1			T554	2		T917	1		T477	1
values[54]	49	1			T554	1		T917	1		T477	1
values[55]	46	1			T554	2		T917	1		T477	1
values[56]	50	1			T554	2		T917	1		T477	1
values[57]	50	1			T554	4		T917	1		T477	1
values[58]	53	1			T554	6		T917	1		T477	1
values[59]	44	1			T554	4		T917	1		T477	1
values[60]	54	1			T554	3		T917	1		T477	1
values[61]	60	1			T554	4		T917	1		T477	1
values[62]	58	1			T554	2		T917	1		T477	1
values[63]	55	1			T554	1		T917	1		T477	1
values[64]	47	1			T554	2		T917	1		T477	1
values[65]	41	1			T554	2		T917	1		T477	1
values[66]	44	1			T554	2		T917	1		T477	1
values[67]	42	1			T554	1		T917	1		T477	1
values[68]	46	1			T554	2		T917	1		T477	1
values[69]	42	1			T554	3		T917	1		T477	1
values[70]	48	1			T554	4		T917	1		T477	1
values[71]	52	1			T554	3		T917	1		T477	1
values[72]	49	1			T554	2		T917	1		T477	1
values[73]	44	1			T554	3		T917	1		T477	1
values[74]	45	1			T554	2		T917	1		T477	1
values[75]	52	1			T554	2		T917	1		T477	1
values[76]	67	1			T554	2		T917	1		T477	1
values[77]	56	1			T554	1		T917	1		T477	1
values[78]	51	1			T554	1		T917	1		T477	1
values[79]	51	1			T554	3		T917	1		T477	1
values[80]	47	1			T554	1		T917	1		T477	1
values[81]	46	1			T554	1		T917	1		T477	1
values[82]	55	1			T554	6		T917	1		T477	1
values[83]	64	1			T554	7		T917	1		T477	1
values[84]	57	1			T554	3		T917	1		T477	1
values[85]	57	1			T554	3		T917	1		T477	1
values[86]	51	1			T554	2		T917	1		T477	1
values[87]	55	1			T554	2		T917	1		T477	1
values[88]	58	1			T554	1		T917	1		T477	1
values[89]	63	1			T554	2		T917	1		T477	1
values[90]	71	1			T554	2		T917	1		T477	1
values[91]	63	1			T554	3		T917	1		T477	1
values[92]	77	1			T554	1		T917	1		T477	1
values[93]	76	1			T554	3		T917	4		T477	1
values[94]	51	1			T554	2		T917	1		T477	1
values[95]	74	1			T554	2		T917	3		T477	1
values[96]	59	1			T554	4		T917	1		T477	1
values[97]	81	1			T554	5		T917	3		T477	2
values[98]	78	1			T554	3		T917	2		T477	4
values[99]	71	1			T554	4		T917	3		T477	3
values[100]	70	1			T554	2		T917	4		T477	2
values[101]	64	1			T554	4		T917	1		T477	3
values[102]	84	1			T554	4		T917	3		T477	2
values[103]	89	1			T554	7		T917	3		T477	1
values[104]	79	1			T554	3		T917	1		T477	2
values[105]	81	1			T554	4		T917	2		T477	3
values[106]	83	1			T554	3		T917	4		T477	9
values[107]	92	1			T554	7		T917	3		T477	4
values[108]	68	1			T554	3		T917	1		T477	1
values[109]	81	1			T554	4		T917	2		T477	2
values[110]	77	1			T554	3		T917	5		T477	3
values[111]	79	1			T554	4		T917	2		T477	2
values[112]	78	1			T554	4		T917	1		T477	2
values[113]	93	1			T554	7		T917	1		T477	2
values[114]	87	1			T554	5		T917	3		T477	2
values[115]	90	1			T554	3		T917	2		T477	3
values[116]	109	1			T554	7		T917	3		T477	2
values[117]	96	1			T554	7		T917	2		T477	1
values[118]	90	1			T554	7		T917	2		T477	2
values[119]	79	1			T554	5		T917	2		T477	1
values[120]	81	1			T554	3		T917	4		T477	2
values[121]	93	1			T554	4		T917	5		T477	5
values[122]	99	1			T554	3		T917	3		T477	2
values[123]	167	1			T554	3		T917	3		T477	1
values[124]	218	1			T554	5		T917	9		T477	2
values[125]	387	1			T554	29		T917	4		T477	1
values[126]	720	1			T554	18		T917	20		T477	16
values[127]	2412	1			T554	14		T917	98		T477	111
values[128]	4033	1			T554	1		T917	209		T477	201