Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	134861	1			T79	49		T80	96		T81	7
values[2]	10291	1			T80	1		T137	6		T421	8
values[3]	4068	1			T137	6		T552	50		T556	4
values[4]	2402	1			T137	7		T552	28		T556	1
values[5]	1448	1			T137	6		T552	15		T556	1
values[6]	1094	1			T137	8		T552	6		T556	4
values[7]	703	1			T137	10		T556	3		T557	4
values[8]	445	1			T137	5		T556	2		T557	2
values[9]	397	1			T137	5		T556	1		T508	5
values[10]	370	1			T137	4		T556	5		T508	16
values[11]	237	1			T137	6		T556	1		T508	8
values[12]	225	1			T137	11		T556	5		T508	6
values[13]	226	1			T137	10		T556	2		T508	8
values[14]	230	1			T137	7		T556	1		T508	3
values[15]	228	1			T137	5		T556	2		T508	6
values[16]	231	1			T137	5		T556	3		T508	3
values[17]	195	1			T137	5		T556	7		T508	7
values[18]	180	1			T137	10		T556	4		T508	6
values[19]	183	1			T137	8		T556	3		T508	6
values[20]	192	1			T137	11		T556	3		T508	6
values[21]	195	1			T137	9		T556	3		T508	11
values[22]	196	1			T137	14		T556	2		T508	5
values[23]	204	1			T137	6		T556	2		T508	6
values[24]	182	1			T137	6		T556	2		T508	11
values[25]	221	1			T137	5		T556	5		T508	5
values[26]	233	1			T137	3		T556	5		T508	38
values[27]	185	1			T137	5		T556	2		T508	17
values[28]	210	1			T137	7		T556	2		T508	4
values[29]	156	1			T137	10		T556	1		T508	8
values[30]	150	1			T137	19		T556	4		T508	5
values[31]	170	1			T137	16		T556	1		T508	2
values[32]	140	1			T137	5		T556	1		T508	3
values[33]	148	1			T137	6		T556	4		T508	5
values[34]	139	1			T137	2		T556	1		T508	4
values[35]	206	1			T137	3		T556	2		T508	7
values[36]	202	1			T137	6		T556	1		T508	9
values[37]	165	1			T137	12		T556	2		T508	6
values[38]	163	1			T137	7		T556	7		T508	11
values[39]	171	1			T137	3		T556	3		T508	13
values[40]	148	1			T137	9		T556	1		T508	11
values[41]	149	1			T137	14		T556	5		T508	3
values[42]	160	1			T137	6		T556	6		T508	18
values[43]	174	1			T137	7		T556	3		T508	5
values[44]	165	1			T137	6		T556	4		T508	5
values[45]	155	1			T137	5		T556	3		T508	9
values[46]	154	1			T137	2		T556	4		T508	11
values[47]	159	1			T556	2		T508	4		T905	1
values[48]	159	1			T556	8		T508	4		T905	1
values[49]	147	1			T556	6		T508	5		T905	1
values[50]	181	1			T556	9		T508	18		T905	1
values[51]	125	1			T556	5		T508	6		T905	1
values[52]	146	1			T556	2		T508	3		T905	1
values[53]	122	1			T556	1		T508	11		T905	1
values[54]	153	1			T556	1		T508	27		T905	1
values[55]	132	1			T556	5		T508	4		T905	1
values[56]	133	1			T556	3		T508	4		T905	1
values[57]	181	1			T556	1		T508	7		T905	1
values[58]	144	1			T556	4		T508	4		T905	1
values[59]	110	1			T556	4		T905	1		T938	5
values[60]	124	1			T556	1		T905	1		T938	15
values[61]	146	1			T556	2		T905	1		T938	7
values[62]	148	1			T556	3		T905	1		T938	4
values[63]	156	1			T556	8		T905	1		T938	9
values[64]	180	1			T556	19		T905	1		T938	9
values[65]	171	1			T556	24		T905	1		T938	8
values[66]	140	1			T556	10		T905	1		T938	6
values[67]	159	1			T556	10		T905	1		T938	12
values[68]	110	1			T556	6		T905	1		T938	8
values[69]	107	1			T556	4		T905	1		T938	6
values[70]	112	1			T556	11		T905	1		T938	9
values[71]	104	1			T556	21		T905	1		T938	13
values[72]	143	1			T556	40		T905	1		T938	19
values[73]	79	1			T556	16		T905	1		T938	12
values[74]	93	1			T556	8		T905	1		T938	15
values[75]	80	1			T556	3		T905	1		T938	8
values[76]	82	1			T556	7		T905	1		T938	9
values[77]	70	1			T556	6		T905	1		T938	6
values[78]	77	1			T556	7		T905	1		T938	8
values[79]	97	1			T556	13		T905	1		T938	17
values[80]	73	1			T556	2		T905	1		T938	14
values[81]	86	1			T556	3		T905	1		T938	5
values[82]	84	1			T556	4		T905	1		T938	5
values[83]	73	1			T556	5		T905	1		T938	7
values[84]	77	1			T556	5		T905	1		T938	5
values[85]	89	1			T556	12		T905	1		T938	9
values[86]	63	1			T556	3		T905	1		T938	12
values[87]	96	1			T556	3		T905	1		T938	8
values[88]	72	1			T556	4		T905	1		T938	7
values[89]	73	1			T556	8		T905	1		T938	9
values[90]	102	1			T556	16		T905	1		T938	22
values[91]	100	1			T556	10		T905	2		T938	13
values[92]	85	1			T556	5		T905	4		T938	12
values[93]	85	1			T556	8		T905	1		T938	9
values[94]	81	1			T556	12		T905	1		T938	6
values[95]	88	1			T556	4		T905	4		T938	5
values[96]	85	1			T556	3		T905	4		T938	9
values[97]	75	1			T556	3		T905	2		T938	7
values[98]	60	1			T556	1		T905	3		T938	11
values[99]	65	1			T556	1		T905	2		T938	12
values[100]	79	1			T556	7		T905	7		T938	14
values[101]	54	1			T556	4		T905	1		T938	10
values[102]	63	1			T556	4		T905	1		T938	13
values[103]	78	1			T556	5		T905	2		T938	19
values[104]	85	1			T556	3		T905	3		T938	21
values[105]	64	1			T556	2		T905	1		T938	13
values[106]	77	1			T556	1		T905	1		T938	18
values[107]	78	1			T556	1		T905	3		T938	13
values[108]	84	1			T556	10		T905	3		T938	11
values[109]	67	1			T556	7		T905	1		T938	7
values[110]	81	1			T556	7		T905	1		T938	12
values[111]	71	1			T556	1		T905	1		T938	9
values[112]	85	1			T905	1		T938	12		T536	2
values[113]	85	1			T905	2		T938	10		T536	2
values[114]	80	1			T905	1		T938	4		T536	2
values[115]	63	1			T905	1		T938	6		T536	2
values[116]	87	1			T905	2		T938	16		T536	5
values[117]	75	1			T905	1		T938	14		T536	4
values[118]	61	1			T905	1		T938	9		T536	3
values[119]	62	1			T905	3		T938	6		T536	2
values[120]	57	1			T905	3		T938	7		T536	4
values[121]	62	1			T905	1		T938	9		T536	3
values[122]	78	1			T905	1		T938	9		T536	5
values[123]	79	1			T905	1		T938	7		T536	3
values[124]	67	1			T905	2		T938	10		T536	2
values[125]	77	1			T905	1		T938	15		T536	3
values[126]	155	1			T905	4		T938	29		T536	6
values[127]	775	1			T905	50		T938	52		T536	63
values[128]	5494	1			T905	311		T938	24		T536	708