Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	144363	1			T79	38		T80	115		T81	8
values[2]	4502	1			T251	2		T462	1		T421	6
values[3]	2257	1			T421	1		T554	25		T760	1
values[4]	1828	1			T421	1		T554	54		T760	1
values[5]	1560	1			T554	48		T760	1		T696	64
values[6]	1273	1			T554	29		T760	1		T696	60
values[7]	1080	1			T554	22		T760	1		T696	76
values[8]	910	1			T554	14		T760	1		T696	59
values[9]	848	1			T554	34		T760	1		T696	37
values[10]	787	1			T554	29		T760	1		T696	32
values[11]	733	1			T554	27		T760	1		T696	25
values[12]	626	1			T554	55		T760	1		T696	21
values[13]	521	1			T554	32		T760	1		T696	26
values[14]	515	1			T554	34		T760	1		T696	27
values[15]	552	1			T554	56		T760	1		T696	17
values[16]	581	1			T554	61		T760	1		T696	17
values[17]	605	1			T554	88		T760	1		T696	13
values[18]	532	1			T554	86		T760	1		T696	9
values[19]	465	1			T554	77		T760	1		T696	12
values[20]	457	1			T554	105		T760	1		T696	9
values[21]	342	1			T554	96		T760	1		T696	5
values[22]	303	1			T554	78		T760	1		T900	2
values[23]	285	1			T554	44		T760	1		T900	1
values[24]	217	1			T554	26		T760	1		T900	1
values[25]	218	1			T554	35		T760	1		T900	2
values[26]	184	1			T554	32		T760	1		T900	3
values[27]	165	1			T554	17		T760	1		T900	1
values[28]	170	1			T554	16		T760	1		T900	5
values[29]	127	1			T554	4		T760	1		T900	4
values[30]	147	1			T554	2		T760	1		T900	2
values[31]	178	1			T554	3		T760	1		T900	6
values[32]	143	1			T554	4		T760	1		T900	1
values[33]	133	1			T554	8		T760	1		T900	1
values[34]	138	1			T554	20		T760	1		T900	2
values[35]	140	1			T554	28		T760	1		T900	1
values[36]	142	1			T554	18		T760	1		T900	2
values[37]	152	1			T554	28		T760	1		T900	3
values[38]	149	1			T554	25		T760	1		T900	2
values[39]	106	1			T554	21		T760	1		T900	2
values[40]	70	1			T554	23		T760	1		T900	1
values[41]	77	1			T554	11		T760	1		T900	3
values[42]	87	1			T760	1		T900	2		T536	1
values[43]	96	1			T760	1		T900	2		T536	1
values[44]	84	1			T760	1		T900	5		T536	1
values[45]	109	1			T760	1		T900	3		T536	1
values[46]	87	1			T760	1		T900	4		T536	1
values[47]	46	1			T760	1		T900	1		T536	1
values[48]	53	1			T760	2		T900	3		T536	1
values[49]	63	1			T760	1		T900	3		T536	1
values[50]	57	1			T760	1		T900	4		T536	1
values[51]	57	1			T760	1		T900	3		T536	1
values[52]	39	1			T760	1		T900	1		T536	1
values[53]	51	1			T760	1		T900	2		T536	1
values[54]	53	1			T760	1		T900	3		T536	1
values[55]	45	1			T760	1		T900	1		T536	1
values[56]	47	1			T760	1		T900	3		T536	1
values[57]	48	1			T760	1		T900	5		T536	1
values[58]	44	1			T760	1		T900	1		T536	1
values[59]	43	1			T760	1		T900	2		T536	1
values[60]	49	1			T760	1		T900	1		T536	1
values[61]	56	1			T760	1		T900	2		T536	1
values[62]	39	1			T760	1		T900	1		T536	1
values[63]	41	1			T760	1		T900	3		T536	1
values[64]	48	1			T760	1		T900	1		T536	1
values[65]	41	1			T760	1		T900	1		T536	1
values[66]	42	1			T760	1		T900	2		T536	1
values[67]	45	1			T760	1		T900	2		T536	1
values[68]	46	1			T760	1		T900	4		T536	1
values[69]	47	1			T760	1		T900	3		T536	1
values[70]	54	1			T760	1		T900	1		T536	1
values[71]	67	1			T760	1		T900	4		T536	1
values[72]	55	1			T760	1		T900	1		T536	1
values[73]	55	1			T760	1		T900	4		T536	1
values[74]	56	1			T760	1		T900	2		T536	1
values[75]	58	1			T760	1		T900	1		T536	1
values[76]	50	1			T760	1		T900	2		T536	1
values[77]	60	1			T760	1		T900	2		T536	1
values[78]	78	1			T760	1		T900	1		T536	1
values[79]	61	1			T760	1		T900	2		T536	1
values[80]	73	1			T760	1		T900	2		T536	1
values[81]	64	1			T760	1		T900	2		T536	1
values[82]	70	1			T760	1		T900	5		T536	1
values[83]	67	1			T760	1		T900	6		T536	1
values[84]	70	1			T760	1		T900	2		T536	1
values[85]	58	1			T760	1		T900	1		T536	1
values[86]	73	1			T760	1		T900	2		T536	1
values[87]	69	1			T760	1		T900	4		T536	1
values[88]	66	1			T760	1		T900	1		T536	1
values[89]	62	1			T760	3		T900	2		T536	1
values[90]	67	1			T760	5		T900	2		T536	1
values[91]	69	1			T760	9		T900	2		T536	1
values[92]	68	1			T760	2		T900	2		T536	1
values[93]	95	1			T760	3		T900	3		T536	1
values[94]	78	1			T760	6		T900	7		T536	1
values[95]	81	1			T760	3		T900	3		T536	1
values[96]	77	1			T760	3		T900	11		T536	1
values[97]	70	1			T760	4		T900	4		T536	1
values[98]	84	1			T760	4		T900	6		T536	1
values[99]	88	1			T760	2		T900	4		T536	1
values[100]	81	1			T760	1		T900	4		T536	1
values[101]	85	1			T760	1		T900	5		T536	1
values[102]	68	1			T760	1		T900	3		T536	1
values[103]	81	1			T760	1		T900	2		T536	1
values[104]	87	1			T760	3		T900	2		T536	1
values[105]	70	1			T760	6		T900	4		T536	1
values[106]	73	1			T760	2		T900	4		T536	1
values[107]	63	1			T760	1		T900	5		T536	1
values[108]	67	1			T760	1		T900	2		T536	1
values[109]	81	1			T760	2		T900	2		T536	1
values[110]	81	1			T760	1		T900	3		T536	2
values[111]	83	1			T760	2		T900	6		T536	1
values[112]	81	1			T760	2		T900	3		T536	2
values[113]	80	1			T760	1		T900	6		T536	2
values[114]	71	1			T760	1		T900	4		T536	1
values[115]	83	1			T760	1		T900	4		T536	4
values[116]	104	1			T760	2		T900	12		T536	3
values[117]	105	1			T760	1		T900	6		T536	1
values[118]	100	1			T760	1		T900	4		T536	2
values[119]	94	1			T760	3		T900	1		T536	2
values[120]	86	1			T760	5		T900	5		T536	1
values[121]	94	1			T760	4		T900	6		T536	2
values[122]	93	1			T760	3		T900	12		T536	2
values[123]	140	1			T760	2		T900	18		T536	1
values[124]	234	1			T760	4		T900	21		T536	3
values[125]	366	1			T760	1		T900	29		T536	1
values[126]	709	1			T760	5		T900	38		T536	19
values[127]	2440	1			T760	99		T900	34		T536	136
values[128]	4413	1			T760	202		T900	5		T536	215