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Summary for Variable cp_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_error

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 905096 1 T79 409 T80 816 T81 45
auto[1] 507866 1 T79 6 T80 71 T81 8



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] 362327 1 T79 48 T80 315 T81 19



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 982909 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 430053 1 T79 98 T80 306 T81 19



Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 1 0 1 100.00


Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins
cp_opcodecp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] biggest_size 115557 1 T79 10 T80 99 T81 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%