Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	438	1			T137	1		T556	3		T761	1
all_values[1]	486	1			T137	3		T939	1		T556	1
all_values[2]	427	1			T556	1		T761	1		T554	2
all_values[3]	422	1			T137	3		T565	1		T556	3
all_values[4]	519	1			T552	1		T556	4		T761	2
all_values[5]	434	1			T137	1		T552	1		T556	5
all_values[6]	490	1			T137	4		T552	1		T556	4
all_values[7]	460	1			T137	2		T556	2		T761	1
all_values[8]	430	1			T137	1		T556	4		T554	1
all_values[9]	431	1			T137	2		T565	1		T556	3
all_values[10]	446	1			T565	1		T552	1		T556	3
all_values[11]	416	1			T137	1		T552	1		T556	2
all_values[12]	425	1			T137	3		T552	1		T556	3
all_values[13]	431	1			T137	4		T552	1		T556	2
all_values[14]	461	1			T552	1		T556	1		T554	3
all_values[15]	444	1			T137	2		T251	2		T552	2
all_values[16]	456	1			T137	1		T251	1		T552	3
all_values[17]	431	1			T556	1		T761	1		T941	1
all_values[18]	456	1			T556	3		T557	2		T941	1
all_values[19]	487	1			T137	3		T552	2		T556	4
all_values[20]	491	1			T137	1		T556	2		T761	2
all_values[21]	440	1			T137	2		T552	2		T556	6
all_values[22]	428	1			T251	1		T552	1		T556	3
all_values[23]	464	1			T552	1		T556	6		T557	1
all_values[24]	421	1			T251	1		T939	1		T556	3
all_values[25]	472	1			T556	3		T761	2		T557	1
all_values[26]	489	1			T137	2		T556	4		T450	1
all_values[27]	464	1			T137	4		T556	4		T557	1
all_values[28]	380	1			T251	1		T565	1		T552	1
all_values[29]	446	1			T137	1		T565	1		T552	1
all_values[30]	467	1			T137	1		T556	1		T557	1
all_values[31]	469	1			T251	1		T565	1		T552	1
all_values[32]	429	1			T137	1		T565	3		T552	1
all_values[33]	470	1			T556	1		T450	2		T761	2
all_values[34]	433	1			T565	1		T556	2		T450	1
all_values[35]	486	1			T556	3		T921	1		T761	1
all_values[36]	412	1			T450	1		T894	4		T560	2
all_values[37]	446	1			T137	1		T552	2		T556	1
all_values[38]	467	1			T556	4		T761	3		T894	3
all_values[39]	444	1			T137	2		T556	6		T761	1
all_values[40]	486	1			T137	2		T556	3		T941	3
all_values[41]	443	1			T137	2		T552	1		T556	3
all_values[42]	428	1			T137	1		T565	1		T556	1
all_values[43]	453	1			T552	1		T556	1		T450	1
all_values[44]	437	1			T552	1		T556	1		T557	2
all_values[45]	407	1			T137	1		T552	2		T556	4
all_values[46]	496	1			T137	1		T565	1		T552	1
all_values[47]	469	1			T552	1		T556	3		T921	1
all_values[48]	423	1			T137	2		T556	3		T761	2
all_values[49]	453	1			T137	1		T552	1		T556	3