Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3362	1			T80	5		T137	5		T251	2
all_values[1]	3404	1			T80	7		T137	6		T251	4
all_values[2]	3464	1			T80	6		T137	2		T251	3
all_values[3]	3384	1			T80	5		T137	9		T251	2
all_values[4]	3331	1			T80	2		T137	8		T251	1
all_values[5]	3419	1			T80	6		T137	7		T251	2
all_values[6]	3384	1			T80	6		T137	2		T251	1
all_values[7]	3253	1			T80	7		T137	6		T251	2
all_values[8]	3484	1			T80	8		T137	6		T251	1
all_values[9]	3489	1			T80	5		T137	2		T251	3
all_values[10]	3410	1			T80	6		T137	5		T251	1
all_values[11]	3472	1			T80	6		T137	6		T251	2
all_values[12]	3427	1			T80	2		T137	10		T552	3
all_values[13]	3325	1			T80	4		T137	8		T251	1
all_values[14]	3323	1			T80	5		T137	1		T251	2
all_values[15]	3382	1			T80	6		T137	6		T251	1
all_values[16]	3374	1			T80	7		T137	8		T251	1
all_values[17]	3382	1			T80	8		T137	6		T251	1
all_values[18]	3361	1			T80	1		T137	12		T251	2
all_values[19]	3530	1			T80	7		T137	10		T251	1
all_values[20]	3475	1			T80	3		T137	5		T561	1
all_values[21]	3426	1			T80	3		T137	10		T422	4
all_values[22]	3334	1			T80	4		T137	6		T251	2
all_values[23]	3296	1			T80	9		T137	5		T552	1
all_values[24]	3364	1			T80	6		T137	8		T251	2
all_values[25]	3429	1			T80	3		T137	5		T251	3
all_values[26]	3449	1			T80	4		T137	8		T251	1
all_values[27]	3366	1			T80	7		T137	3		T552	1
all_values[28]	3450	1			T80	5		T137	7		T552	4
all_values[29]	3515	1			T80	5		T137	8		T251	5
all_values[30]	3372	1			T80	6		T137	5		T251	2
all_values[31]	3498	1			T80	7		T137	9		T251	1
all_values[32]	3534	1			T80	5		T137	7		T251	3
all_values[33]	3255	1			T80	6		T137	4		T552	3
all_values[34]	3403	1			T80	4		T137	5		T251	3
all_values[35]	3322	1			T80	3		T137	9		T251	1
all_values[36]	3413	1			T80	3		T137	5		T552	4
all_values[37]	3433	1			T80	3		T137	8		T552	4
all_values[38]	3378	1			T80	7		T137	5		T251	1
all_values[39]	3421	1			T80	5		T137	6		T251	2
all_values[40]	3350	1			T80	4		T137	11		T251	4
all_values[41]	3348	1			T80	5		T137	8		T251	2
all_values[42]	3431	1			T80	2		T137	6		T552	3
all_values[43]	3433	1			T80	6		T137	9		T251	1
all_values[44]	3491	1			T80	7		T137	6		T251	2
all_values[45]	3386	1			T80	7		T137	6		T251	1
all_values[46]	3347	1			T80	5		T137	6		T251	1
all_values[47]	3364	1			T80	5		T137	7		T251	1
all_values[48]	3509	1			T137	2		T251	1		T552	1
all_values[49]	3487	1			T80	4		T137	9		T251	3
all_values[50]	3507	1			T80	1		T137	2		T251	2
all_values[51]	3433	1			T80	5		T137	7		T251	1
all_values[52]	3529	1			T80	6		T137	9		T251	1
all_values[53]	3455	1			T80	3		T137	7		T552	1
all_values[54]	3388	1			T80	8		T137	5		T561	1
all_values[55]	3382	1			T80	2		T137	5		T251	1
all_values[56]	3489	1			T80	3		T137	2		T251	3
all_values[57]	3481	1			T80	8		T137	11		T552	3
all_values[58]	3435	1			T80	3		T137	4		T251	2
all_values[59]	3395	1			T80	5		T137	5		T561	1
all_values[60]	3336	1			T80	6		T137	5		T251	2
all_values[61]	3453	1			T80	3		T137	12		T251	3
all_values[62]	3461	1			T80	4		T137	11		T251	1
all_values[63]	3466	1			T80	5		T137	7		T251	1