| V1 |
chip_sw_example_tests |
chip_sw_example_rom |
|
|
0 |
0 |
-- |
|
|
chip_sw_example_flash |
|
|
0 |
0 |
-- |
|
|
chip_sw_example_manufacturer |
|
|
0 |
0 |
-- |
|
|
chip_sw_example_concurrency |
|
|
0 |
0 |
-- |
| V1 |
csr_hw_reset |
chip_csr_hw_reset |
|
|
0 |
0 |
-- |
| V1 |
csr_rw |
chip_csr_rw |
|
|
0 |
0 |
-- |
| V1 |
csr_bit_bash |
chip_csr_bit_bash |
|
|
0 |
0 |
-- |
| V1 |
csr_aliasing |
chip_csr_aliasing |
|
|
0 |
0 |
-- |
| V1 |
csr_mem_rw_with_rand_reset |
chip_csr_mem_rw_with_rand_reset |
|
|
0 |
0 |
-- |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
chip_csr_rw |
|
|
0 |
0 |
-- |
|
|
chip_csr_aliasing |
|
|
0 |
0 |
-- |
| V1 |
xbar_smoke |
xbar_smoke |
|
|
0 |
0 |
-- |
| V1 |
chip_sw_gpio_out |
chip_sw_gpio |
|
|
0 |
0 |
-- |
| V1 |
chip_sw_gpio_in |
chip_sw_gpio |
|
|
0 |
0 |
-- |
| V1 |
chip_sw_gpio_irq |
chip_sw_gpio |
|
|
0 |
0 |
-- |
| V1 |
chip_sw_uart_tx_rx |
chip_sw_uart_tx_rx |
|
|
0 |
0 |
-- |
| V1 |
chip_sw_uart_rx_overflow |
chip_sw_uart_tx_rx |
|
|
0 |
0 |
-- |
|
|
chip_sw_uart_tx_rx_idx1 |
|
|
0 |
0 |
-- |
|
|
chip_sw_uart_tx_rx_idx2 |
|
|
0 |
0 |
-- |
|
|
chip_sw_uart_tx_rx_idx3 |
|
|
0 |
0 |
-- |
| V1 |
chip_sw_uart_baud_rate |
chip_sw_uart_rand_baudrate |
|
|
0 |
0 |
-- |
| V1 |
chip_sw_uart_tx_rx_alt_clk_freq |
chip_sw_uart_tx_rx_alt_clk_freq |
|
|
0 |
0 |
-- |
|
|
chip_sw_uart_tx_rx_alt_clk_freq_low_speed |
|
|
0 |
0 |
-- |
| V1 |
|
TOTAL |
|
|
0 |
0 |
-- |
| V2 |
chip_pin_mux |
chip_padctrl_attributes |
18.067m |
4.794ms |
10 |
10 |
100.00 |
| V2 |
chip_padctrl_attributes |
chip_padctrl_attributes |
18.067m |
4.794ms |
10 |
10 |
100.00 |
| V2 |
chip_sw_sleep_pin_mio_dio_val |
chip_sw_sleep_pin_mio_dio_val |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sleep_pin_wake |
chip_sw_sleep_pin_wake |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sleep_pin_retention |
chip_sw_sleep_pin_retention |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_tap_strap_sampling |
chip_tap_straps_dev |
|
|
0 |
0 |
-- |
|
|
chip_tap_straps_prod |
|
|
0 |
0 |
-- |
|
|
chip_tap_straps_rma |
|
|
0 |
0 |
-- |
|
|
chip_tap_straps_testunlock0 |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pattgen_ios |
chip_sw_pattgen_ios |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sleep_pwm_pulses |
chip_sw_sleep_pwm_pulses |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_data_integrity |
chip_sw_data_integrity_escalation |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_instruction_integrity |
chip_sw_data_integrity_escalation |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_ast_clk_outputs |
chip_sw_ast_clk_outputs |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_ast_clk_rst_inputs |
chip_sw_ast_clk_rst_inputs |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_ast_sys_clk_jitter |
chip_sw_clkmgr_jitter |
|
|
0 |
0 |
-- |
|
|
chip_sw_flash_ctrl_ops_jitter_en |
|
|
0 |
0 |
-- |
|
|
chip_sw_flash_ctrl_access_jitter_en |
|
|
0 |
0 |
-- |
|
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
|
|
0 |
0 |
-- |
|
|
chip_sw_aes_enc_jitter_en |
|
|
0 |
0 |
-- |
|
|
chip_sw_hmac_enc_jitter_en |
|
|
0 |
0 |
-- |
|
|
chip_sw_keymgr_key_derivation_jitter_en |
|
|
0 |
0 |
-- |
|
|
chip_sw_kmac_mode_kmac_jitter_en |
|
|
0 |
0 |
-- |
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
|
|
0 |
0 |
-- |
|
|
chip_sw_edn_entropy_reqs_jitter |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_ast_usb_clk_calib |
chip_sw_usb_ast_clk_calib |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sensor_ctrl_ast_alerts |
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup |
|
|
0 |
0 |
-- |
|
|
chip_sw_sensor_ctrl_alert |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sensor_ctrl_ast_status |
chip_sw_sensor_ctrl_status |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup |
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_smoketest |
chip_sw_aes_smoketest |
|
|
0 |
0 |
-- |
|
|
chip_sw_aon_timer_smoketest |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_smoketest |
|
|
0 |
0 |
-- |
|
|
chip_sw_csrng_smoketest |
|
|
0 |
0 |
-- |
|
|
chip_sw_entropy_src_smoketest |
|
|
0 |
0 |
-- |
|
|
chip_sw_gpio_smoketest |
|
|
0 |
0 |
-- |
|
|
chip_sw_hmac_smoketest |
|
|
0 |
0 |
-- |
|
|
chip_sw_kmac_smoketest |
|
|
0 |
0 |
-- |
|
|
chip_sw_otbn_smoketest |
|
|
0 |
0 |
-- |
|
|
chip_sw_pwrmgr_smoketest |
|
|
0 |
0 |
-- |
|
|
chip_sw_pwrmgr_usbdev_smoketest |
|
|
0 |
0 |
-- |
|
|
chip_sw_rv_plic_smoketest |
|
|
0 |
0 |
-- |
|
|
chip_sw_rv_timer_smoketest |
|
|
0 |
0 |
-- |
|
|
chip_sw_rstmgr_smoketest |
|
|
0 |
0 |
-- |
|
|
chip_sw_sram_ctrl_smoketest |
|
|
0 |
0 |
-- |
|
|
chip_sw_uart_smoketest |
|
|
0 |
0 |
-- |
|
|
chip_sw_flash_scrambling_smoketest |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_otp_smoketest |
chip_sw_otp_ctrl_smoketest |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_rom_functests |
rom_keymgr_functest |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_boot |
chip_sw_uart_tx_rx_bootstrap |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_secure_boot |
rom_e2e_smoke |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_rom_raw_unlock |
rom_raw_unlock |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_power_idle_load |
chip_sw_power_idle_load |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_power_sleep_load |
chip_sw_power_sleep_load |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_exit_test_unlocked_bootstrap |
chip_sw_exit_test_unlocked_bootstrap |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_inject_scramble_seed |
chip_sw_inject_scramble_seed |
|
|
0 |
0 |
-- |
| V2 |
tl_d_oob_addr_access |
chip_tl_errors |
|
|
0 |
0 |
-- |
| V2 |
tl_d_illegal_access |
chip_tl_errors |
|
|
0 |
0 |
-- |
| V2 |
tl_d_outstanding_access |
chip_csr_hw_reset |
|
|
0 |
0 |
-- |
|
|
chip_csr_rw |
|
|
0 |
0 |
-- |
|
|
chip_csr_aliasing |
|
|
0 |
0 |
-- |
|
|
chip_same_csr_outstanding |
|
|
0 |
0 |
-- |
| V2 |
tl_d_partial_access |
chip_csr_hw_reset |
|
|
0 |
0 |
-- |
|
|
chip_csr_rw |
|
|
0 |
0 |
-- |
|
|
chip_csr_aliasing |
|
|
0 |
0 |
-- |
|
|
chip_same_csr_outstanding |
|
|
0 |
0 |
-- |
| V2 |
xbar_base_random_sequence |
xbar_random |
|
|
0 |
0 |
-- |
| V2 |
xbar_random_delay |
xbar_smoke_zero_delays |
|
|
0 |
0 |
-- |
|
|
xbar_smoke_large_delays |
|
|
0 |
0 |
-- |
|
|
xbar_smoke_slow_rsp |
|
|
0 |
0 |
-- |
|
|
xbar_random_zero_delays |
|
|
0 |
0 |
-- |
|
|
xbar_random_large_delays |
|
|
0 |
0 |
-- |
|
|
xbar_random_slow_rsp |
|
|
0 |
0 |
-- |
| V2 |
xbar_unmapped_address |
xbar_unmapped_addr |
|
|
0 |
0 |
-- |
|
|
xbar_error_and_unmapped_addr |
|
|
0 |
0 |
-- |
| V2 |
xbar_error_cases |
xbar_error_random |
|
|
0 |
0 |
-- |
|
|
xbar_error_and_unmapped_addr |
|
|
0 |
0 |
-- |
| V2 |
xbar_all_access_same_device |
xbar_access_same_device |
|
|
0 |
0 |
-- |
|
|
xbar_access_same_device_slow_rsp |
|
|
0 |
0 |
-- |
| V2 |
xbar_all_hosts_use_same_source_id |
xbar_same_source |
|
|
0 |
0 |
-- |
| V2 |
xbar_stress_all |
xbar_stress_all |
|
|
0 |
0 |
-- |
|
|
xbar_stress_all_with_error |
|
|
0 |
0 |
-- |
| V2 |
xbar_stress_with_reset |
xbar_stress_all_with_rand_reset |
|
|
0 |
0 |
-- |
|
|
xbar_stress_all_with_reset_error |
|
|
0 |
0 |
-- |
| V2 |
rom_e2e_smoke |
rom_e2e_smoke |
|
|
0 |
0 |
-- |
| V2 |
rom_e2e_shutdown_output |
rom_e2e_shutdown_output |
|
|
0 |
0 |
-- |
| V2 |
rom_e2e_shutdown_exception_c |
rom_e2e_shutdown_exception_c |
|
|
0 |
0 |
-- |
| V2 |
rom_e2e_boot_policy_valid |
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 |
|
|
0 |
0 |
-- |
|
|
rom_e2e_boot_policy_valid_a_good_b_good_dev |
|
|
0 |
0 |
-- |
|
|
rom_e2e_boot_policy_valid_a_good_b_good_prod |
|
|
0 |
0 |
-- |
|
|
rom_e2e_boot_policy_valid_a_good_b_good_prod_end |
|
|
0 |
0 |
-- |
|
|
rom_e2e_boot_policy_valid_a_good_b_good_rma |
|
|
0 |
0 |
-- |
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 |
|
|
0 |
0 |
-- |
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_dev |
|
|
0 |
0 |
-- |
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_prod |
|
|
0 |
0 |
-- |
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end |
|
|
0 |
0 |
-- |
|
|
rom_e2e_boot_policy_valid_a_good_b_bad_rma |
|
|
0 |
0 |
-- |
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 |
|
|
0 |
0 |
-- |
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_dev |
|
|
0 |
0 |
-- |
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_prod |
|
|
0 |
0 |
-- |
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end |
|
|
0 |
0 |
-- |
|
|
rom_e2e_boot_policy_valid_a_bad_b_good_rma |
|
|
0 |
0 |
-- |
| V2 |
rom_e2e_sigverify_always |
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 |
|
|
0 |
0 |
-- |
|
|
rom_e2e_sigverify_always_a_bad_b_bad_dev |
|
|
0 |
0 |
-- |
|
|
rom_e2e_sigverify_always_a_bad_b_bad_prod |
|
|
0 |
0 |
-- |
|
|
rom_e2e_sigverify_always_a_bad_b_bad_prod_end |
|
|
0 |
0 |
-- |
|
|
rom_e2e_sigverify_always_a_bad_b_bad_rma |
|
|
0 |
0 |
-- |
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 |
|
|
0 |
0 |
-- |
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_dev |
|
|
0 |
0 |
-- |
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_prod |
|
|
0 |
0 |
-- |
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end |
|
|
0 |
0 |
-- |
|
|
rom_e2e_sigverify_always_a_bad_b_nothing_rma |
|
|
0 |
0 |
-- |
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 |
|
|
0 |
0 |
-- |
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_dev |
|
|
0 |
0 |
-- |
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_prod |
|
|
0 |
0 |
-- |
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end |
|
|
0 |
0 |
-- |
|
|
rom_e2e_sigverify_always_a_nothing_b_bad_rma |
|
|
0 |
0 |
-- |
| V2 |
rom_e2e_asm_init |
rom_e2e_asm_init_test_unlocked0 |
|
|
0 |
0 |
-- |
|
|
rom_e2e_asm_init_dev |
|
|
0 |
0 |
-- |
|
|
rom_e2e_asm_init_prod |
|
|
0 |
0 |
-- |
|
|
rom_e2e_asm_init_prod_end |
|
|
0 |
0 |
-- |
|
|
rom_e2e_asm_init_rma |
|
|
0 |
0 |
-- |
| V2 |
rom_e2e_keymgr_init |
rom_e2e_keymgr_init_rom_ext_meas |
|
|
0 |
0 |
-- |
|
|
rom_e2e_keymgr_init_rom_ext_no_meas |
|
|
0 |
0 |
-- |
|
|
rom_e2e_keymgr_init_rom_ext_invalid_meas |
|
|
0 |
0 |
-- |
| V2 |
rom_e2e_static_critical |
rom_e2e_static_critical |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_aes_enc |
chip_sw_aes_enc |
|
|
0 |
0 |
-- |
|
|
chip_sw_aes_enc_jitter_en |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_aes_multi_block |
chip_sw_aes_multi_block |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_aes_interrupt_encryption |
chip_sw_aes_interrupt_encryption |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_aes_entropy |
chip_sw_aes_entropy |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_aes_prng_reseed |
chip_sw_aes_prng_reseed |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_aes_force_prng_reseed |
chip_sw_aes_force_prng_reseed |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_aes_idle |
chip_sw_aes_idle |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_aes_sideload |
chip_sw_keymgr_sideload_aes |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_adc_ctrl_debug_cable_irq |
chip_sw_adc_ctrl_sleep_debug_cable_wakeup |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_adc_ctrl_sleep_debug_cable_wakeup |
chip_sw_adc_ctrl_sleep_debug_cable_wakeup |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_aon_timer_wakeup_irq |
chip_sw_aon_timer_irq |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_aon_timer_sleep_wakeup |
chip_sw_pwrmgr_smoketest |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_aon_timer_wdog_bark_irq |
chip_sw_aon_timer_irq |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_aon_timer_wdog_bite_reset |
chip_sw_aon_timer_wdog_bite_reset |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_aon_timer_sleep_wdog_bite_reset |
chip_sw_aon_timer_wdog_bite_reset |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_aon_timer_sleep_wdog_sleep_pause |
chip_sw_aon_timer_sleep_wdog_sleep_pause |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_aon_timer_wdog_lc_escalate |
chip_sw_aon_timer_wdog_lc_escalate |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_clkmgr_idle_trans |
chip_sw_aes_idle |
|
|
0 |
0 |
-- |
|
|
chip_sw_hmac_enc_idle |
|
|
0 |
0 |
-- |
|
|
chip_sw_kmac_idle |
|
|
0 |
0 |
-- |
|
|
chip_sw_otbn_randomness |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_clkmgr_off_trans |
chip_sw_clkmgr_off_aes_trans |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_off_hmac_trans |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_off_kmac_trans |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_off_otbn_trans |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_clkmgr_off_peri |
chip_sw_clkmgr_off_peri |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_clkmgr_div |
chip_sw_ast_clk_outputs |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_clkmgr_external_clk_src_for_lc |
chip_sw_clkmgr_external_clk_src_for_lc |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_clkmgr_external_clk_src_for_sw |
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_clkmgr_jitter |
chip_sw_clkmgr_jitter |
|
|
0 |
0 |
-- |
|
|
chip_sw_flash_ctrl_ops_jitter_en |
|
|
0 |
0 |
-- |
|
|
chip_sw_flash_ctrl_access_jitter_en |
|
|
0 |
0 |
-- |
|
|
chip_sw_otbn_ecdsa_op_irq_jitter_en |
|
|
0 |
0 |
-- |
|
|
chip_sw_aes_enc_jitter_en |
|
|
0 |
0 |
-- |
|
|
chip_sw_hmac_enc_jitter_en |
|
|
0 |
0 |
-- |
|
|
chip_sw_keymgr_key_derivation_jitter_en |
|
|
0 |
0 |
-- |
|
|
chip_sw_kmac_mode_kmac_jitter_en |
|
|
0 |
0 |
-- |
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
|
|
0 |
0 |
-- |
|
|
chip_sw_edn_entropy_reqs_jitter |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_clkmgr_extended_range |
chip_sw_clkmgr_jitter_reduced_freq |
|
|
0 |
0 |
-- |
|
|
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq |
|
|
0 |
0 |
-- |
|
|
chip_sw_flash_ctrl_access_jitter_en_reduced_freq |
|
|
0 |
0 |
-- |
|
|
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq |
|
|
0 |
0 |
-- |
|
|
chip_sw_aes_enc_jitter_en_reduced_freq |
|
|
0 |
0 |
-- |
|
|
chip_sw_hmac_enc_jitter_en_reduced_freq |
|
|
0 |
0 |
-- |
|
|
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq |
|
|
0 |
0 |
-- |
|
|
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq |
|
|
0 |
0 |
-- |
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq |
|
|
0 |
0 |
-- |
|
|
chip_sw_flash_init_reduced_freq |
|
|
0 |
0 |
-- |
|
|
chip_sw_csrng_edn_concurrency_reduced_freq |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_clkmgr_deep_sleep_frequency |
chip_sw_ast_clk_outputs |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_clkmgr_sleep_frequency |
chip_sw_clkmgr_sleep_frequency |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_clkmgr_reset_frequency |
chip_sw_clkmgr_reset_frequency |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_clkmgr_escalation_reset |
chip_sw_all_escalation_resets |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_clkmgr_alert_handler_clock_enables |
chip_sw_alert_handler_lpg_clkoff |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_csrng_edn_cmd |
chip_sw_entropy_src_csrng |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_csrng_fuse_en_sw_app_read |
chip_sw_csrng_fuse_en_sw_app_read_test |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_csrng_lc_hw_debug_en |
chip_sw_csrng_lc_hw_debug_en_test |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_csrng_known_answer_tests |
chip_sw_csrng_kat_test |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sysrst_ctrl_reset |
chip_sw_pwrmgr_sysrst_ctrl_reset |
|
|
0 |
0 |
-- |
|
|
chip_sw_sysrst_ctrl_reset |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sysrst_ctrl_inputs |
chip_sw_sysrst_ctrl_inputs |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sysrst_ctrl_outputs |
chip_sw_sysrst_ctrl_outputs |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sysrst_ctrl_in_irq |
chip_sw_sysrst_ctrl_in_irq |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sysrst_ctrl_sleep_wakeup |
chip_sw_sysrst_ctrl_reset |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sysrst_ctrl_sleep_reset |
chip_sw_sysrst_ctrl_reset |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sysrst_ctrl_ec_rst_l |
chip_sw_sysrst_ctrl_ec_rst_l |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sysrst_ctrl_flash_wp_l |
chip_sw_sysrst_ctrl_ec_rst_l |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sysrst_ctrl_ulp_z3_wakeup |
chip_sw_adc_ctrl_sleep_debug_cable_wakeup |
|
|
0 |
0 |
-- |
|
|
chip_sw_sysrst_ctrl_ulp_z3_wakeup |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_edn_entropy_reqs |
chip_sw_edn_entropy_reqs |
|
|
0 |
0 |
-- |
|
|
chip_sw_csrng_edn_concurrency |
|
|
0 |
0 |
-- |
|
|
chip_sw_entropy_src_ast_rng_req |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_entropy_src_ast_rng_req |
chip_sw_entropy_src_ast_rng_req |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_entropy_src_csrng |
chip_sw_entropy_src_csrng |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_entropy_src_fuse_en_fw_read |
chip_sw_entropy_src_fuse_en_fw_read_test |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_entropy_src_known_answer_tests |
chip_sw_entropy_src_kat_test |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_entropy_src_fw_observe_many_contiguous |
chip_sw_entropy_src_fw_observe_many_contiguous |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_entropy_src_fw_extract_and_insert |
chip_sw_entropy_src_fw_extract_and_insert |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_init |
chip_sw_flash_init |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_host_access |
chip_sw_flash_ctrl_access |
|
|
0 |
0 |
-- |
|
|
chip_sw_flash_ctrl_access_jitter_en |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_ctrl_ops |
chip_sw_flash_ctrl_ops |
|
|
0 |
0 |
-- |
|
|
chip_sw_flash_ctrl_ops_jitter_en |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_rma_unlocked |
chip_sw_flash_rma_unlocked |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_scramble |
chip_sw_flash_init |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_idle_low_power |
chip_sw_flash_ctrl_idle_low_power |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_keymgr_seeds |
chip_sw_keymgr_key_derivation |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_lc_creator_seed_sw_rw_en |
chip_sw_flash_ctrl_lc_rw_en |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_creator_seed_wipe_on_rma |
chip_sw_flash_rma_unlocked |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_lc_owner_seed_sw_rw_en |
chip_sw_flash_ctrl_lc_rw_en |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_lc_iso_part_sw_rd_en |
chip_sw_flash_ctrl_lc_rw_en |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_lc_iso_part_sw_wr_en |
chip_sw_flash_ctrl_lc_rw_en |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_lc_seed_hw_rd_en |
chip_sw_flash_ctrl_lc_rw_en |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_lc_escalate_en |
chip_sw_all_escalation_resets |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_prim_tl_access |
chip_prim_tl_access |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_ctrl_clock_freqs |
chip_sw_flash_ctrl_clock_freqs |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_ctrl_escalation_reset |
chip_sw_flash_crash_alert |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_flash_ctrl_write_clear |
chip_sw_flash_crash_alert |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_hmac_enc |
chip_sw_hmac_enc |
|
|
0 |
0 |
-- |
|
|
chip_sw_hmac_enc_jitter_en |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_hmac_idle |
chip_sw_hmac_enc_idle |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_hmac_all_configurations |
chip_sw_hmac_oneshot |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_hmac_multistream_mode |
chip_sw_hmac_multistream |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_i2c_host_tx_rx |
chip_sw_i2c_host_tx_rx |
|
|
0 |
0 |
-- |
|
|
chip_sw_i2c_host_tx_rx_idx1 |
|
|
0 |
0 |
-- |
|
|
chip_sw_i2c_host_tx_rx_idx2 |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_i2c_device_tx_rx |
chip_sw_i2c_device_tx_rx |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_keymgr_key_derivation |
chip_sw_keymgr_key_derivation |
|
|
0 |
0 |
-- |
|
|
chip_sw_keymgr_key_derivation_jitter_en |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_keymgr_sideload_kmac |
chip_sw_keymgr_sideload_kmac |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_keymgr_sideload_aes |
chip_sw_keymgr_sideload_aes |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_keymgr_sideload_otbn |
chip_sw_keymgr_sideload_otbn |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_kmac_enc |
chip_sw_kmac_mode_cshake |
|
|
0 |
0 |
-- |
|
|
chip_sw_kmac_mode_kmac |
|
|
0 |
0 |
-- |
|
|
chip_sw_kmac_mode_kmac_jitter_en |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_kmac_app_keymgr |
chip_sw_keymgr_key_derivation |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_kmac_app_lc |
chip_sw_lc_ctrl_transition |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_kmac_app_rom |
chip_sw_kmac_app_rom |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_kmac_entropy |
chip_sw_kmac_entropy |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_kmac_idle |
chip_sw_kmac_idle |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_lc_ctrl_alert_handler_escalation |
chip_sw_alert_handler_escalation |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_lc_ctrl_jtag_access |
chip_tap_straps_dev |
|
|
0 |
0 |
-- |
|
|
chip_tap_straps_prod |
|
|
0 |
0 |
-- |
|
|
chip_tap_straps_rma |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_lc_ctrl_otp_hw_cfg0 |
chip_sw_lc_ctrl_otp_hw_cfg0 |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_lc_ctrl_init |
chip_sw_lc_ctrl_transition |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_lc_ctrl_transitions |
chip_sw_lc_ctrl_transition |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_lc_ctrl_kmac_req |
chip_sw_lc_ctrl_transition |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_lc_ctrl_key_div |
chip_sw_keymgr_key_derivation_prod |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_lc_ctrl_broadcast |
chip_prim_tl_access |
|
|
0 |
0 |
-- |
|
|
chip_tap_straps_dev |
|
|
0 |
0 |
-- |
|
|
chip_tap_straps_prod |
|
|
0 |
0 |
-- |
|
|
chip_tap_straps_rma |
|
|
0 |
0 |
-- |
|
|
chip_sw_rom_ctrl_integrity_check |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma |
|
|
0 |
0 |
-- |
|
|
chip_sw_sram_ctrl_execution_main |
|
|
0 |
0 |
-- |
|
|
chip_rv_dm_lc_disabled |
|
|
0 |
0 |
-- |
|
|
chip_sw_keymgr_key_derivation |
|
|
0 |
0 |
-- |
|
|
chip_sw_clkmgr_external_clk_src_for_lc |
|
|
0 |
0 |
-- |
|
|
chip_sw_flash_rma_unlocked |
|
|
0 |
0 |
-- |
|
|
chip_sw_lc_ctrl_transition |
|
|
0 |
0 |
-- |
|
|
chip_sw_flash_ctrl_lc_rw_en |
|
|
0 |
0 |
-- |
|
|
chip_sw_otp_ctrl_lc_signals_test_unlocked0 |
|
|
0 |
0 |
-- |
|
|
chip_sw_otp_ctrl_lc_signals_dev |
|
|
0 |
0 |
-- |
|
|
chip_sw_otp_ctrl_lc_signals_prod |
|
|
0 |
0 |
-- |
|
|
chip_sw_otp_ctrl_lc_signals_rma |
|
|
0 |
0 |
-- |
| V2 |
chip_lc_scrap |
chip_sw_lc_ctrl_rand_to_scrap |
|
|
0 |
0 |
-- |
|
|
chip_sw_lc_ctrl_raw_to_scrap |
|
|
0 |
0 |
-- |
|
|
chip_sw_lc_ctrl_rma_to_scrap |
|
|
0 |
0 |
-- |
|
|
chip_sw_lc_ctrl_test_locked0_to_scrap |
|
|
0 |
0 |
-- |
| V2 |
chip_lc_test_locked |
chip_sw_lc_walkthrough_testunlocks |
|
|
0 |
0 |
-- |
|
|
chip_rv_dm_lc_disabled |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_lc_walkthrough |
chip_sw_lc_walkthrough_dev |
|
|
0 |
0 |
-- |
|
|
chip_sw_lc_walkthrough_prod |
|
|
0 |
0 |
-- |
|
|
chip_sw_lc_walkthrough_prodend |
|
|
0 |
0 |
-- |
|
|
chip_sw_lc_walkthrough_rma |
|
|
0 |
0 |
-- |
|
|
chip_sw_lc_walkthrough_testunlocks |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_lc_ctrl_volatile_raw_unlock |
chip_sw_lc_ctrl_volatile_raw_unlock |
|
|
0 |
0 |
-- |
|
|
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz |
|
|
0 |
0 |
-- |
|
|
rom_volatile_raw_unlock |
|
|
0 |
0 |
-- |
| V2 |
chip_otp_ctrl_init |
chip_sw_lc_ctrl_transition |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_otp_ctrl_keys |
chip_sw_sram_ctrl_scrambled_access |
|
|
0 |
0 |
-- |
|
|
chip_sw_flash_init |
|
|
0 |
0 |
-- |
|
|
chip_sw_keymgr_key_derivation |
|
|
0 |
0 |
-- |
|
|
chip_sw_otbn_mem_scramble |
|
|
0 |
0 |
-- |
|
|
chip_sw_rv_core_ibex_icache_invalidate |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_otp_ctrl_entropy |
chip_sw_sram_ctrl_scrambled_access |
|
|
0 |
0 |
-- |
|
|
chip_sw_flash_init |
|
|
0 |
0 |
-- |
|
|
chip_sw_keymgr_key_derivation |
|
|
0 |
0 |
-- |
|
|
chip_sw_otbn_mem_scramble |
|
|
0 |
0 |
-- |
|
|
chip_sw_rv_core_ibex_icache_invalidate |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_otp_ctrl_program |
chip_sw_lc_ctrl_transition |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_otp_ctrl_program_error |
chip_sw_lc_ctrl_program_error |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_otp_ctrl_hw_cfg0 |
chip_sw_lc_ctrl_otp_hw_cfg0 |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_otp_ctrl_lc_signals |
chip_prim_tl_access |
|
|
0 |
0 |
-- |
|
|
chip_sw_lc_ctrl_transition |
|
|
0 |
0 |
-- |
|
|
chip_sw_otp_ctrl_lc_signals_test_unlocked0 |
|
|
0 |
0 |
-- |
|
|
chip_sw_otp_ctrl_lc_signals_dev |
|
|
0 |
0 |
-- |
|
|
chip_sw_otp_ctrl_lc_signals_prod |
|
|
0 |
0 |
-- |
|
|
chip_sw_otp_ctrl_lc_signals_rma |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_otp_prim_tl_access |
chip_prim_tl_access |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_otp_ctrl_dai_lock |
chip_sw_otp_ctrl_dai_lock |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_external_full_reset |
chip_sw_pwrmgr_full_aon_reset |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_random_sleep_all_wake_ups |
chip_sw_pwrmgr_random_sleep_all_wake_ups |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_normal_sleep_all_wake_ups |
chip_sw_pwrmgr_normal_sleep_all_wake_ups |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_deep_sleep_por_reset |
chip_sw_pwrmgr_deep_sleep_por_reset |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_normal_sleep_por_reset |
chip_sw_pwrmgr_normal_sleep_por_reset |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_deep_sleep_all_wake_ups |
chip_sw_pwrmgr_deep_sleep_all_wake_ups |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_deep_sleep_all_reset_reqs |
chip_sw_aon_timer_wdog_bite_reset |
|
|
0 |
0 |
-- |
|
|
chip_sw_pwrmgr_deep_sleep_all_reset_reqs |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_normal_sleep_all_reset_reqs |
chip_sw_pwrmgr_normal_sleep_all_reset_reqs |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_wdog_reset |
chip_sw_pwrmgr_wdog_reset |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_aon_power_glitch_reset |
chip_sw_pwrmgr_full_aon_reset |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_main_power_glitch_reset |
chip_sw_pwrmgr_main_power_glitch_reset |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_random_sleep_power_glitch_reset |
chip_sw_pwrmgr_random_sleep_power_glitch_reset |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_deep_sleep_power_glitch_reset |
chip_sw_pwrmgr_deep_sleep_power_glitch_reset |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_sleep_power_glitch_reset |
chip_sw_pwrmgr_sleep_power_glitch_reset |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_random_sleep_all_reset_reqs |
chip_sw_pwrmgr_random_sleep_all_reset_reqs |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_sysrst_ctrl_reset |
chip_sw_pwrmgr_sysrst_ctrl_reset |
|
|
0 |
0 |
-- |
|
|
chip_sw_pwrmgr_all_reset_reqs |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_b2b_sleep_reset_req |
chip_sw_pwrmgr_b2b_sleep_reset_req |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_sleep_disabled |
chip_sw_pwrmgr_sleep_disabled |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_pwrmgr_escalation_reset |
chip_sw_all_escalation_resets |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_rom_access |
chip_sw_rom_ctrl_integrity_check |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_rom_ctrl_integrity_check |
chip_sw_rom_ctrl_integrity_check |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_rstmgr_non_sys_reset_info |
chip_sw_pwrmgr_smoketest |
|
|
0 |
0 |
-- |
|
|
chip_sw_pwrmgr_random_sleep_all_reset_reqs |
|
|
0 |
0 |
-- |
|
|
chip_sw_pwrmgr_all_reset_reqs |
|
|
0 |
0 |
-- |
|
|
chip_sw_pwrmgr_wdog_reset |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_rstmgr_sys_reset_info |
chip_rv_dm_ndm_reset_req |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_rstmgr_cpu_info |
chip_sw_rstmgr_cpu_info |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_rstmgr_sw_req_reset |
chip_sw_rstmgr_sw_req |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_rstmgr_alert_info |
chip_sw_rstmgr_alert_info |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_rstmgr_sw_rst |
chip_sw_rstmgr_sw_rst |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_rstmgr_escalation_reset |
chip_sw_all_escalation_resets |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_rstmgr_alert_handler_reset_enables |
chip_sw_alert_handler_lpg_reset_toggle |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_plic_all_irqs |
chip_plic_all_irqs_0 |
|
|
0 |
0 |
-- |
|
|
chip_plic_all_irqs_10 |
|
|
0 |
0 |
-- |
|
|
chip_plic_all_irqs_20 |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_plic_sw_irq |
chip_sw_plic_sw_irq |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_timer |
chip_sw_rv_timer_irq |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_spi_device_flash_mode |
rom_e2e_smoke |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_spi_device_pass_through |
chip_sw_spi_device_pass_through |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_spi_device_pass_through_collision |
chip_sw_spi_device_pass_through_collision |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_spi_device_tpm |
chip_sw_spi_device_tpm |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_spi_host_tx_rx |
chip_sw_spi_host_tx_rx |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sram_scrambled_access |
chip_sw_sram_ctrl_scrambled_access |
|
|
0 |
0 |
-- |
|
|
chip_sw_sram_ctrl_scrambled_access_jitter_en |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sleep_sram_ret_contents |
chip_sw_sleep_sram_ret_contents_no_scramble |
|
|
0 |
0 |
-- |
|
|
chip_sw_sleep_sram_ret_contents_scramble |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sram_execution |
chip_sw_sram_ctrl_execution_main |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_sram_lc_escalation |
chip_sw_all_escalation_resets |
|
|
0 |
0 |
-- |
|
|
chip_sw_data_integrity_escalation |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_usbdev_mem |
chip_sw_usbdev_mem |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_usbdev_vbus |
chip_sw_usbdev_vbus |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_usbdev_pullup |
chip_sw_usbdev_pullup |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_usbdev_aon_pullup |
chip_sw_usbdev_aon_pullup |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_usbdev_sof |
chip_sw_usbdev_sof |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_usbdev_setup_rx |
chip_sw_usbdev_setuprx |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_usbdev_config_host |
chip_sw_usbdev_config_host |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_usbdev_pincfg |
chip_sw_usbdev_pincfg |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_usbdev_tx_rx |
chip_sw_usbdev_dpi |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_alert_handler_alerts |
chip_sw_alert_test |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_alert_handler_escalations |
chip_sw_alert_handler_escalation |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_alert_handler_escalation_nmi_reset |
chip_sw_alert_handler_escalation_nmi_reset |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_alert_handler_escalation_methods |
chip_sw_alert_handler_escalation_methods |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_all_escalation_resets |
chip_sw_all_escalation_resets |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_alert_handler_irqs |
chip_plic_all_irqs |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_alert_handler_entropy |
chip_sw_alert_handler_entropy |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_alert_handler_crashdump |
chip_sw_rstmgr_alert_info |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_alert_handler_ping_timeout |
chip_sw_alert_handler_ping_timeout |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_alert_handler_lpg_sleep_mode_alerts |
chip_sw_alert_handler_lpg_sleep_mode_alerts |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_alert_handler_lpg_sleep_mode_pings |
chip_sw_alert_handler_lpg_sleep_mode_pings |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_alert_handler_lpg_clock_off |
chip_sw_alert_handler_lpg_clkoff |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_alert_handler_lpg_reset_toggle |
chip_sw_alert_handler_lpg_reset_toggle |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_alert_handler_ping_ok |
chip_sw_alert_handler_ping_ok |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_alert_handler_reverse_ping_in_deep_sleep |
chip_sw_alert_handler_reverse_ping_in_deep_sleep |
|
|
0 |
0 |
-- |
| V2 |
chip_jtag_csr_rw |
chip_jtag_csr_rw |
|
|
0 |
0 |
-- |
| V2 |
chip_jtag_mem_access |
chip_jtag_mem_access |
|
|
0 |
0 |
-- |
| V2 |
chip_rv_dm_ndm_reset_req |
chip_rv_dm_ndm_reset_req |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted |
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted |
|
|
0 |
0 |
-- |
| V2 |
chip_rv_dm_access_after_wakeup |
chip_sw_rv_dm_access_after_wakeup |
|
|
0 |
0 |
-- |
| V2 |
chip_sw_rv_dm_jtag_tap_sel |
chip_tap_straps_rma |
|
|
0 |
0 |
-- |
| V2 |
chip_rv_dm_lc_disabled |
chip_rv_dm_lc_disabled |
|
|
0 |
0 |
-- |
| V2 |
chip_rv_dm_jtag |
chip_rv_dm_jtag |
|
|
0 |
0 |
-- |
| V2 |
chip_rv_dm_dtm |
chip_rv_dm_dtm |
|
|
0 |
0 |
-- |
| V2 |
chip_rv_dm_control_status |
chip_rv_dm_control_status |
|
|
0 |
0 |
-- |
| V2 |
|
TOTAL |
|
|
10 |
10 |
100.00 |
| V2S |
chip_sw_aes_masking_off |
chip_sw_aes_masking_off |
|
|
0 |
0 |
-- |
| V2S |
|
TOTAL |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_usb_suspend |
chip_sw_usb_suspend |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_coremark |
chip_sw_coremark |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_power_max_load |
chip_sw_power_virus |
|
|
0 |
0 |
-- |
| V3 |
rom_e2e_debug |
rom_e2e_jtag_debug_test_unlocked0 |
|
|
0 |
0 |
-- |
|
|
rom_e2e_jtag_debug_dev |
|
|
0 |
0 |
-- |
|
|
rom_e2e_jtag_debug_rma |
|
|
0 |
0 |
-- |
| V3 |
rom_e2e_jtag_inject |
rom_e2e_jtag_inject_test_unlocked0 |
|
|
0 |
0 |
-- |
|
|
rom_e2e_jtag_inject_dev |
|
|
0 |
0 |
-- |
|
|
rom_e2e_jtag_inject_rma |
|
|
0 |
0 |
-- |
| V3 |
rom_bootstrap_rma |
rom_bootstrap_rma |
|
|
0 |
0 |
-- |
| V3 |
rom_e2e_weak_straps |
rom_e2e_weak_straps |
|
|
0 |
0 |
-- |
| V3 |
rom_e2e_self_hash |
rom_e2e_self_hash |
|
|
0 |
0 |
-- |
| V3 |
manuf_cp_unlock_raw |
manuf_cp_unlock_raw |
|
|
0 |
0 |
-- |
| V3 |
manuf_scrap |
manuf_scrap |
|
|
0 |
0 |
-- |
| V3 |
manuf_cp_yield_test |
manuf_cp_yield_test |
|
|
0 |
0 |
-- |
| V3 |
manuf_cp_ast_test_execution |
manuf_cp_ast_test_execution |
|
|
0 |
0 |
-- |
| V3 |
manuf_cp_device_info_flash_wr |
manuf_cp_device_info_flash_wr |
|
|
0 |
0 |
-- |
| V3 |
manuf_cp_test_lock |
manuf_cp_test_lock |
|
|
0 |
0 |
-- |
| V3 |
manuf_ft_exit_token |
manuf_ft_exit_token |
|
|
0 |
0 |
-- |
| V3 |
manuf_ft_sku_individualization_preop |
manuf_ft_sku_individualization_preop |
|
|
0 |
0 |
-- |
| V3 |
manuf_ft_sku_individualization |
manuf_ft_sku_individualization |
|
|
0 |
0 |
-- |
| V3 |
manuf_ft_provision_rma_token_and_personalization |
manuf_ft_provision_rma_token_and_personalization |
|
|
0 |
0 |
-- |
| V3 |
manuf_ft_load_transport_image |
manuf_ft_load_transport_image |
|
|
0 |
0 |
-- |
| V3 |
manuf_ft_load_certificates |
manuf_ft_load_certificates |
|
|
0 |
0 |
-- |
| V3 |
manuf_ft_eom |
manuf_ft_eom |
|
|
0 |
0 |
-- |
| V3 |
manuf_rma_entry |
manuf_rma_entry |
|
|
0 |
0 |
-- |
| V3 |
manuf_sram_program_crc_functest |
manuf_sram_program_crc_functest |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_adc_ctrl_normal |
chip_sw_adc_ctrl_normal |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_adc_ctrl_oneshot |
chip_sw_adc_ctrl_oneshot |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_clkmgr_jitter_cycle_measurements |
chip_sw_clkmgr_jitter_frequency |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_edn_boot_mode |
chip_sw_edn_boot_mode |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_edn_auto_mode |
chip_sw_edn_auto_mode |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_edn_sw_mode |
chip_sw_edn_sw_mode |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_edn_kat |
chip_sw_edn_kat |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_entropy_src_bypass_mode_health_tests |
chip_sw_entropy_src_bypass_mode_health_tests |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_entropy_src_fips_mode_health_tests |
chip_sw_entropy_src_fips_mode_health_tests |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_entropy_src_validation |
chip_sw_entropy_src_validation |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_flash_memory_protection |
chip_sw_flash_ctrl_mem_protection |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_hmac_sha2_stress |
chip_sw_hmac_sha2_stress |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_hmac_stress |
chip_sw_hmac_stress |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_hmac_endianness |
chip_sw_hmac_endianness |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_hmac_secure_wipe |
chip_sw_hmac_secure_wipe |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_hmac_error_conditions |
chip_sw_hmac_error_conditions |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_i2c_speed |
chip_sw_i2c_speed |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_i2c_override |
chip_sw_i2c_override |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_i2c_clockstretching |
chip_sw_i2c_clockstretching |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_i2c_nack |
chip_sw_i2c_nack |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_i2c_repeatedstart |
chip_sw_i2c_repeatedstart |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_keymgr_sideload_kmac_error |
chip_sw_keymgr_sideload_kmac_error |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_keymgr_derive_attestation |
chip_sw_keymgr_derive_attestation |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_keymgr_derive_sealing |
chip_sw_keymgr_derive_sealing |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_kmac_sha3_stress |
chip_sw_kmac_sha3_stress |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_kmac_shake_stress |
chip_sw_kmac_shake_stress |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_kmac_cshake_stress |
chip_sw_kmac_cshake_stress |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_kmac_kmac_stress |
chip_sw_kmac_kmac_stress |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_kmac_kmac_key_sideload |
chip_sw_kmac_kmac_key_sideload |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_kmac_endianess |
chip_sw_kmac_endianess |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_kmac_entropy_stress |
chip_sw_kmac_entropy_stress |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_kmac_error_conditions |
chip_sw_kmac_error_conditions |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_lc_ctrl_kmac_error |
chip_sw_lc_ctrl_kmac_error |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_lc_ctrl_debug_access |
chip_sw_lc_ctrl_debug_access |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_otp_ctrl_vendor_test_csr_access |
chip_sw_otp_ctrl_vendor_test_csr_access |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_otp_ctrl_escalation |
chip_sw_otp_ctrl_escalation |
|
|
0 |
0 |
-- |
| V3 |
otp_ctrl_calibration |
otp_ctrl_calibration |
|
|
0 |
0 |
-- |
| V3 |
otp_ctrl_partition_access_locked |
otp_ctrl_partition_access_locked |
|
|
0 |
0 |
-- |
| V3 |
otp_ctrl_check_timeout |
otp_ctrl_check_timeout |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_sensor_ctrl_deep_sleep_wake_up |
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_pwrmgr_usb_clk_disabled_when_active |
chip_sw_pwrmgr_usb_clk_disabled_when_active |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_all_resets |
chip_sw_pwrmgr_all_reset_reqs |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_rom_ctrl_kmac_error |
chip_sw_rom_ctrl_kmac_error |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_rom_ctrl_digests |
chip_sw_rom_ctrl_digests |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_plic_alerts |
chip_sw_all_escalation_resets |
|
|
0 |
0 |
-- |
| V3 |
tick_configuration |
chip_sw_rv_timer_systick_test |
|
|
0 |
0 |
-- |
| V3 |
counter_wrap |
chip_sw_rv_timer_systick_test |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_spi_device_pass_through_flash_model |
//sw/device/tests:spi_passthru_test |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_spi_device_output_when_disabled_or_sleeping |
chip_sw_spi_device_pinmux_sleep_retention |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_spi_host_pass_through |
//sw/device/tests:spi_passthru_test |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_spi_host_configuration |
//sw/device/tests:spi_host_config_test |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_spi_host_events |
chip_sw_spi_host_events |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_sram_memset |
chip_sw_sram_memset |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_sram_readback |
chip_sw_sram_readback |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_sram_subword_access |
chip_sw_sram_subword_access |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_uart_parity |
chip_sw_uart_parity |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_uart_line_loopback |
chip_sw_uart_line_loopback |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_uart_system_loopback |
chip_sw_uart_system_loopback |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_uart_line_break |
chip_sw_uart_line_break |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_uart_watermarks |
chip_sw_uart_tx_rx |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_usbdev_stream |
chip_sw_usbdev_stream |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_usbdev_iso |
chip_sw_usbdev_iso |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_usbdev_mixed |
chip_sw_usbdev_mixed |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_usbdev_suspend_resume |
chip_sw_usbdev_suspend_resume |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_usbdev_aon_wake_reset |
chip_sw_usbdev_aon_wake_reset |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_usbdev_aon_wake_disconnect |
chip_sw_usbdev_aon_wake_disconnect |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_usbdev_toggle_restore |
chip_sw_usbdev_toggle_restore |
|
|
0 |
0 |
-- |
| V3 |
chip_rv_dm_perform_debug |
rom_e2e_jtag_debug_test_unlocked0 |
|
|
0 |
0 |
-- |
|
|
rom_e2e_jtag_debug_dev |
|
|
0 |
0 |
-- |
|
|
rom_e2e_jtag_debug_rma |
|
|
0 |
0 |
-- |
| V3 |
chip_sw_rv_dm_access_after_hw_reset |
chip_sw_rv_dm_access_after_escalation_reset |
|
|
0 |
0 |
-- |
| V3 |
|
TOTAL |
|
|
0 |
0 |
-- |
|
|
TOTAL |
|
|
10 |
10 |
100.00 |