Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	146077	1			T71	78		T72	3		T73	6
values[2]	10425	1			T71	3		T73	1		T131	6
values[3]	3909	1			T131	1		T552	26		T560	1
values[4]	2190	1			T552	8		T560	1		T726	22
values[5]	1229	1			T552	8		T560	1		T726	15
values[6]	900	1			T552	2		T560	1		T505	19
values[7]	697	1			T560	1		T505	11		T885	1
values[8]	514	1			T560	1		T505	9		T885	1
values[9]	488	1			T560	1		T505	12		T885	1
values[10]	437	1			T560	1		T505	13		T885	1
values[11]	369	1			T560	1		T505	14		T885	1
values[12]	386	1			T560	1		T505	9		T885	1
values[13]	376	1			T560	1		T505	8		T885	1
values[14]	367	1			T560	1		T505	8		T885	1
values[15]	388	1			T560	1		T505	7		T885	1
values[16]	335	1			T560	1		T505	3		T885	1
values[17]	363	1			T560	1		T505	5		T885	1
values[18]	306	1			T560	1		T505	6		T885	1
values[19]	331	1			T560	1		T505	3		T885	1
values[20]	361	1			T560	1		T505	4		T885	1
values[21]	316	1			T560	1		T505	5		T885	1
values[22]	334	1			T560	1		T505	3		T885	1
values[23]	305	1			T560	1		T505	5		T885	1
values[24]	339	1			T560	1		T505	2		T885	1
values[25]	325	1			T560	1		T505	4		T885	1
values[26]	281	1			T560	1		T505	7		T885	1
values[27]	249	1			T560	1		T505	2		T885	1
values[28]	293	1			T560	1		T505	2		T885	1
values[29]	305	1			T560	1		T505	10		T885	1
values[30]	298	1			T560	1		T505	10		T885	1
values[31]	283	1			T560	1		T505	17		T885	1
values[32]	318	1			T560	1		T505	9		T885	1
values[33]	345	1			T560	1		T505	18		T885	1
values[34]	313	1			T560	1		T505	2		T885	1
values[35]	314	1			T560	1		T505	3		T885	1
values[36]	292	1			T560	1		T505	3		T885	1
values[37]	292	1			T560	1		T505	5		T885	1
values[38]	312	1			T560	1		T505	3		T885	1
values[39]	260	1			T560	1		T505	2		T885	1
values[40]	278	1			T560	1		T505	4		T885	1
values[41]	292	1			T560	1		T505	5		T885	1
values[42]	305	1			T560	1		T505	2		T885	1
values[43]	257	1			T560	1		T505	3		T885	1
values[44]	287	1			T560	1		T505	7		T885	1
values[45]	266	1			T560	1		T505	5		T885	1
values[46]	283	1			T560	1		T505	3		T885	1
values[47]	273	1			T560	1		T505	2		T885	1
values[48]	269	1			T560	1		T505	2		T885	1
values[49]	267	1			T560	1		T505	1		T885	1
values[50]	285	1			T560	1		T505	4		T885	1
values[51]	282	1			T560	1		T505	6		T885	1
values[52]	240	1			T560	1		T505	2		T885	2
values[53]	231	1			T560	1		T505	1		T885	1
values[54]	230	1			T560	1		T505	2		T885	1
values[55]	227	1			T560	1		T505	5		T885	1
values[56]	253	1			T560	1		T505	5		T885	1
values[57]	233	1			T560	1		T505	2		T885	1
values[58]	243	1			T560	1		T505	1		T885	1
values[59]	234	1			T560	1		T505	4		T885	1
values[60]	202	1			T560	1		T505	2		T885	1
values[61]	212	1			T560	1		T505	3		T885	1
values[62]	164	1			T560	1		T505	1		T885	1
values[63]	203	1			T560	1		T505	4		T885	1
values[64]	213	1			T560	1		T505	10		T885	1
values[65]	222	1			T560	1		T505	6		T885	1
values[66]	205	1			T560	1		T505	5		T885	1
values[67]	231	1			T560	1		T505	5		T885	1
values[68]	195	1			T560	1		T505	7		T885	1
values[69]	192	1			T560	1		T505	2		T885	1
values[70]	169	1			T560	1		T505	6		T885	1
values[71]	152	1			T560	1		T505	2		T885	1
values[72]	156	1			T560	1		T505	1		T885	1
values[73]	123	1			T560	1		T505	2		T885	1
values[74]	118	1			T560	1		T505	1		T885	1
values[75]	120	1			T560	1		T505	2		T885	1
values[76]	115	1			T560	1		T505	4		T885	1
values[77]	87	1			T560	1		T505	2		T885	1
values[78]	96	1			T560	1		T505	2		T885	1
values[79]	101	1			T560	1		T505	3		T885	1
values[80]	102	1			T560	1		T505	11		T885	1
values[81]	79	1			T560	1		T505	6		T885	1
values[82]	90	1			T560	1		T505	5		T885	1
values[83]	91	1			T560	1		T505	5		T885	1
values[84]	101	1			T560	1		T505	6		T885	1
values[85]	109	1			T560	1		T505	5		T885	1
values[86]	98	1			T560	1		T505	2		T885	1
values[87]	94	1			T560	3		T505	1		T885	1
values[88]	86	1			T560	3		T505	2		T885	1
values[89]	93	1			T560	3		T505	1		T885	1
values[90]	113	1			T560	3		T505	1		T885	1
values[91]	98	1			T560	2		T505	3		T885	1
values[92]	109	1			T560	3		T505	2		T885	1
values[93]	113	1			T560	9		T505	7		T885	1
values[94]	95	1			T560	3		T505	8		T885	1
values[95]	97	1			T560	1		T505	8		T885	1
values[96]	97	1			T560	2		T505	14		T885	1
values[97]	100	1			T560	1		T505	4		T885	1
values[98]	99	1			T560	8		T505	2		T885	1
values[99]	92	1			T560	4		T505	7		T885	1
values[100]	94	1			T560	3		T505	3		T885	1
values[101]	89	1			T560	2		T505	1		T885	1
values[102]	91	1			T560	2		T505	3		T885	1
values[103]	87	1			T560	3		T505	1		T885	1
values[104]	104	1			T560	6		T505	2		T885	1
values[105]	77	1			T560	4		T505	3		T885	1
values[106]	72	1			T560	1		T505	3		T885	1
values[107]	82	1			T560	2		T505	4		T885	1
values[108]	89	1			T560	5		T505	8		T885	1
values[109]	103	1			T560	6		T505	6		T885	1
values[110]	85	1			T560	1		T505	11		T885	1
values[111]	110	1			T560	2		T505	16		T885	1
values[112]	107	1			T560	3		T505	11		T885	1
values[113]	86	1			T560	1		T505	3		T885	1
values[114]	90	1			T560	3		T505	2		T885	1
values[115]	103	1			T560	1		T505	6		T885	1
values[116]	68	1			T560	1		T505	2		T885	1
values[117]	73	1			T560	2		T505	2		T885	1
values[118]	86	1			T560	5		T505	4		T885	1
values[119]	86	1			T560	5		T505	1		T885	1
values[120]	73	1			T560	2		T505	2		T885	1
values[121]	85	1			T560	2		T505	3		T885	1
values[122]	70	1			T560	2		T505	3		T885	1
values[123]	88	1			T560	3		T505	5		T885	1
values[124]	78	1			T560	2		T505	7		T885	2
values[125]	110	1			T560	1		T505	5		T885	1
values[126]	217	1			T560	3		T505	13		T885	6
values[127]	893	1			T560	30		T505	26		T885	36
values[128]	6595	1			T560	268		T505	17		T885	305