Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.20	95.54	94.20	95.34		95.05	97.53	99.52

Total tests in report: 2943

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.54	39.54	44.96	44.96	43.00	43.00	31.60	31.60			57.86	57.86	59.44	59.44	0.39	0.39	/workspace/coverage/default/5.chip_sw_all_escalation_resets.2795141087
48.96	9.42	50.68	5.72	58.66	15.67	32.00	0.40			68.36	10.50	82.52	23.08	1.56	1.17	/workspace/coverage/cover_reg_top/17.chip_csr_rw.3710489270
55.40	6.44	61.13	10.45	61.74	3.08	38.55	6.56			69.40	1.04	82.52	0.00	19.06	17.50	/workspace/coverage/cover_reg_top/37.xbar_stress_all.1324996543
60.28	4.88	71.89	10.76	68.67	6.94	40.67	2.12			78.87	9.48	82.52	0.00	19.06	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.3000670873
64.17	3.89	71.89	0.00	68.68	0.01	40.67	0.00			78.87	0.00	82.52	0.00	42.39	23.33	/workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.2600239791
67.67	3.50	76.29	4.40	70.84	2.16	49.29	8.62			80.66	1.78	86.54	4.02	42.39	0.00	/workspace/coverage/default/2.chip_sw_power_virus.587022283
70.28	2.61	78.78	2.49	73.85	3.00	56.56	7.27			83.01	2.35	87.06	0.52	42.39	0.00	/workspace/coverage/default/2.rom_e2e_self_hash.3766307634
72.83	2.56	83.74	4.96	77.69	3.84	59.88	3.32			84.67	1.66	88.64	1.57	42.39	0.00	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2422837402
75.36	2.53	83.74	0.00	77.69	0.01	59.88	0.00			84.67	0.00	88.64	0.00	57.55	15.16	/workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.98870203
77.64	2.28	83.74	0.00	77.69	0.00	73.55	13.67			84.67	0.00	88.64	0.00	57.55	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3094056722
79.45	1.81	83.74	0.00	77.83	0.14	73.55	0.00			84.69	0.02	88.64	0.00	68.24	10.69	/workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.3736345466
81.08	1.63	85.80	2.06	79.63	1.80	75.24	1.69			86.36	1.67	90.73	2.10	68.70	0.46	/workspace/coverage/default/2.chip_jtag_csr_rw.4075856808
82.66	1.59	86.09	0.29	79.78	0.15	83.97	8.73			86.54	0.18	90.91	0.17	68.70	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1415314010
84.06	1.39	86.09	0.00	79.83	0.05	83.97	0.00			86.54	0.00	90.91	0.00	77.01	8.31	/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3388515011
85.23	1.18	86.09	0.00	79.86	0.02	83.97	0.00			86.54	0.00	90.91	0.00	84.04	7.04	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.1873760358
86.37	1.14	88.14	2.05	81.85	2.00	84.37	0.40			88.92	2.39	90.91	0.00	84.04	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.3469324648
87.32	0.95	89.33	1.19	82.63	0.77	85.52	1.15			89.88	0.96	92.48	1.57	84.09	0.05	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1982254544
88.19	0.87	90.67	1.34	84.51	1.89	85.67	0.15			91.72	1.83	92.48	0.00	84.09	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2784896510
88.92	0.73	90.96	0.29	84.63	0.12	85.68	0.01			91.83	0.11	96.33	3.85	84.09	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.571863573
89.60	0.68	90.96	0.00	84.63	0.00	85.68	0.00			91.83	0.00	96.33	0.00	88.14	4.05	/workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.3725216523
90.11	0.51	90.96	0.01	84.79	0.16	86.39	0.71			91.86	0.03	96.33	0.00	90.32	2.17	/workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.1971908150
90.53	0.42	91.78	0.82	85.62	0.83	86.63	0.24			92.45	0.58	96.33	0.00	90.37	0.05	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.808823475
90.94	0.41	91.79	0.01	87.68	2.07	86.63	0.00			92.45	0.00	96.33	0.00	90.76	0.40	/workspace/coverage/cover_reg_top/12.chip_tl_errors.1945187114
91.33	0.39	91.81	0.02	87.72	0.04	87.36	0.73			92.45	0.00	96.33	0.00	92.30	1.54	/workspace/coverage/default/1.chip_sw_alert_test.3353519822
91.65	0.32	92.63	0.82	88.17	0.44	87.63	0.27			92.83	0.38	96.33	0.00	92.30	0.00	/workspace/coverage/default/2.chip_sw_gpio.3368522160
91.96	0.31	92.63	0.00	88.54	0.37	87.63	0.00			92.88	0.05	96.33	0.00	93.77	1.47	/workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.1304061264
92.24	0.27	93.14	0.51	89.00	0.46	87.84	0.22			93.34	0.46	96.33	0.00	93.77	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.3661476053
92.47	0.23	93.14	0.00	89.00	0.00	87.84	0.00			93.34	0.00	96.33	0.00	95.17	1.40	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3724978789
92.70	0.23	93.14	0.00	89.04	0.05	87.84	0.00			93.34	0.00	96.33	0.00	96.52	1.35	/workspace/coverage/cover_reg_top/56.xbar_random_large_delays.332482913
92.92	0.21	93.14	0.00	89.04	0.00	89.13	1.29			93.34	0.00	96.33	0.00	96.52	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1912031896
93.09	0.18	93.41	0.27	89.73	0.69	89.13	0.01			93.45	0.11	96.33	0.00	96.52	0.00	/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.4130156650
93.25	0.15	93.42	0.01	89.73	0.01	90.03	0.90			93.45	0.00	96.33	0.00	96.52	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1683748036
93.40	0.15	93.46	0.04	90.13	0.40	90.06	0.03			93.88	0.43	96.33	0.00	96.52	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.399825295
93.54	0.15	93.66	0.21	90.45	0.32	90.42	0.36			93.88	0.00	96.33	0.00	96.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.56405673
93.68	0.13	93.66	0.00	90.80	0.35	90.42	0.00			93.91	0.03	96.33	0.00	96.95	0.42	/workspace/coverage/cover_reg_top/81.xbar_stress_all.1487170890
93.81	0.13	93.68	0.01	90.87	0.06	90.91	0.49			93.94	0.02	96.50	0.17	96.95	0.00	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.4009090730
93.92	0.12	93.73	0.06	90.90	0.03	91.51	0.59			93.96	0.02	96.50	0.00	96.95	0.00	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.618082728
94.03	0.11	93.73	0.00	90.90	0.00	92.16	0.65			93.96	0.00	96.50	0.00	96.95	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.4264546333
94.14	0.11	93.73	0.00	90.95	0.05	92.16	0.00			93.96	0.00	96.50	0.00	97.53	0.59	/workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.2672059678
94.24	0.10	93.87	0.14	91.14	0.19	92.23	0.07			94.17	0.21	96.50	0.00	97.54	0.01	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4167164466
94.35	0.10	93.87	0.00	91.75	0.62	92.23	0.00			94.17	0.00	96.50	0.00	97.54	0.00	/workspace/coverage/cover_reg_top/23.chip_tl_errors.3199304601
94.43	0.08	93.87	0.00	91.75	0.00	92.70	0.48			94.17	0.00	96.50	0.00	97.54	0.00	/workspace/coverage/default/0.chip_sw_all_escalation_resets.2032375134
94.50	0.08	93.87	0.00	91.75	0.00	92.70	0.00			94.17	0.00	96.50	0.00	98.00	0.46	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.3565451797
94.58	0.08	93.87	0.00	91.75	0.00	93.16	0.46			94.17	0.00	96.50	0.00	98.00	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.68550076
94.65	0.07	94.01	0.13	91.86	0.10	93.24	0.08			94.28	0.11	96.50	0.00	98.00	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.237230514
94.72	0.07	94.01	0.00	92.04	0.19	93.25	0.01			94.49	0.21	96.50	0.00	98.00	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3676659456
94.78	0.06	94.01	0.00	92.16	0.12	93.25	0.00			94.52	0.03	96.50	0.00	98.23	0.22	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.1174263828
94.84	0.06	94.11	0.11	92.30	0.14	93.29	0.04			94.60	0.08	96.50	0.00	98.23	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.138050510
94.89	0.05	94.11	0.00	92.30	0.00	93.62	0.32			94.60	0.00	96.50	0.00	98.23	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1624929982
94.94	0.05	94.14	0.03	92.33	0.03	93.62	0.01			94.65	0.05	96.68	0.17	98.24	0.01	/workspace/coverage/default/42.chip_sw_all_escalation_resets.4074531658
94.99	0.05	94.31	0.17	92.35	0.02	93.71	0.09			94.65	0.00	96.68	0.00	98.24	0.00	/workspace/coverage/default/3.chip_sw_uart_tx_rx.2788011419
95.03	0.04	94.31	0.00	92.61	0.25	93.71	0.00			94.65	0.00	96.68	0.00	98.25	0.01	/workspace/coverage/cover_reg_top/15.chip_tl_errors.1026570267
95.08	0.04	94.43	0.12	92.61	0.01	93.84	0.13			94.65	0.00	96.68	0.00	98.25	0.00	/workspace/coverage/cover_reg_top/3.xbar_error_random.2896813645
95.12	0.04	94.45	0.02	92.62	0.01	93.86	0.01			94.66	0.01	96.85	0.17	98.26	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.1280022266
95.16	0.04	94.45	0.00	92.62	0.00	94.09	0.23			94.66	0.00	96.85	0.00	98.26	0.00	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.4107116534
95.19	0.04	94.49	0.03	92.73	0.11	94.09	0.00			94.73	0.07	96.85	0.00	98.26	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3741695782
95.23	0.04	94.51	0.03	92.74	0.01	94.09	0.01			94.74	0.01	97.03	0.17	98.26	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2043461951
95.27	0.04	94.52	0.01	92.75	0.01	94.09	0.00			94.75	0.01	97.20	0.17	98.27	0.01	/workspace/coverage/default/48.chip_sw_all_escalation_resets.1004497580
95.30	0.04	94.52	0.01	92.76	0.01	94.10	0.01			94.76	0.01	97.38	0.17	98.28	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3992299888
95.34	0.04	94.52	0.00	92.76	0.00	94.14	0.04			94.76	0.00	97.55	0.17	98.28	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.670696592
95.37	0.03	94.52	0.00	92.76	0.00	94.33	0.20			94.76	0.00	97.55	0.00	98.28	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1114096698
95.40	0.03	94.52	0.00	92.94	0.18	94.33	0.00			94.76	0.00	97.55	0.00	98.28	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2515178092
95.43	0.03	94.60	0.07	92.97	0.03	94.35	0.01			94.81	0.05	97.55	0.00	98.28	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2178907775
95.45	0.03	94.67	0.07	92.97	0.00	94.42	0.07			94.82	0.01	97.55	0.00	98.28	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.3098555754
95.48	0.03	94.72	0.05	93.04	0.07	94.42	0.00			94.85	0.03	97.55	0.00	98.28	0.00	/workspace/coverage/cover_reg_top/10.chip_csr_rw.4052224634
95.50	0.02	94.79	0.07	93.09	0.05	94.42	0.00			94.88	0.03	97.55	0.00	98.28	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.987738256
95.53	0.02	94.81	0.02	93.16	0.07	94.42	0.00			94.93	0.05	97.55	0.00	98.28	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2176072631
95.55	0.02	94.81	0.00	93.30	0.14	94.42	0.00			94.93	0.00	97.55	0.00	98.28	0.00	/workspace/coverage/cover_reg_top/19.chip_tl_errors.2746948262
95.57	0.02	94.88	0.07	93.35	0.05	94.42	0.00			94.95	0.02	97.55	0.00	98.28	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.579459663
95.59	0.02	94.88	0.01	93.35	0.00	94.53	0.11			94.96	0.01	97.55	0.00	98.28	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1779382064
95.61	0.02	94.88	0.00	93.35	0.01	94.53	0.00			94.96	0.00	97.55	0.00	98.40	0.12	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.4110169322
95.63	0.02	94.88	0.00	93.35	0.00	94.65	0.12			94.96	0.00	97.55	0.00	98.40	0.00	/workspace/coverage/default/0.chip_sw_power_sleep_load.2570450937
95.65	0.02	94.88	0.00	93.42	0.07	94.65	0.00			94.96	0.00	97.55	0.00	98.44	0.04	/workspace/coverage/cover_reg_top/5.xbar_stress_all.3800456843
95.67	0.02	94.88	0.00	93.42	0.00	94.75	0.10			94.96	0.00	97.55	0.00	98.44	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2534115767
95.68	0.02	94.90	0.02	93.46	0.03	94.76	0.02			94.99	0.02	97.55	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3896349886
95.70	0.01	94.90	0.00	93.46	0.00	94.85	0.09			94.99	0.00	97.55	0.00	98.44	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3593563391
95.71	0.01	94.90	0.00	93.47	0.02	94.85	0.00			94.99	0.00	97.55	0.00	98.51	0.07	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.1819849399
95.73	0.01	94.90	0.00	93.56	0.08	94.85	0.00			94.99	0.00	97.55	0.00	98.51	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1606063759
95.74	0.01	94.91	0.01	93.60	0.04	94.85	0.00			95.02	0.03	97.55	0.00	98.51	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2145063468
95.75	0.01	94.91	0.00	93.61	0.01	94.85	0.00			95.02	0.00	97.55	0.00	98.57	0.06	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.3298125345
95.76	0.01	94.91	0.00	93.61	0.00	94.93	0.07			95.02	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.467760023
95.77	0.01	94.91	0.00	93.67	0.06	94.93	0.00			95.02	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.272261083
95.78	0.01	94.91	0.00	93.68	0.01	94.93	0.00			95.02	0.00	97.55	0.00	98.61	0.05	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.3754824258
95.79	0.01	94.93	0.02	93.69	0.01	94.93	0.01			95.03	0.02	97.55	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2523229249
95.80	0.01	94.93	0.00	93.69	0.00	94.93	0.00			95.03	0.00	97.55	0.00	98.66	0.05	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1339924993
95.81	0.01	94.93	0.00	93.69	0.00	94.97	0.05			95.03	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2704697268
95.81	0.01	94.93	0.00	93.73	0.05	94.97	0.00			95.03	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/18.chip_tl_errors.1034041212
95.82	0.01	94.93	0.00	93.75	0.02	94.97	0.00			95.03	0.00	97.55	0.00	98.68	0.02	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.2711623841
95.83	0.01	94.94	0.01	93.78	0.02	94.98	0.01			95.03	0.00	97.55	0.00	98.68	0.00	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2059465156
95.84	0.01	94.95	0.01	93.79	0.01	95.00	0.02			95.03	0.00	97.55	0.00	98.68	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2360187268
95.84	0.01	94.95	0.00	93.79	0.00	95.04	0.04			95.03	0.00	97.55	0.00	98.68	0.00	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1305312234
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96.06	0.01	94.95	0.00	94.06	0.00	95.24	0.00			95.03	0.00	97.55	0.00	99.51	0.01	/workspace/coverage/default/97.chip_sw_all_escalation_resets.2591319193
96.06	0.01	94.95	0.00	94.06	0.00	95.24	0.00			95.03	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/98.chip_sw_all_escalation_resets.2053248979
96.06	0.01	94.95	0.00	94.07	0.01	95.24	0.00			95.03	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3547244380
96.06	0.01	94.96	0.01	94.07	0.00	95.25	0.01			95.03	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/4.chip_sw_all_escalation_resets.122935670
96.07	0.01	94.96	0.00	94.07	0.00	95.26	0.01			95.03	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2118127131
96.07	0.01	94.96	0.00	94.07	0.00	95.27	0.01			95.03	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.194207069
96.07	0.01	94.96	0.00	94.07	0.00	95.28	0.01			95.03	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1388438146
96.07	0.01	94.96	0.00	94.07	0.00	95.29	0.01			95.03	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.836202391
96.07	0.01	94.96	0.00	94.07	0.00	95.29	0.00			95.04	0.01	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3400362633
96.07	0.01	94.96	0.00	94.07	0.00	95.29	0.00			95.05	0.01	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.1017871518
96.07	0.01	94.96	0.00	94.08	0.01	95.29	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/0.xbar_stress_all.883151822
96.08	0.01	94.96	0.00	94.09	0.01	95.29	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1169583447
96.08	0.01	94.96	0.00	94.10	0.01	95.29	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.361941706
96.08	0.01	94.96	0.00	94.10	0.01	95.29	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.634990448
96.08	0.01	94.96	0.00	94.11	0.01	95.29	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.259189008
96.08	0.01	94.96	0.00	94.12	0.01	95.29	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.1225443076
96.08	0.01	94.96	0.00	94.12	0.01	95.29	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_gpio.2740689998
96.08	0.01	94.96	0.00	94.13	0.01	95.29	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2743527689
96.08	0.01	94.96	0.00	94.14	0.01	95.29	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1720002093
96.09	0.01	94.96	0.00	94.14	0.01	95.29	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1472223838
96.09	0.01	94.96	0.00	94.15	0.01	95.29	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2549633585
96.09	0.01	94.96	0.00	94.15	0.00	95.29	0.01			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.449779002
96.09	0.01	94.96	0.00	94.15	0.00	95.30	0.01			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3526467010
96.09	0.01	94.96	0.01	94.15	0.00	95.30	0.01			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1630886635
96.09	0.01	94.96	0.00	94.15	0.00	95.31	0.01			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.568915840
96.09	0.01	94.96	0.00	94.15	0.00	95.31	0.01			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_kmac_idle.3114571442
96.09	0.01	94.96	0.00	94.15	0.00	95.32	0.01			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2868061506
96.09	0.01	94.96	0.00	94.15	0.00	95.32	0.01			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2874739709
96.09	0.01	94.96	0.00	94.15	0.00	95.33	0.01			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.188562509
96.09	0.01	94.96	0.00	94.16	0.01	95.33	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.2889534573
96.09	0.01	94.96	0.00	94.16	0.01	95.33	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/2.chip_tl_errors.1823350056
96.10	0.01	94.96	0.00	94.16	0.01	95.33	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.4294495296
96.10	0.01	94.96	0.00	94.17	0.01	95.33	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.3943965300
96.10	0.01	94.96	0.00	94.17	0.01	95.33	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/4.chip_tl_errors.109512559
96.10	0.01	94.96	0.00	94.17	0.01	95.33	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.1724480780
96.10	0.01	94.96	0.00	94.18	0.01	95.33	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/81.xbar_error_random.3726074643
96.10	0.01	94.96	0.00	94.18	0.01	95.33	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.1080477948
96.10	0.01	94.96	0.00	94.18	0.01	95.33	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.2239214858
96.10	0.01	94.96	0.00	94.19	0.01	95.33	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.3106795977
96.10	0.01	94.96	0.00	94.19	0.01	95.33	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.685450956
96.10	0.01	94.96	0.00	94.19	0.01	95.33	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.932453016
96.10	0.01	94.96	0.00	94.20	0.01	95.33	0.00			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.96892489
96.10	0.01	94.96	0.00	94.20	0.00	95.33	0.01			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/1.chip_tap_straps_testunlock0.3701747531
96.10	0.01	94.96	0.00	94.20	0.00	95.33	0.01			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.4058240205
96.10	0.01	94.96	0.00	94.20	0.00	95.34	0.01			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2047046688
96.10	0.01	94.96	0.00	94.20	0.00	95.34	0.01			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2032936015
96.10	0.01	94.96	0.00	94.20	0.00	95.34	0.01			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3105168592
96.10	0.01	94.96	0.00	94.20	0.00	95.34	0.01			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.397823570
96.10	0.01	94.96	0.00	94.20	0.00	95.34	0.01			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1091120518
96.10	0.01	94.96	0.00	94.20	0.00	95.34	0.01			95.05	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2343161667

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.4233226757
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2409673756
/workspace/coverage/cover_reg_top/0.chip_csr_rw.3203490750
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1116095001
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.769839571
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1001694841
/workspace/coverage/cover_reg_top/0.chip_tl_errors.1293680062
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.892483384
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1933315122
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3922450780
/workspace/coverage/cover_reg_top/0.xbar_error_random.1739747342
/workspace/coverage/cover_reg_top/0.xbar_random.2342491546
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.355452384
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3077870310
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3970602255
/workspace/coverage/cover_reg_top/0.xbar_same_source.1122494174
/workspace/coverage/cover_reg_top/0.xbar_smoke.1030831972
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.4113793582
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2865535869
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3309816687
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2440279476
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.258565182
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3686890824
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2972624305
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.299211633
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1933838091
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1368311047
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.400483429
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.4241030324
/workspace/coverage/cover_reg_top/1.chip_tl_errors.226600924
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.267516346
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.557956235
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3270068221
/workspace/coverage/cover_reg_top/1.xbar_error_random.295520019
/workspace/coverage/cover_reg_top/1.xbar_random.2598855407
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3629657654
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3746982857
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.4228718263
/workspace/coverage/cover_reg_top/1.xbar_same_source.4223398549
/workspace/coverage/cover_reg_top/1.xbar_smoke.3109011465
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2795931674
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3729761974
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2491903659
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2225969032
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.3915105270
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3728231098
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.898929936
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2443665134
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.711312735
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2533274275
/workspace/coverage/cover_reg_top/10.chip_tl_errors.463280477
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.4218707591
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.139963278
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3821043120
/workspace/coverage/cover_reg_top/10.xbar_error_random.3907977492
/workspace/coverage/cover_reg_top/10.xbar_random.3198341048
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3446502325
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.889611222
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3170318122
/workspace/coverage/cover_reg_top/10.xbar_same_source.3608608963
/workspace/coverage/cover_reg_top/10.xbar_smoke.2992800251
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2541649858
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3915432031
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1147009487
/workspace/coverage/cover_reg_top/10.xbar_stress_all.2621054651
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.4125317045
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3537424873
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.257655110
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.953845364
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2573626819
/workspace/coverage/cover_reg_top/11.chip_csr_rw.526375919
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2348910464
/workspace/coverage/cover_reg_top/11.chip_tl_errors.2783221295
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2207896749
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1871040288
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2640403345
/workspace/coverage/cover_reg_top/11.xbar_error_random.1834966091
/workspace/coverage/cover_reg_top/11.xbar_random.2728464966
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1868288344
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.980040505
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2702106105
/workspace/coverage/cover_reg_top/11.xbar_same_source.2636576119
/workspace/coverage/cover_reg_top/11.xbar_smoke.3921711285
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2900157360
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.738717285
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3563028662
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1866306842
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3662674451
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2990444857
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1854690807
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.611328322
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1553413012
/workspace/coverage/cover_reg_top/12.chip_csr_rw.1839726859
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2286144054
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2933565874
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2458142926
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1979950748
/workspace/coverage/cover_reg_top/12.xbar_error_random.2548275726
/workspace/coverage/cover_reg_top/12.xbar_random.1741566128
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1232930906
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2520573943
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.573118599
/workspace/coverage/cover_reg_top/12.xbar_same_source.4150938293
/workspace/coverage/cover_reg_top/12.xbar_smoke.847017678
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3176134690
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1006033423
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3508175734
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1202540522
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.304771641
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2131694868
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3540440706
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1959089201
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.2161259327
/workspace/coverage/cover_reg_top/13.chip_csr_rw.2245259403
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2955919281
/workspace/coverage/cover_reg_top/13.chip_tl_errors.2364272878
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.1685845875
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.564582272
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2268753594
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/workspace/coverage/default/94.chip_sw_all_escalation_resets.2322787626
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/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.495014914
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2321294617

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Total test records in report: 2943

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---

TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3895175644			Aug 13 07:21:20 PM PDT 24	Aug 13 07:31:17 PM PDT 24	4867420515 ps
T2	/workspace/coverage/default/3.chip_sw_uart_tx_rx.2788011419			Aug 13 07:34:10 PM PDT 24	Aug 13 07:43:01 PM PDT 24	3898484606 ps
T3	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.4009090730			Aug 13 07:28:19 PM PDT 24	Aug 13 07:39:56 PM PDT 24	4669694450 ps
T4	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2444047670			Aug 13 07:17:16 PM PDT 24	Aug 13 08:06:47 PM PDT 24	24310934722 ps
T5	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.808823475			Aug 13 07:36:30 PM PDT 24	Aug 13 07:44:33 PM PDT 24	4548659160 ps
T6	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1415314010			Aug 13 07:13:37 PM PDT 24	Aug 13 08:48:06 PM PDT 24	45476640120 ps
T61	/workspace/coverage/default/5.chip_sw_all_escalation_resets.2795141087			Aug 13 07:34:19 PM PDT 24	Aug 13 07:43:38 PM PDT 24	4525981836 ps
T43	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.4148333984			Aug 13 07:15:19 PM PDT 24	Aug 13 08:02:59 PM PDT 24	14894785438 ps
T83	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3003378913			Aug 13 07:29:20 PM PDT 24	Aug 13 07:38:04 PM PDT 24	3890273720 ps
T45	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.467760023			Aug 13 07:10:51 PM PDT 24	Aug 13 07:20:51 PM PDT 24	4416201536 ps
T44	/workspace/coverage/default/2.rom_e2e_self_hash.3766307634			Aug 13 07:37:08 PM PDT 24	Aug 13 09:08:55 PM PDT 24	25911556120 ps
T295	/workspace/coverage/default/1.chip_sw_aes_masking_off.151120717			Aug 13 07:18:39 PM PDT 24	Aug 13 07:24:03 PM PDT 24	2829631180 ps
T158	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3879750264			Aug 13 07:24:43 PM PDT 24	Aug 13 07:44:44 PM PDT 24	8317489536 ps
T229	/workspace/coverage/default/0.chip_sw_uart_tx_rx.1616709251			Aug 13 07:09:58 PM PDT 24	Aug 13 07:21:43 PM PDT 24	4735883280 ps
T398	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.4013716596			Aug 13 07:36:04 PM PDT 24	Aug 13 07:41:24 PM PDT 24	3356402384 ps
T62	/workspace/coverage/default/41.chip_sw_all_escalation_resets.3319099001			Aug 13 07:41:29 PM PDT 24	Aug 13 07:51:58 PM PDT 24	5905440248 ps
T7	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.618082728			Aug 13 07:23:18 PM PDT 24	Aug 13 10:16:39 PM PDT 24	58280580768 ps
T185	/workspace/coverage/default/81.chip_sw_all_escalation_resets.3650651410			Aug 13 07:40:32 PM PDT 24	Aug 13 07:49:15 PM PDT 24	5207607232 ps
T17	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.2079963565			Aug 13 07:08:49 PM PDT 24	Aug 13 07:16:02 PM PDT 24	4201465112 ps
T399	/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1485611660			Aug 13 07:33:24 PM PDT 24	Aug 13 07:37:32 PM PDT 24	2479573416 ps
T14	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1385285901			Aug 13 07:08:54 PM PDT 24	Aug 13 07:20:24 PM PDT 24	3880041212 ps
T82	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.486269286			Aug 13 07:12:00 PM PDT 24	Aug 13 10:28:50 PM PDT 24	63871535909 ps
T132	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3379567507			Aug 13 07:34:18 PM PDT 24	Aug 13 07:41:34 PM PDT 24	9507808168 ps
T18	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1982254544			Aug 13 07:31:08 PM PDT 24	Aug 13 08:00:00 PM PDT 24	22918380570 ps
T102	/workspace/coverage/default/34.chip_sw_all_escalation_resets.351464768			Aug 13 07:36:08 PM PDT 24	Aug 13 07:49:45 PM PDT 24	6005790704 ps
T103	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3940332175			Aug 13 07:10:10 PM PDT 24	Aug 13 07:32:27 PM PDT 24	5858277001 ps
T104	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1099067914			Aug 13 07:14:20 PM PDT 24	Aug 13 07:31:34 PM PDT 24	5094430144 ps
T78	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3617885446			Aug 13 07:18:24 PM PDT 24	Aug 13 10:24:24 PM PDT 24	255044445204 ps
T105	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1673893285			Aug 13 07:11:53 PM PDT 24	Aug 13 07:20:46 PM PDT 24	8039510352 ps
T40	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2534115767			Aug 13 07:18:32 PM PDT 24	Aug 13 08:12:51 PM PDT 24	14202577380 ps
T106	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3554489253			Aug 13 07:32:14 PM PDT 24	Aug 13 07:35:32 PM PDT 24	3258403880 ps
T60	/workspace/coverage/default/0.rom_volatile_raw_unlock.3492245668			Aug 13 07:17:31 PM PDT 24	Aug 13 07:19:47 PM PDT 24	2499245143 ps
T107	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1792648665			Aug 13 07:24:57 PM PDT 24	Aug 13 07:42:09 PM PDT 24	5568497552 ps
T34	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1259876016			Aug 13 07:26:15 PM PDT 24	Aug 13 07:33:42 PM PDT 24	4908221708 ps
T260	/workspace/coverage/default/2.chip_sw_aon_timer_irq.393511751			Aug 13 07:25:11 PM PDT 24	Aug 13 07:32:40 PM PDT 24	3766612076 ps
T117	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2651214394			Aug 13 07:32:09 PM PDT 24	Aug 13 07:37:39 PM PDT 24	3276449639 ps
T111	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1305312234			Aug 13 07:25:37 PM PDT 24	Aug 13 07:35:15 PM PDT 24	19971442656 ps
T66	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2911040381			Aug 13 07:15:26 PM PDT 24	Aug 13 07:25:38 PM PDT 24	6584916640 ps
T459	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1239960274			Aug 13 07:10:51 PM PDT 24	Aug 13 07:16:04 PM PDT 24	3104325066 ps
T176	/workspace/coverage/default/1.chip_sw_flash_init.2658630809			Aug 13 07:13:56 PM PDT 24	Aug 13 07:49:43 PM PDT 24	19079128073 ps
T233	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.3387626044			Aug 13 07:33:05 PM PDT 24	Aug 13 07:42:43 PM PDT 24	5058207818 ps
T247	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1754299907			Aug 13 07:26:20 PM PDT 24	Aug 13 07:36:27 PM PDT 24	4258707400 ps
T937	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.106419846			Aug 13 07:16:49 PM PDT 24	Aug 13 07:22:45 PM PDT 24	4494040448 ps
T406	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1677878052			Aug 13 07:37:38 PM PDT 24	Aug 13 07:44:16 PM PDT 24	3624926538 ps
T163	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3753982037			Aug 13 07:11:20 PM PDT 24	Aug 13 10:33:32 PM PDT 24	255010870016 ps
T231	/workspace/coverage/default/27.chip_sw_all_escalation_resets.3907963118			Aug 13 07:35:27 PM PDT 24	Aug 13 07:45:09 PM PDT 24	5012004928 ps
T121	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.801610102			Aug 13 07:16:37 PM PDT 24	Aug 13 07:18:30 PM PDT 24	2846040096 ps
T152	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2059465156			Aug 13 07:31:48 PM PDT 24	Aug 13 07:42:31 PM PDT 24	4036625308 ps
T122	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1472223838			Aug 13 07:12:57 PM PDT 24	Aug 13 07:20:31 PM PDT 24	3782462234 ps
T67	/workspace/coverage/default/4.chip_tap_straps_dev.3895668110			Aug 13 07:31:32 PM PDT 24	Aug 13 07:42:03 PM PDT 24	6716045861 ps
T255	/workspace/coverage/default/0.chip_sw_plic_sw_irq.2710893468			Aug 13 07:12:15 PM PDT 24	Aug 13 07:15:40 PM PDT 24	2185657584 ps
T133	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3432123411			Aug 13 07:31:56 PM PDT 24	Aug 13 07:40:05 PM PDT 24	5221672544 ps
T395	/workspace/coverage/default/1.rom_e2e_asm_init_dev.3406061717			Aug 13 07:25:41 PM PDT 24	Aug 13 08:30:18 PM PDT 24	15002148850 ps
T19	/workspace/coverage/default/0.chip_sw_usbdev_config_host.3318897896			Aug 13 07:10:12 PM PDT 24	Aug 13 07:44:37 PM PDT 24	7878184338 ps
T396	/workspace/coverage/default/1.rom_e2e_self_hash.1732479272			Aug 13 07:26:48 PM PDT 24	Aug 13 09:07:09 PM PDT 24	26578511032 ps
T355	/workspace/coverage/default/1.chip_sw_uart_tx_rx.1330444699			Aug 13 07:15:46 PM PDT 24	Aug 13 07:26:26 PM PDT 24	4010113464 ps
T550	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2000171755			Aug 13 07:24:01 PM PDT 24	Aug 13 07:27:52 PM PDT 24	2681723850 ps
T128	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3094056722			Aug 13 07:30:28 PM PDT 24	Aug 13 07:46:23 PM PDT 24	6847270304 ps
T392	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.915159629			Aug 13 07:33:36 PM PDT 24	Aug 13 07:38:42 PM PDT 24	4015228128 ps
T938	/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2827237959			Aug 13 07:19:12 PM PDT 24	Aug 13 07:23:55 PM PDT 24	2770400662 ps
T424	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1940693666			Aug 13 07:41:00 PM PDT 24	Aug 13 07:45:53 PM PDT 24	3083707600 ps
T177	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1796245282			Aug 13 07:29:16 PM PDT 24	Aug 13 08:09:33 PM PDT 24	25064352558 ps
T232	/workspace/coverage/default/84.chip_sw_all_escalation_resets.4026443967			Aug 13 07:40:58 PM PDT 24	Aug 13 07:49:19 PM PDT 24	5061623668 ps
T939	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1110382477			Aug 13 07:23:24 PM PDT 24	Aug 13 07:26:38 PM PDT 24	2540023280 ps
T256	/workspace/coverage/default/2.chip_sw_plic_sw_irq.3482628887			Aug 13 07:32:10 PM PDT 24	Aug 13 07:37:15 PM PDT 24	2814110220 ps
T261	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4167164466			Aug 13 07:15:58 PM PDT 24	Aug 13 07:40:38 PM PDT 24	10334364860 ps
T940	/workspace/coverage/default/0.chip_sw_hmac_smoketest.2676612251			Aug 13 07:18:28 PM PDT 24	Aug 13 07:23:45 PM PDT 24	2841538668 ps
T262	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3759296901			Aug 13 07:13:11 PM PDT 24	Aug 13 07:23:42 PM PDT 24	4493407176 ps
T178	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1624929982			Aug 13 07:24:16 PM PDT 24	Aug 13 07:33:05 PM PDT 24	4235216200 ps
T367	/workspace/coverage/default/47.chip_sw_all_escalation_resets.2310910303			Aug 13 07:41:35 PM PDT 24	Aug 13 07:50:42 PM PDT 24	6076781872 ps
T768	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1090470863			Aug 13 07:37:22 PM PDT 24	Aug 13 07:46:10 PM PDT 24	4420693576 ps
T758	/workspace/coverage/default/2.chip_sw_aes_idle.3670698332			Aug 13 07:27:00 PM PDT 24	Aug 13 07:30:44 PM PDT 24	3127232968 ps
T759	/workspace/coverage/default/36.chip_sw_all_escalation_resets.1130572295			Aug 13 07:36:42 PM PDT 24	Aug 13 07:48:34 PM PDT 24	5829197760 ps
T467	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.706951989			Aug 13 07:10:35 PM PDT 24	Aug 13 07:19:46 PM PDT 24	7081288865 ps
T129	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1247926829			Aug 13 07:30:27 PM PDT 24	Aug 13 07:55:52 PM PDT 24	9452991260 ps
T8	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2784896510			Aug 13 07:24:33 PM PDT 24	Aug 13 07:31:04 PM PDT 24	3174185073 ps
T59	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.171464704			Aug 13 07:37:35 PM PDT 24	Aug 13 07:51:40 PM PDT 24	13917159466 ps
T345	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.845493284			Aug 13 07:08:49 PM PDT 24	Aug 13 07:14:48 PM PDT 24	3691971792 ps
T239	/workspace/coverage/default/2.chip_sw_flash_init.3151469642			Aug 13 07:23:08 PM PDT 24	Aug 13 07:54:14 PM PDT 24	20688553046 ps
T941	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1182004578			Aug 13 07:20:43 PM PDT 24	Aug 13 07:26:10 PM PDT 24	2992179596 ps
T277	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.837928802			Aug 13 07:24:40 PM PDT 24	Aug 13 07:26:45 PM PDT 24	2396870261 ps
T460	/workspace/coverage/default/2.chip_sw_kmac_smoketest.418501287			Aug 13 07:32:30 PM PDT 24	Aug 13 07:38:52 PM PDT 24	3448179328 ps
T215	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3691474146			Aug 13 07:12:05 PM PDT 24	Aug 13 07:16:08 PM PDT 24	2875704416 ps
T394	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2437090036			Aug 13 07:37:47 PM PDT 24	Aug 13 07:44:02 PM PDT 24	4012779300 ps
T419	/workspace/coverage/default/0.rom_e2e_static_critical.802519285			Aug 13 07:18:51 PM PDT 24	Aug 13 08:32:44 PM PDT 24	17106133800 ps
T130	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3526467010			Aug 13 07:13:22 PM PDT 24	Aug 13 07:49:12 PM PDT 24	11264919760 ps
T220	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.95903302			Aug 13 07:26:12 PM PDT 24	Aug 13 07:30:33 PM PDT 24	2676203598 ps
T224	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2884307202			Aug 13 07:23:07 PM PDT 24	Aug 13 07:32:20 PM PDT 24	4248721818 ps
T357	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.665675516			Aug 13 07:23:19 PM PDT 24	Aug 13 07:38:25 PM PDT 24	5517637120 ps
T942	/workspace/coverage/default/1.chip_sw_aes_smoketest.2432527183			Aug 13 07:22:23 PM PDT 24	Aug 13 07:26:36 PM PDT 24	2913256360 ps
T41	/workspace/coverage/default/1.rom_e2e_shutdown_output.1770285245			Aug 13 07:27:28 PM PDT 24	Aug 13 08:24:01 PM PDT 24	29888188256 ps
T397	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.604887706			Aug 13 07:18:36 PM PDT 24	Aug 13 08:21:50 PM PDT 24	15789994640 ps
T943	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2763444580			Aug 13 07:33:03 PM PDT 24	Aug 13 07:41:25 PM PDT 24	7278375128 ps
T944	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3982826290			Aug 13 07:22:40 PM PDT 24	Aug 13 07:28:46 PM PDT 24	3426262280 ps
T37	/workspace/coverage/default/2.chip_sw_spi_device_tpm.3025996466			Aug 13 07:26:33 PM PDT 24	Aug 13 07:32:14 PM PDT 24	2910242300 ps
T945	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.4281658534			Aug 13 07:17:47 PM PDT 24	Aug 13 07:21:57 PM PDT 24	2281573001 ps
T228	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2549633585			Aug 13 07:23:27 PM PDT 24	Aug 13 07:35:57 PM PDT 24	4480870150 ps
T723	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1012057593			Aug 13 07:34:55 PM PDT 24	Aug 13 07:41:59 PM PDT 24	3362325476 ps
T734	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.1346036317			Aug 13 07:09:33 PM PDT 24	Aug 13 07:20:45 PM PDT 24	9503355620 ps
T74	/workspace/coverage/default/1.rom_raw_unlock.3708095362			Aug 13 07:23:39 PM PDT 24	Aug 13 07:28:43 PM PDT 24	6998383183 ps
T328	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2510504404			Aug 13 07:28:36 PM PDT 24	Aug 13 07:33:29 PM PDT 24	2736231407 ps
T329	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1386747240			Aug 13 07:17:22 PM PDT 24	Aug 13 07:23:21 PM PDT 24	3840756356 ps
T278	/workspace/coverage/default/1.rom_volatile_raw_unlock.93765482			Aug 13 07:23:16 PM PDT 24	Aug 13 07:25:18 PM PDT 24	2796007758 ps
T112	/workspace/coverage/default/0.chip_sw_power_sleep_load.2570450937			Aug 13 07:11:44 PM PDT 24	Aug 13 07:16:36 PM PDT 24	4096371144 ps
T184	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1618127931			Aug 13 07:34:58 PM PDT 24	Aug 13 08:35:34 PM PDT 24	15993438569 ps
T946	/workspace/coverage/default/0.chip_sw_example_concurrency.2556745628			Aug 13 07:11:05 PM PDT 24	Aug 13 07:16:05 PM PDT 24	3107847854 ps
T168	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2874739709			Aug 13 07:16:40 PM PDT 24	Aug 13 07:18:32 PM PDT 24	2056634682 ps
T63	/workspace/coverage/default/0.chip_tap_straps_rma.3098555754			Aug 13 07:10:32 PM PDT 24	Aug 13 07:22:55 PM PDT 24	7362385000 ps
T401	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.81682657			Aug 13 07:36:19 PM PDT 24	Aug 13 07:42:19 PM PDT 24	3413316660 ps
T20	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.237230514			Aug 13 07:15:22 PM PDT 24	Aug 13 07:44:22 PM PDT 24	25205845000 ps
T234	/workspace/coverage/default/33.chip_sw_all_escalation_resets.2354485233			Aug 13 07:36:48 PM PDT 24	Aug 13 07:46:22 PM PDT 24	4540794172 ps
T125	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.4209304873			Aug 13 07:18:29 PM PDT 24	Aug 13 07:44:11 PM PDT 24	6599710056 ps
T359	/workspace/coverage/default/99.chip_sw_all_escalation_resets.1350236304			Aug 13 07:41:51 PM PDT 24	Aug 13 07:53:29 PM PDT 24	5600523402 ps
T226	/workspace/coverage/default/2.chip_sw_pattgen_ios.1016581248			Aug 13 07:23:12 PM PDT 24	Aug 13 07:27:38 PM PDT 24	2467752321 ps
T770	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2692175331			Aug 13 07:41:29 PM PDT 24	Aug 13 07:47:26 PM PDT 24	3757191160 ps
T225	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2406155346			Aug 13 07:15:51 PM PDT 24	Aug 13 07:31:48 PM PDT 24	6098610000 ps
T947	/workspace/coverage/default/1.chip_sw_example_rom.785380963			Aug 13 07:13:48 PM PDT 24	Aug 13 07:15:50 PM PDT 24	2899259960 ps
T214	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.1910346670			Aug 13 07:12:54 PM PDT 24	Aug 13 10:11:21 PM PDT 24	63451903842 ps
T165	/workspace/coverage/default/68.chip_sw_all_escalation_resets.2574681969			Aug 13 07:39:50 PM PDT 24	Aug 13 07:46:46 PM PDT 24	3962347780 ps
T257	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3175135669			Aug 13 07:11:23 PM PDT 24	Aug 13 07:15:46 PM PDT 24	2889398470 ps
T164	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2335747882			Aug 13 07:41:50 PM PDT 24	Aug 13 07:47:28 PM PDT 24	3789094800 ps
T776	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2119673625			Aug 13 07:10:21 PM PDT 24	Aug 13 07:36:28 PM PDT 24	8369183520 ps
T948	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3844104871			Aug 13 07:30:18 PM PDT 24	Aug 13 07:52:27 PM PDT 24	7192853849 ps
T393	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3231050638			Aug 13 07:37:32 PM PDT 24	Aug 13 07:44:31 PM PDT 24	3543582736 ps
T46	/workspace/coverage/default/1.chip_sw_alert_test.3353519822			Aug 13 07:17:09 PM PDT 24	Aug 13 07:23:40 PM PDT 24	2822047740 ps
T855	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1707540569			Aug 13 07:39:41 PM PDT 24	Aug 13 07:47:52 PM PDT 24	3890203996 ps
T11	/workspace/coverage/default/2.chip_sw_power_virus.587022283			Aug 13 07:36:10 PM PDT 24	Aug 13 07:57:49 PM PDT 24	6160513090 ps
T360	/workspace/coverage/default/46.chip_sw_all_escalation_resets.594239629			Aug 13 07:39:04 PM PDT 24	Aug 13 07:50:24 PM PDT 24	5622854904 ps
T12	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3903919125			Aug 13 07:11:44 PM PDT 24	Aug 13 07:21:37 PM PDT 24	4026644466 ps
T252	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.993757698			Aug 13 07:41:02 PM PDT 24	Aug 13 07:46:38 PM PDT 24	3712725770 ps
T123	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.489461014			Aug 13 07:10:40 PM PDT 24	Aug 13 07:20:15 PM PDT 24	3639910872 ps
T15	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3741695782			Aug 13 07:11:33 PM PDT 24	Aug 13 07:18:21 PM PDT 24	4768210036 ps
T296	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3514648136			Aug 13 07:18:43 PM PDT 24	Aug 13 08:35:01 PM PDT 24	18248379768 ps
T297	/workspace/coverage/default/2.chip_sw_example_rom.715030324			Aug 13 07:22:01 PM PDT 24	Aug 13 07:23:57 PM PDT 24	2531122404 ps
T154	/workspace/coverage/default/1.chip_sw_power_idle_load.831055484			Aug 13 07:21:06 PM PDT 24	Aug 13 07:32:36 PM PDT 24	4627190684 ps
T298	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3738816300			Aug 13 07:15:42 PM PDT 24	Aug 13 07:20:22 PM PDT 24	3205427456 ps
T299	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.441478119			Aug 13 07:18:55 PM PDT 24	Aug 13 07:25:27 PM PDT 24	3767073884 ps
T134	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3292045829			Aug 13 07:32:14 PM PDT 24	Aug 13 07:45:24 PM PDT 24	5566631212 ps
T300	/workspace/coverage/default/2.chip_sw_edn_sw_mode.2527845505			Aug 13 07:28:46 PM PDT 24	Aug 13 08:03:18 PM PDT 24	10201625078 ps
T235	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3055181216			Aug 13 07:17:33 PM PDT 24	Aug 13 07:36:12 PM PDT 24	6216848536 ps
T428	/workspace/coverage/default/51.chip_sw_all_escalation_resets.2747974183			Aug 13 07:38:04 PM PDT 24	Aug 13 07:50:28 PM PDT 24	5246176336 ps
T113	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1683748036			Aug 13 07:20:42 PM PDT 24	Aug 14 12:54:40 AM PDT 24	148346178621 ps
T949	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3651581078			Aug 13 07:32:56 PM PDT 24	Aug 13 07:38:16 PM PDT 24	3111685512 ps
T762	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2924976863			Aug 13 07:20:20 PM PDT 24	Aug 13 07:36:01 PM PDT 24	8041623720 ps
T363	/workspace/coverage/default/1.chip_sival_flash_info_access.3452226269			Aug 13 07:13:03 PM PDT 24	Aug 13 07:17:23 PM PDT 24	2784129432 ps
T950	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1536023979			Aug 13 07:11:05 PM PDT 24	Aug 13 07:14:06 PM PDT 24	2355170360 ps
T951	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1922807985			Aug 13 07:29:38 PM PDT 24	Aug 13 07:39:55 PM PDT 24	4899931678 ps
T371	/workspace/coverage/default/2.chip_sw_hmac_enc.625506891			Aug 13 07:28:35 PM PDT 24	Aug 13 07:32:36 PM PDT 24	3035976850 ps
T344	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.31263571			Aug 13 07:12:32 PM PDT 24	Aug 13 07:22:14 PM PDT 24	4294978152 ps
T771	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3309624210			Aug 13 07:36:52 PM PDT 24	Aug 13 07:42:35 PM PDT 24	3304427112 ps
T193	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2047046688			Aug 13 07:09:42 PM PDT 24	Aug 13 07:17:00 PM PDT 24	5105950280 ps
T197	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3492947362			Aug 13 07:34:08 PM PDT 24	Aug 13 07:41:38 PM PDT 24	7059410806 ps
T57	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1397030329			Aug 13 07:11:00 PM PDT 24	Aug 13 07:34:36 PM PDT 24	20101163560 ps
T952	/workspace/coverage/default/0.chip_sw_aon_timer_irq.736960856			Aug 13 07:09:34 PM PDT 24	Aug 13 07:16:36 PM PDT 24	4588914434 ps
T227	/workspace/coverage/default/0.chip_sw_pattgen_ios.2394178238			Aug 13 07:09:31 PM PDT 24	Aug 13 07:13:50 PM PDT 24	3570499600 ps
T953	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3434101526			Aug 13 07:25:38 PM PDT 24	Aug 13 07:38:01 PM PDT 24	9940272134 ps
T954	/workspace/coverage/default/1.chip_sw_hmac_smoketest.1399380720			Aug 13 07:22:21 PM PDT 24	Aug 13 07:29:25 PM PDT 24	3592314992 ps
T955	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.361549912			Aug 13 07:13:13 PM PDT 24	Aug 13 07:19:26 PM PDT 24	6120688730 ps
T462	/workspace/coverage/default/1.chip_sw_kmac_entropy.2916903923			Aug 13 07:14:39 PM PDT 24	Aug 13 07:18:13 PM PDT 24	2487118790 ps
T546	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.96892489			Aug 13 07:12:22 PM PDT 24	Aug 13 07:26:30 PM PDT 24	4396642676 ps
T956	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3019144295			Aug 13 07:13:31 PM PDT 24	Aug 13 07:23:10 PM PDT 24	4667859052 ps
T856	/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3456014807			Aug 13 07:39:58 PM PDT 24	Aug 13 07:44:48 PM PDT 24	2899804904 ps
T267	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2739404192			Aug 13 07:26:47 PM PDT 24	Aug 13 07:44:25 PM PDT 24	5703854488 ps
T351	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2176072631			Aug 13 07:14:16 PM PDT 24	Aug 13 07:27:16 PM PDT 24	4994321049 ps
T547	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.808004689			Aug 13 07:27:13 PM PDT 24	Aug 13 07:45:44 PM PDT 24	4908323106 ps
T126	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2877215733			Aug 13 07:37:24 PM PDT 24	Aug 13 07:49:31 PM PDT 24	8306308258 ps
T266	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2780321993			Aug 13 07:33:16 PM PDT 24	Aug 13 08:38:55 PM PDT 24	19660469520 ps
T824	/workspace/coverage/default/87.chip_sw_all_escalation_resets.3664512849			Aug 13 07:42:30 PM PDT 24	Aug 13 07:52:18 PM PDT 24	4568629620 ps
T764	/workspace/coverage/default/92.chip_sw_all_escalation_resets.2633970074			Aug 13 07:41:06 PM PDT 24	Aug 13 07:49:39 PM PDT 24	5290995236 ps
T781	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3290761240			Aug 13 07:43:43 PM PDT 24	Aug 13 07:49:53 PM PDT 24	3130535648 ps
T325	/workspace/coverage/default/0.chip_plic_all_irqs_20.3000670873			Aug 13 07:12:47 PM PDT 24	Aug 13 07:28:23 PM PDT 24	5158392216 ps
T153	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.478701707			Aug 13 07:34:50 PM PDT 24	Aug 13 07:54:39 PM PDT 24	8316500440 ps
T42	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3605981678			Aug 13 07:14:49 PM PDT 24	Aug 13 08:03:54 PM PDT 24	11243798684 ps
T957	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1851485215			Aug 13 07:17:20 PM PDT 24	Aug 13 07:35:12 PM PDT 24	5327535140 ps
T958	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.726582893			Aug 13 07:14:59 PM PDT 24	Aug 13 07:27:55 PM PDT 24	4158871512 ps
T13	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.4275932841			Aug 13 07:18:27 PM PDT 24	Aug 13 07:25:44 PM PDT 24	4414829172 ps
T179	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2043983043			Aug 13 07:25:26 PM PDT 24	Aug 13 09:01:51 PM PDT 24	47848843950 ps
T959	/workspace/coverage/default/0.chip_sw_aes_smoketest.956642086			Aug 13 07:18:44 PM PDT 24	Aug 13 07:24:20 PM PDT 24	3059137976 ps
T118	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.579421172			Aug 13 07:19:02 PM PDT 24	Aug 13 07:41:28 PM PDT 24	8282700606 ps
T116	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1604333878			Aug 13 07:14:09 PM PDT 24	Aug 13 08:15:53 PM PDT 24	18650801638 ps
T960	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2720372800			Aug 13 07:16:52 PM PDT 24	Aug 13 07:26:21 PM PDT 24	6072507892 ps
T368	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1463719775			Aug 13 07:15:22 PM PDT 24	Aug 13 07:28:14 PM PDT 24	4718923650 ps
T280	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.4169855721			Aug 13 07:17:45 PM PDT 24	Aug 13 07:28:49 PM PDT 24	8529780385 ps
T425	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3700474385			Aug 13 07:41:37 PM PDT 24	Aug 13 07:48:42 PM PDT 24	3993824232 ps
T127	/workspace/coverage/default/2.chip_sw_edn_auto_mode.3368589067			Aug 13 07:37:15 PM PDT 24	Aug 13 08:09:47 PM PDT 24	6626619752 ps
T463	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2786999767			Aug 13 07:11:18 PM PDT 24	Aug 13 07:36:52 PM PDT 24	8302357288 ps
T961	/workspace/coverage/default/2.chip_sw_csrng_smoketest.2623474568			Aug 13 07:30:31 PM PDT 24	Aug 13 07:36:49 PM PDT 24	2733930482 ps
T962	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.188562509			Aug 13 07:09:49 PM PDT 24	Aug 13 07:19:20 PM PDT 24	8027334696 ps
T194	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.4107116534			Aug 13 07:15:46 PM PDT 24	Aug 13 07:26:48 PM PDT 24	5924934408 ps
T21	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3477751219			Aug 13 07:10:22 PM PDT 24	Aug 13 07:15:51 PM PDT 24	3868096142 ps
T400	/workspace/coverage/default/1.chip_sw_edn_boot_mode.165731274			Aug 13 07:16:45 PM PDT 24	Aug 13 07:26:08 PM PDT 24	3373053630 ps
T155	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2541587930			Aug 13 07:17:46 PM PDT 24	Aug 13 08:25:31 PM PDT 24	17422473096 ps
T180	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2470645346			Aug 13 07:17:20 PM PDT 24	Aug 13 07:21:28 PM PDT 24	3628881609 ps
T279	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4185564306			Aug 13 07:11:58 PM PDT 24	Aug 13 07:14:01 PM PDT 24	2208449149 ps
T458	/workspace/coverage/default/7.chip_sw_all_escalation_resets.2505339715			Aug 13 07:34:38 PM PDT 24	Aug 13 07:47:53 PM PDT 24	5566921514 ps
T963	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2237537207			Aug 13 07:15:20 PM PDT 24	Aug 13 07:38:06 PM PDT 24	14799232261 ps
T964	/workspace/coverage/default/1.chip_sw_hmac_oneshot.2045944487			Aug 13 07:17:24 PM PDT 24	Aug 13 07:23:09 PM PDT 24	2607284340 ps
T282	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.136042304			Aug 13 07:32:40 PM PDT 24	Aug 13 07:43:26 PM PDT 24	5605030400 ps
T114	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2097299864			Aug 13 07:33:03 PM PDT 24	Aug 13 08:38:26 PM PDT 24	24382391209 ps
T286	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1586701431			Aug 13 07:33:46 PM PDT 24	Aug 13 07:43:40 PM PDT 24	6360516148 ps
T287	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1998026827			Aug 13 07:15:33 PM PDT 24	Aug 13 07:32:27 PM PDT 24	7545175200 ps
T38	/workspace/coverage/default/0.chip_sw_spi_device_tpm.4007820703			Aug 13 07:10:15 PM PDT 24	Aug 13 07:17:32 PM PDT 24	3805564139 ps
T288	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2711077762			Aug 13 07:33:05 PM PDT 24	Aug 13 07:36:31 PM PDT 24	2470945710 ps
T230	/workspace/coverage/default/2.chip_sw_power_idle_load.3945135358			Aug 13 07:31:44 PM PDT 24	Aug 13 07:42:36 PM PDT 24	4161786264 ps
T289	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1557950496			Aug 13 07:25:27 PM PDT 24	Aug 13 07:39:08 PM PDT 24	4602225212 ps
T49	/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.4183022740			Aug 13 07:16:48 PM PDT 24	Aug 13 07:22:03 PM PDT 24	3373457982 ps
T79	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1470892431			Aug 13 07:41:12 PM PDT 24	Aug 13 07:48:28 PM PDT 24	3788220040 ps
T89	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1604551265			Aug 13 07:40:53 PM PDT 24	Aug 13 07:47:55 PM PDT 24	4238387862 ps
T90	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1484094180			Aug 13 07:24:51 PM PDT 24	Aug 13 07:29:21 PM PDT 24	2813426304 ps
T91	/workspace/coverage/default/1.chip_sw_power_sleep_load.1609301525			Aug 13 07:21:08 PM PDT 24	Aug 13 07:28:21 PM PDT 24	4481933420 ps
T92	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1891960667			Aug 13 07:19:27 PM PDT 24	Aug 13 08:00:00 PM PDT 24	11332183020 ps
T93	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.932453016			Aug 13 07:09:25 PM PDT 24	Aug 13 07:23:08 PM PDT 24	4714119164 ps
T9	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3676659456			Aug 13 07:11:18 PM PDT 24	Aug 13 07:18:20 PM PDT 24	3131418029 ps
T94	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1152918100			Aug 13 07:18:18 PM PDT 24	Aug 13 07:22:37 PM PDT 24	2891668740 ps
T95	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3978003342			Aug 13 07:17:18 PM PDT 24	Aug 13 07:22:02 PM PDT 24	2854686612 ps
T96	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1091120518			Aug 13 07:10:10 PM PDT 24	Aug 13 07:21:41 PM PDT 24	7824281109 ps
T251	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.894167503			Aug 13 07:15:27 PM PDT 24	Aug 13 07:41:05 PM PDT 24	10098459240 ps
T313	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.3646461560			Aug 13 07:38:04 PM PDT 24	Aug 13 08:36:23 PM PDT 24	15059086952 ps
T314	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2355907591			Aug 13 07:14:09 PM PDT 24	Aug 13 07:23:16 PM PDT 24	5976664960 ps
T68	/workspace/coverage/default/2.chip_tap_straps_prod.2475233018			Aug 13 07:28:32 PM PDT 24	Aug 13 07:47:25 PM PDT 24	11048837405 ps
T84	/workspace/coverage/default/62.chip_sw_all_escalation_resets.371139345			Aug 13 07:39:53 PM PDT 24	Aug 13 07:51:00 PM PDT 24	4918449462 ps
T315	/workspace/coverage/default/0.chip_sival_flash_info_access.95892008			Aug 13 07:10:19 PM PDT 24	Aug 13 07:15:35 PM PDT 24	2369763280 ps
T316	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3250973033			Aug 13 07:38:37 PM PDT 24	Aug 13 07:45:46 PM PDT 24	3526921328 ps
T317	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2516293109			Aug 13 07:11:52 PM PDT 24	Aug 13 07:21:49 PM PDT 24	5216984336 ps
T318	/workspace/coverage/default/12.chip_sw_all_escalation_resets.222326615			Aug 13 07:35:44 PM PDT 24	Aug 13 07:46:00 PM PDT 24	4796741704 ps
T965	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1720134117			Aug 13 07:16:55 PM PDT 24	Aug 13 07:21:44 PM PDT 24	3366102090 ps
T240	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.68550076			Aug 13 07:09:33 PM PDT 24	Aug 13 08:41:32 PM PDT 24	50834619900 ps
T966	/workspace/coverage/default/18.chip_sw_all_escalation_resets.384118125			Aug 13 07:36:57 PM PDT 24	Aug 13 07:49:55 PM PDT 24	5411802270 ps
T31	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1630886635			Aug 13 07:09:45 PM PDT 24	Aug 13 07:13:43 PM PDT 24	3619430934 ps
T108	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3272352363			Aug 13 07:19:05 PM PDT 24	Aug 13 07:28:04 PM PDT 24	4399740832 ps
T442	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3551900204			Aug 13 07:20:43 PM PDT 24	Aug 13 07:24:44 PM PDT 24	2821754520 ps
T16	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3590264991			Aug 13 07:35:37 PM PDT 24	Aug 13 07:43:23 PM PDT 24	3977592120 ps
T183	/workspace/coverage/default/0.rom_e2e_shutdown_output.4106821308			Aug 13 07:15:19 PM PDT 24	Aug 13 08:18:21 PM PDT 24	24870461732 ps
T216	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2316402398			Aug 13 07:17:17 PM PDT 24	Aug 13 07:21:41 PM PDT 24	3018506406 ps
T369	/workspace/coverage/default/61.chip_sw_all_escalation_resets.1030848343			Aug 13 07:39:44 PM PDT 24	Aug 13 07:47:33 PM PDT 24	5735374216 ps
T85	/workspace/coverage/default/82.chip_sw_all_escalation_resets.1184530463			Aug 13 07:41:13 PM PDT 24	Aug 13 07:50:47 PM PDT 24	5006292204 ps
T323	/workspace/coverage/default/96.chip_sw_all_escalation_resets.4081879659			Aug 13 07:42:46 PM PDT 24	Aug 13 07:51:55 PM PDT 24	4908364550 ps
T205	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.609893116			Aug 13 07:09:10 PM PDT 24	Aug 13 07:21:26 PM PDT 24	6188358862 ps
T443	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2151398921			Aug 13 07:40:19 PM PDT 24	Aug 13 07:46:26 PM PDT 24	3834064224 ps
T356	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2622740227			Aug 13 07:33:47 PM PDT 24	Aug 13 07:45:37 PM PDT 24	4697249342 ps
T32	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3852055626			Aug 13 07:15:08 PM PDT 24	Aug 13 07:20:20 PM PDT 24	3209793210 ps
T354	/workspace/coverage/default/2.chip_sival_flash_info_access.2006914614			Aug 13 07:29:04 PM PDT 24	Aug 13 07:36:10 PM PDT 24	3734170434 ps
T445	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1598679110			Aug 13 07:22:56 PM PDT 24	Aug 13 07:27:32 PM PDT 24	2444939250 ps
T967	/workspace/coverage/default/1.chip_sw_aes_entropy.913990249			Aug 13 07:21:12 PM PDT 24	Aug 13 07:24:55 PM PDT 24	3382532136 ps
T763	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1995004178			Aug 13 07:13:06 PM PDT 24	Aug 13 07:18:35 PM PDT 24	3917569096 ps
T968	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1161752288			Aug 13 07:32:17 PM PDT 24	Aug 13 07:37:54 PM PDT 24	2978493436 ps
T769	/workspace/coverage/default/80.chip_sw_all_escalation_resets.1598604898			Aug 13 07:40:06 PM PDT 24	Aug 13 07:50:20 PM PDT 24	5953184836 ps
T969	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1443698457			Aug 13 07:21:39 PM PDT 24	Aug 13 07:30:54 PM PDT 24	3764562184 ps
T405	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3882908162			Aug 13 07:19:52 PM PDT 24	Aug 13 07:23:06 PM PDT 24	2557831830 ps
T828	/workspace/coverage/default/55.chip_sw_all_escalation_resets.1219743647			Aug 13 07:38:43 PM PDT 24	Aug 13 07:46:48 PM PDT 24	5194405504 ps