Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.otp_ctrl__prim_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	143867	1			T71	36		T72	9		T73	2
values[2]	10782	1			T71	3		T77	1		T131	5
values[3]	4555	1			T883	1		T553	1		T560	1
values[4]	2556	1			T883	1		T560	1		T896	1
values[5]	1585	1			T883	1		T560	1		T896	1
values[6]	1118	1			T883	1		T560	1		T896	1
values[7]	808	1			T883	1		T560	1		T896	1
values[8]	636	1			T883	1		T560	1		T896	1
values[9]	521	1			T883	1		T560	1		T896	1
values[10]	454	1			T883	1		T560	1		T896	1
values[11]	381	1			T883	1		T560	2		T896	1
values[12]	365	1			T883	1		T560	1		T896	1
values[13]	381	1			T883	1		T560	1		T896	1
values[14]	386	1			T883	1		T560	1		T896	1
values[15]	369	1			T883	1		T560	1		T896	1
values[16]	363	1			T883	1		T560	1		T896	1
values[17]	328	1			T883	1		T560	1		T896	1
values[18]	337	1			T883	1		T560	1		T896	1
values[19]	406	1			T883	1		T560	1		T896	1
values[20]	290	1			T883	1		T560	2		T896	1
values[21]	278	1			T883	1		T560	1		T896	1
values[22]	299	1			T883	1		T560	1		T896	1
values[23]	326	1			T883	1		T560	1		T896	1
values[24]	346	1			T883	1		T560	1		T896	1
values[25]	342	1			T883	1		T560	1		T896	1
values[26]	344	1			T883	1		T560	1		T896	1
values[27]	347	1			T883	1		T560	1		T896	1
values[28]	303	1			T883	1		T560	1		T896	1
values[29]	327	1			T883	1		T560	1		T896	1
values[30]	270	1			T883	1		T560	1		T896	1
values[31]	279	1			T883	1		T560	1		T896	1
values[32]	275	1			T883	1		T560	1		T896	1
values[33]	327	1			T883	1		T560	1		T896	1
values[34]	333	1			T883	1		T560	1		T896	1
values[35]	273	1			T883	1		T560	1		T896	1
values[36]	277	1			T883	1		T560	1		T896	1
values[37]	336	1			T883	1		T560	1		T896	1
values[38]	300	1			T883	1		T560	1		T896	1
values[39]	296	1			T883	1		T560	1		T896	1
values[40]	297	1			T883	1		T560	1		T896	1
values[41]	305	1			T883	1		T560	1		T896	1
values[42]	304	1			T883	1		T560	1		T896	1
values[43]	265	1			T883	1		T560	1		T896	1
values[44]	242	1			T883	1		T560	1		T896	1
values[45]	256	1			T883	1		T560	1		T896	1
values[46]	300	1			T883	1		T560	1		T896	1
values[47]	295	1			T883	1		T560	1		T896	1
values[48]	319	1			T883	1		T560	1		T896	1
values[49]	311	1			T883	1		T560	1		T896	1
values[50]	288	1			T883	1		T560	1		T896	1
values[51]	278	1			T883	1		T560	1		T896	1
values[52]	306	1			T883	1		T560	1		T896	1
values[53]	262	1			T883	1		T560	1		T896	1
values[54]	257	1			T883	1		T560	1		T896	1
values[55]	234	1			T883	1		T560	1		T896	1
values[56]	268	1			T883	1		T560	1		T896	1
values[57]	270	1			T883	1		T560	1		T896	1
values[58]	263	1			T883	1		T560	1		T896	1
values[59]	226	1			T883	1		T560	1		T896	1
values[60]	213	1			T883	1		T560	1		T896	1
values[61]	156	1			T883	1		T560	1		T896	1
values[62]	202	1			T883	1		T560	1		T896	1
values[63]	270	1			T883	1		T560	1		T896	1
values[64]	188	1			T883	1		T560	1		T896	1
values[65]	177	1			T883	1		T560	1		T896	1
values[66]	183	1			T883	1		T560	1		T896	1
values[67]	153	1			T883	1		T560	1		T896	1
values[68]	143	1			T883	1		T560	1		T896	1
values[69]	165	1			T883	1		T560	1		T896	1
values[70]	148	1			T883	1		T560	1		T896	1
values[71]	152	1			T883	1		T560	1		T896	1
values[72]	110	1			T883	1		T560	1		T896	1
values[73]	135	1			T883	1		T560	1		T896	1
values[74]	156	1			T883	1		T560	1		T896	1
values[75]	139	1			T883	1		T560	1		T896	1
values[76]	118	1			T883	1		T560	1		T896	2
values[77]	102	1			T883	1		T560	1		T896	1
values[78]	90	1			T883	1		T560	1		T896	1
values[79]	88	1			T883	1		T560	1		T896	1
values[80]	96	1			T883	1		T560	1		T896	1
values[81]	107	1			T883	1		T560	1		T896	1
values[82]	108	1			T883	1		T560	1		T896	1
values[83]	143	1			T883	1		T560	1		T896	1
values[84]	116	1			T883	1		T560	1		T896	1
values[85]	96	1			T883	1		T560	1		T896	1
values[86]	101	1			T883	1		T560	1		T896	1
values[87]	102	1			T883	1		T560	1		T896	1
values[88]	111	1			T883	1		T560	1		T896	1
values[89]	120	1			T883	2		T560	1		T896	1
values[90]	122	1			T883	1		T560	1		T896	1
values[91]	121	1			T883	1		T560	1		T896	1
values[92]	100	1			T883	1		T560	1		T896	1
values[93]	97	1			T883	1		T560	1		T896	1
values[94]	85	1			T883	1		T560	1		T896	1
values[95]	101	1			T883	1		T560	1		T896	1
values[96]	103	1			T883	1		T560	2		T896	1
values[97]	124	1			T883	1		T560	7		T896	1
values[98]	122	1			T883	1		T560	3		T896	1
values[99]	102	1			T883	1		T560	3		T896	1
values[100]	109	1			T883	1		T560	2		T896	1
values[101]	96	1			T883	1		T560	3		T896	1
values[102]	86	1			T883	1		T560	2		T896	1
values[103]	103	1			T883	1		T560	2		T896	1
values[104]	104	1			T883	1		T560	4		T896	1
values[105]	94	1			T883	1		T560	2		T896	1
values[106]	101	1			T883	1		T560	1		T896	1
values[107]	103	1			T883	1		T560	2		T896	1
values[108]	96	1			T883	1		T560	7		T896	1
values[109]	88	1			T883	1		T560	2		T896	1
values[110]	93	1			T883	1		T560	1		T896	3
values[111]	85	1			T883	1		T560	1		T896	2
values[112]	101	1			T883	1		T560	1		T896	2
values[113]	85	1			T883	1		T560	3		T896	3
values[114]	81	1			T883	1		T560	1		T896	1
values[115]	68	1			T883	1		T560	3		T896	1
values[116]	84	1			T883	1		T560	1		T896	1
values[117]	69	1			T883	1		T560	1		T896	4
values[118]	97	1			T883	2		T560	3		T896	8
values[119]	81	1			T883	1		T560	2		T896	1
values[120]	65	1			T883	2		T560	2		T896	1
values[121]	78	1			T883	1		T560	1		T896	2
values[122]	94	1			T883	1		T560	1		T896	3
values[123]	76	1			T883	5		T560	1		T896	1
values[124]	96	1			T883	3		T560	2		T896	3
values[125]	115	1			T883	2		T560	2		T896	1
values[126]	166	1			T883	5		T560	3		T896	1
values[127]	946	1			T883	33		T560	42		T896	19
values[128]	7993	1			T883	401		T560	349		T896	319