Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	148226	1			T71	56		T72	7		T73	6
values[2]	11105	1			T71	1		T131	82		T555	1
values[3]	3873	1			T131	37		T551	1		T502	1
values[4]	2179	1			T131	18		T551	1		T493	5
values[5]	1530	1			T131	7		T551	1		T493	3
values[6]	1078	1			T551	1		T493	8		T726	18
values[7]	844	1			T551	1		T493	1		T726	7
values[8]	664	1			T551	1		T493	1		T726	6
values[9]	622	1			T551	1		T726	3		T863	7
values[10]	508	1			T551	1		T726	5		T863	7
values[11]	437	1			T551	1		T726	6		T863	5
values[12]	438	1			T551	1		T726	3		T863	4
values[13]	363	1			T551	1		T726	4		T863	3
values[14]	357	1			T551	1		T726	3		T863	7
values[15]	397	1			T551	1		T726	8		T863	10
values[16]	404	1			T551	1		T726	8		T863	3
values[17]	395	1			T551	1		T726	2		T863	18
values[18]	309	1			T551	1		T726	1		T863	6
values[19]	311	1			T551	1		T726	3		T863	4
values[20]	282	1			T551	1		T726	2		T863	4
values[21]	330	1			T551	1		T726	1		T863	7
values[22]	391	1			T551	1		T726	2		T863	10
values[23]	355	1			T551	1		T726	7		T863	6
values[24]	335	1			T551	1		T726	5		T863	4
values[25]	277	1			T551	1		T726	2		T863	4
values[26]	340	1			T551	1		T726	6		T863	19
values[27]	305	1			T551	1		T726	1		T863	15
values[28]	291	1			T551	1		T726	3		T863	4
values[29]	336	1			T551	1		T726	2		T863	5
values[30]	291	1			T551	1		T726	5		T863	3
values[31]	317	1			T551	1		T726	2		T863	9
values[32]	323	1			T551	1		T726	2		T863	10
values[33]	320	1			T551	1		T726	3		T863	19
values[34]	369	1			T551	1		T726	1		T863	10
values[35]	325	1			T551	1		T726	2		T863	9
values[36]	326	1			T551	1		T726	1		T863	6
values[37]	318	1			T551	1		T726	1		T863	9
values[38]	316	1			T551	1		T726	2		T863	8
values[39]	326	1			T551	1		T726	1		T863	3
values[40]	337	1			T551	1		T726	1		T863	27
values[41]	313	1			T551	1		T726	4		T863	4
values[42]	280	1			T551	1		T726	2		T863	7
values[43]	270	1			T551	1		T726	3		T863	9
values[44]	283	1			T551	1		T726	2		T863	7
values[45]	265	1			T551	1		T726	2		T863	7
values[46]	219	1			T551	1		T726	5		T863	6
values[47]	262	1			T551	1		T726	3		T863	11
values[48]	329	1			T551	1		T726	3		T863	11
values[49]	277	1			T551	1		T726	1		T863	11
values[50]	280	1			T551	1		T726	5		T863	8
values[51]	292	1			T551	1		T726	1		T863	10
values[52]	287	1			T551	1		T726	4		T863	7
values[53]	258	1			T551	1		T726	1		T863	6
values[54]	261	1			T551	1		T726	2		T863	7
values[55]	284	1			T551	1		T726	3		T863	9
values[56]	296	1			T551	1		T726	2		T863	14
values[57]	236	1			T551	1		T726	2		T863	3
values[58]	223	1			T551	1		T726	3		T863	4
values[59]	197	1			T551	1		T726	1		T863	12
values[60]	223	1			T551	1		T726	3		T863	9
values[61]	216	1			T551	1		T726	4		T863	3
values[62]	177	1			T551	1		T726	10		T863	7
values[63]	145	1			T551	1		T726	4		T863	8
values[64]	170	1			T551	1		T726	3		T863	7
values[65]	143	1			T551	1		T726	3		T863	1
values[66]	133	1			T551	1		T726	3		T480	3
values[67]	174	1			T551	1		T726	4		T480	7
values[68]	139	1			T551	1		T726	1		T480	3
values[69]	152	1			T551	1		T726	2		T480	2
values[70]	184	1			T551	1		T726	5		T480	7
values[71]	155	1			T551	1		T726	2		T480	9
values[72]	128	1			T551	1		T726	2		T480	2
values[73]	116	1			T551	1		T726	4		T480	3
values[74]	91	1			T551	1		T726	2		T480	3
values[75]	107	1			T551	1		T726	11		T480	1
values[76]	104	1			T551	1		T726	13		T480	3
values[77]	104	1			T551	1		T726	11		T480	3
values[78]	87	1			T551	1		T726	2		T480	1
values[79]	87	1			T551	1		T726	3		T480	5
values[80]	91	1			T551	1		T726	1		T480	5
values[81]	84	1			T551	1		T726	5		T480	3
values[82]	81	1			T551	1		T726	4		T480	2
values[83]	82	1			T551	1		T726	4		T480	1
values[84]	99	1			T551	1		T726	5		T480	1
values[85]	76	1			T551	1		T726	5		T480	1
values[86]	82	1			T551	1		T726	5		T480	3
values[87]	103	1			T551	1		T726	7		T480	1
values[88]	102	1			T551	4		T726	5		T480	2
values[89]	98	1			T551	5		T726	4		T480	1
values[90]	84	1			T551	3		T726	2		T480	1
values[91]	65	1			T551	1		T726	2		T480	2
values[92]	102	1			T551	7		T726	4		T480	9
values[93]	91	1			T551	3		T726	7		T480	4
values[94]	102	1			T551	1		T726	2		T480	2
values[95]	114	1			T551	4		T726	7		T480	2
values[96]	91	1			T551	9		T726	3		T480	1
values[97]	106	1			T551	9		T726	8		T480	1
values[98]	116	1			T551	1		T726	6		T480	2
values[99]	124	1			T551	1		T726	7		T480	6
values[100]	100	1			T551	1		T726	3		T480	7
values[101]	96	1			T551	1		T726	3		T480	3
values[102]	101	1			T551	1		T726	5		T480	2
values[103]	85	1			T551	4		T726	3		T480	5
values[104]	94	1			T551	1		T726	8		T480	9
values[105]	101	1			T551	2		T726	7		T480	6
values[106]	88	1			T551	3		T726	10		T480	2
values[107]	117	1			T551	5		T726	10		T480	5
values[108]	96	1			T551	1		T726	3		T480	2
values[109]	81	1			T551	3		T726	5		T480	2
values[110]	84	1			T551	1		T726	8		T480	1
values[111]	81	1			T551	2		T726	5		T480	4
values[112]	81	1			T551	2		T726	2		T480	4
values[113]	72	1			T551	1		T726	2		T480	6
values[114]	87	1			T551	1		T726	6		T480	7
values[115]	89	1			T551	1		T726	10		T480	1
values[116]	78	1			T551	2		T726	2		T480	2
values[117]	87	1			T551	1		T726	2		T480	3
values[118]	82	1			T551	1		T726	3		T480	3
values[119]	67	1			T551	2		T726	6		T480	4
values[120]	76	1			T551	1		T726	6		T480	7
values[121]	100	1			T551	1		T726	6		T480	3
values[122]	87	1			T551	2		T726	2		T480	2
values[123]	78	1			T551	1		T726	3		T480	3
values[124]	84	1			T551	1		T726	5		T480	3
values[125]	104	1			T551	1		T726	15		T480	4
values[126]	177	1			T551	1		T726	19		T480	10
values[127]	861	1			T551	23		T726	20		T480	28
values[128]	6306	1			T551	299		T726	9		T480	16