Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	144949	1			T71	57		T72	5		T73	5
values[2]	11066	1			T77	2		T131	2		T440	4
values[3]	4595	1			T429	1		T552	6		T502	2
values[4]	2805	1			T429	3		T552	5		T560	2
values[5]	1750	1			T429	3		T552	3		T560	2
values[6]	1122	1			T429	1		T552	3		T560	2
values[7]	762	1			T429	1		T552	2		T560	2
values[8]	568	1			T429	1		T552	7		T560	3
values[9]	478	1			T429	3		T552	9		T560	2
values[10]	369	1			T429	1		T552	14		T560	2
values[11]	348	1			T429	4		T552	8		T560	2
values[12]	364	1			T429	4		T552	12		T560	2
values[13]	276	1			T429	2		T552	8		T560	2
values[14]	351	1			T429	14		T552	3		T560	2
values[15]	310	1			T429	11		T552	4		T560	2
values[16]	301	1			T429	5		T552	5		T560	2
values[17]	251	1			T429	3		T552	10		T560	2
values[18]	284	1			T429	1		T552	5		T560	2
values[19]	305	1			T429	5		T552	4		T560	2
values[20]	314	1			T429	1		T552	2		T560	2
values[21]	262	1			T429	4		T552	6		T560	2
values[22]	304	1			T429	2		T552	13		T560	2
values[23]	302	1			T429	1		T552	10		T560	2
values[24]	296	1			T429	2		T552	5		T560	2
values[25]	300	1			T429	1		T552	4		T560	2
values[26]	264	1			T429	2		T552	3		T560	2
values[27]	284	1			T429	3		T552	18		T560	2
values[28]	274	1			T429	1		T552	4		T560	2
values[29]	327	1			T429	1		T552	3		T560	2
values[30]	288	1			T429	4		T552	5		T560	2
values[31]	275	1			T429	1		T552	7		T560	2
values[32]	270	1			T429	3		T552	7		T560	2
values[33]	295	1			T429	3		T552	6		T560	2
values[34]	257	1			T429	4		T552	6		T560	2
values[35]	277	1			T429	7		T552	6		T560	2
values[36]	266	1			T429	5		T552	3		T560	2
values[37]	294	1			T429	7		T552	5		T560	2
values[38]	288	1			T429	4		T552	5		T560	3
values[39]	250	1			T429	6		T552	3		T560	2
values[40]	294	1			T429	4		T552	5		T560	2
values[41]	291	1			T429	3		T552	6		T560	2
values[42]	263	1			T429	1		T552	6		T560	2
values[43]	300	1			T429	3		T552	15		T560	2
values[44]	255	1			T429	7		T552	10		T560	2
values[45]	261	1			T429	3		T552	6		T560	2
values[46]	234	1			T429	2		T552	4		T560	2
values[47]	263	1			T429	2		T552	9		T560	2
values[48]	280	1			T429	7		T552	3		T560	2
values[49]	258	1			T429	1		T552	8		T560	2
values[50]	278	1			T429	1		T552	12		T560	2
values[51]	269	1			T429	2		T552	8		T560	2
values[52]	241	1			T429	1		T552	9		T560	2
values[53]	212	1			T429	2		T552	14		T560	2
values[54]	231	1			T429	2		T552	14		T560	2
values[55]	221	1			T429	1		T552	10		T560	3
values[56]	213	1			T429	2		T552	6		T560	2
values[57]	175	1			T429	1		T552	6		T560	2
values[58]	179	1			T429	3		T552	11		T560	2
values[59]	170	1			T429	2		T552	5		T560	2
values[60]	190	1			T429	3		T552	4		T560	2
values[61]	247	1			T429	2		T552	5		T560	2
values[62]	194	1			T429	4		T552	4		T560	2
values[63]	167	1			T429	2		T552	7		T560	2
values[64]	209	1			T429	6		T552	10		T560	2
values[65]	184	1			T429	2		T552	9		T560	2
values[66]	131	1			T429	2		T552	10		T560	2
values[67]	211	1			T429	2		T552	21		T560	2
values[68]	158	1			T429	3		T552	13		T560	2
values[69]	119	1			T429	2		T552	19		T560	2
values[70]	117	1			T429	1		T552	22		T560	2
values[71]	117	1			T429	3		T552	29		T560	2
values[72]	100	1			T429	2		T552	15		T560	2
values[73]	120	1			T429	3		T552	23		T560	2
values[74]	98	1			T429	7		T552	17		T560	2
values[75]	86	1			T429	4		T552	17		T560	2
values[76]	77	1			T429	2		T552	15		T560	2
values[77]	77	1			T429	4		T552	10		T560	2
values[78]	72	1			T429	2		T552	11		T560	2
values[79]	66	1			T429	4		T552	8		T560	2
values[80]	91	1			T429	4		T552	22		T560	2
values[81]	91	1			T429	6		T552	9		T560	2
values[82]	77	1			T429	7		T552	10		T560	2
values[83]	58	1			T429	3		T552	7		T560	2
values[84]	61	1			T429	2		T552	12		T560	2
values[85]	80	1			T429	7		T552	8		T560	2
values[86]	79	1			T429	6		T552	18		T560	2
values[87]	64	1			T429	7		T552	5		T560	2
values[88]	70	1			T429	1		T552	16		T560	2
values[89]	71	1			T429	3		T552	20		T560	2
values[90]	64	1			T429	1		T552	12		T560	2
values[91]	68	1			T429	2		T552	13		T560	3
values[92]	51	1			T429	3		T552	9		T560	2
values[93]	71	1			T429	8		T552	11		T560	2
values[94]	80	1			T429	15		T552	9		T560	2
values[95]	65	1			T429	8		T552	4		T560	2
values[96]	46	1			T429	4		T552	9		T560	2
values[97]	46	1			T429	5		T552	9		T560	2
values[98]	39	1			T429	5		T552	4		T560	2
values[99]	42	1			T429	3		T552	3		T560	2
values[100]	39	1			T429	1		T552	5		T560	2
values[101]	37	1			T429	5		T552	4		T560	2
values[102]	40	1			T429	11		T552	1		T560	2
values[103]	43	1			T429	7		T552	3		T560	2
values[104]	48	1			T429	12		T560	3		T875	2
values[105]	43	1			T429	4		T560	3		T875	2
values[106]	54	1			T429	2		T560	3		T875	1
values[107]	34	1			T429	3		T560	2		T875	2
values[108]	49	1			T429	4		T560	2		T875	4
values[109]	48	1			T429	7		T560	3		T875	1
values[110]	57	1			T429	4		T560	2		T875	4
values[111]	71	1			T429	8		T560	3		T875	8
values[112]	56	1			T429	10		T560	2		T875	4
values[113]	30	1			T429	2		T560	2		T875	1
values[114]	50	1			T429	7		T560	3		T875	2
values[115]	46	1			T429	5		T560	2		T875	2
values[116]	69	1			T429	12		T560	12		T875	5
values[117]	58	1			T429	7		T560	3		T875	3
values[118]	42	1			T429	2		T560	3		T875	1
values[119]	42	1			T429	3		T560	4		T875	1
values[120]	47	1			T429	4		T560	5		T875	3
values[121]	55	1			T429	4		T560	2		T875	4
values[122]	65	1			T429	2		T560	5		T875	11
values[123]	54	1			T429	4		T560	3		T875	10
values[124]	59	1			T429	4		T560	2		T875	14
values[125]	75	1			T429	1		T560	2		T875	26
values[126]	145	1			T560	5		T875	45		T873	3
values[127]	721	1			T560	75		T875	49		T873	28
values[128]	5463	1			T560	696		T875	29		T873	287