Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	147875	1			T71	73		T72	6		T73	4
values[2]	9869	1			T77	1		T131	5		T440	3
values[3]	3898	1			T429	92		T551	1		T552	75
values[4]	2240	1			T429	45		T551	1		T552	46
values[5]	1542	1			T429	48		T551	1		T552	28
values[6]	1092	1			T429	24		T551	1		T552	42
values[7]	719	1			T429	12		T551	1		T552	29
values[8]	578	1			T551	1		T552	40		T493	6
values[9]	486	1			T551	1		T552	32		T493	11
values[10]	383	1			T551	1		T552	28		T493	5
values[11]	370	1			T551	1		T552	11		T493	4
values[12]	329	1			T551	1		T493	2		T726	3
values[13]	296	1			T551	1		T493	1		T726	4
values[14]	327	1			T551	1		T493	1		T726	2
values[15]	268	1			T551	1		T493	3		T726	4
values[16]	268	1			T551	1		T493	3		T726	4
values[17]	315	1			T551	1		T493	1		T726	5
values[18]	285	1			T551	1		T726	5		T505	4
values[19]	333	1			T551	1		T726	4		T505	8
values[20]	342	1			T551	1		T726	4		T505	5
values[21]	291	1			T551	1		T726	6		T505	4
values[22]	298	1			T551	1		T726	5		T505	5
values[23]	361	1			T551	1		T726	8		T505	3
values[24]	329	1			T551	1		T726	5		T505	2
values[25]	315	1			T551	1		T726	5		T505	8
values[26]	320	1			T551	1		T726	1		T505	6
values[27]	283	1			T551	1		T726	1		T505	2
values[28]	283	1			T551	1		T726	5		T505	11
values[29]	281	1			T551	1		T726	6		T505	7
values[30]	293	1			T551	1		T726	4		T505	3
values[31]	298	1			T551	1		T726	2		T505	4
values[32]	279	1			T551	1		T726	2		T505	4
values[33]	256	1			T551	1		T726	5		T505	3
values[34]	250	1			T551	1		T726	1		T505	4
values[35]	302	1			T551	1		T726	5		T505	8
values[36]	326	1			T551	1		T726	1		T505	12
values[37]	334	1			T551	1		T726	2		T505	24
values[38]	281	1			T551	1		T726	4		T505	9
values[39]	279	1			T551	1		T726	4		T505	9
values[40]	281	1			T551	1		T726	6		T505	6
values[41]	272	1			T551	1		T726	5		T505	11
values[42]	285	1			T551	1		T726	6		T505	10
values[43]	240	1			T551	1		T726	3		T505	5
values[44]	274	1			T551	1		T726	1		T505	5
values[45]	280	1			T551	1		T726	2		T505	8
values[46]	263	1			T551	1		T726	3		T505	8
values[47]	230	1			T551	1		T726	2		T505	8
values[48]	250	1			T551	1		T726	5		T505	6
values[49]	280	1			T551	1		T726	7		T505	4
values[50]	239	1			T551	1		T726	6		T505	5
values[51]	231	1			T551	1		T726	6		T505	9
values[52]	236	1			T551	1		T726	9		T505	10
values[53]	223	1			T551	1		T726	3		T505	7
values[54]	232	1			T551	1		T726	2		T505	5
values[55]	241	1			T551	1		T726	3		T505	4
values[56]	183	1			T551	1		T726	1		T505	9
values[57]	199	1			T551	1		T726	3		T505	7
values[58]	240	1			T551	1		T726	4		T505	8
values[59]	206	1			T551	1		T726	4		T505	3
values[60]	182	1			T551	1		T726	9		T505	3
values[61]	161	1			T551	1		T726	4		T505	4
values[62]	179	1			T551	1		T726	2		T505	7
values[63]	168	1			T551	1		T726	2		T505	5
values[64]	175	1			T551	1		T726	16		T505	3
values[65]	161	1			T551	1		T726	20		T505	3
values[66]	155	1			T551	1		T726	11		T505	4
values[67]	114	1			T551	1		T726	17		T505	5
values[68]	122	1			T551	1		T726	4		T505	7
values[69]	72	1			T551	1		T726	3		T505	6
values[70]	64	1			T551	1		T726	3		T505	2
values[71]	54	1			T551	1		T726	3		T505	3
values[72]	70	1			T551	1		T726	4		T505	6
values[73]	69	1			T551	1		T726	5		T505	5
values[74]	58	1			T551	1		T726	2		T505	4
values[75]	64	1			T551	1		T726	1		T505	3
values[76]	57	1			T551	1		T726	4		T505	6
values[77]	62	1			T551	1		T726	2		T505	6
values[78]	52	1			T551	1		T726	3		T505	6
values[79]	52	1			T551	1		T726	4		T505	7
values[80]	52	1			T551	1		T726	3		T505	6
values[81]	46	1			T551	1		T726	1		T505	5
values[82]	48	1			T551	1		T726	4		T505	6
values[83]	54	1			T551	1		T726	4		T505	8
values[84]	43	1			T551	1		T726	5		T505	3
values[85]	59	1			T551	1		T726	1		T505	13
values[86]	50	1			T551	1		T726	2		T505	5
values[87]	50	1			T551	1		T726	2		T505	13
values[88]	52	1			T551	1		T726	1		T505	10
values[89]	55	1			T551	1		T726	1		T505	6
values[90]	54	1			T551	1		T726	3		T505	9
values[91]	54	1			T551	1		T726	5		T505	3
values[92]	56	1			T551	1		T726	2		T505	6
values[93]	54	1			T551	1		T726	2		T505	14
values[94]	52	1			T551	1		T726	1		T505	9
values[95]	49	1			T551	1		T726	2		T505	4
values[96]	45	1			T551	1		T726	2		T505	6
values[97]	51	1			T551	1		T726	2		T505	7
values[98]	61	1			T551	1		T726	4		T505	8
values[99]	64	1			T551	1		T726	3		T505	15
values[100]	56	1			T551	1		T726	2		T505	8
values[101]	61	1			T551	1		T726	4		T505	3
values[102]	61	1			T551	2		T726	1		T505	9
values[103]	64	1			T551	1		T726	1		T505	8
values[104]	62	1			T551	1		T726	3		T505	13
values[105]	85	1			T551	3		T726	4		T505	3
values[106]	66	1			T551	2		T726	4		T505	10
values[107]	71	1			T551	2		T726	2		T505	11
values[108]	83	1			T551	2		T726	2		T505	16
values[109]	79	1			T551	4		T726	3		T505	18
values[110]	64	1			T551	1		T726	1		T505	11
values[111]	66	1			T551	4		T726	2		T505	7
values[112]	81	1			T551	3		T726	4		T505	11
values[113]	60	1			T551	2		T726	2		T505	8
values[114]	72	1			T551	1		T726	6		T505	15
values[115]	61	1			T551	2		T726	6		T505	8
values[116]	56	1			T551	2		T726	5		T505	5
values[117]	59	1			T551	1		T726	2		T505	10
values[118]	56	1			T551	5		T726	5		T505	7
values[119]	51	1			T551	3		T726	2		T505	4
values[120]	56	1			T551	2		T726	3		T505	10
values[121]	48	1			T551	1		T726	3		T505	10
values[122]	45	1			T551	1		T726	7		T505	11
values[123]	64	1			T551	2		T726	3		T505	10
values[124]	54	1			T551	1		T726	6		T505	5
values[125]	74	1			T551	1		T726	7		T505	12
values[126]	124	1			T551	2		T726	11		T505	16
values[127]	688	1			T551	31		T726	3		T505	42
values[128]	6107	1			T551	358		T726	2		T505	16