Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	146148	1			T71	59		T72	7		T73	4
values[2]	11521	1			T131	8		T440	4		T464	1
values[3]	4326	1			T552	59		T880	139		T559	3
values[4]	2637	1			T552	55		T880	96		T559	4
values[5]	1827	1			T552	25		T880	54		T559	6
values[6]	1322	1			T552	9		T880	23		T559	4
values[7]	983	1			T552	8		T880	13		T559	4
values[8]	680	1			T880	2		T559	6		T726	3
values[9]	588	1			T559	2		T726	1		T882	1
values[10]	467	1			T559	6		T726	2		T882	1
values[11]	442	1			T559	2		T726	1		T882	1
values[12]	359	1			T559	3		T726	2		T882	1
values[13]	364	1			T559	1		T726	4		T882	1
values[14]	378	1			T559	2		T726	3		T882	1
values[15]	329	1			T559	1		T726	3		T882	1
values[16]	371	1			T559	2		T726	1		T882	1
values[17]	300	1			T559	1		T726	3		T882	1
values[18]	314	1			T559	1		T726	4		T882	1
values[19]	341	1			T559	1		T726	1		T882	1
values[20]	357	1			T559	2		T726	6		T882	1
values[21]	355	1			T559	2		T726	2		T882	1
values[22]	297	1			T559	1		T726	5		T882	1
values[23]	315	1			T559	3		T726	4		T882	1
values[24]	303	1			T559	1		T726	6		T882	1
values[25]	325	1			T559	2		T726	4		T882	1
values[26]	322	1			T559	2		T726	1		T882	1
values[27]	345	1			T559	4		T726	2		T882	1
values[28]	315	1			T559	2		T726	6		T882	1
values[29]	363	1			T559	6		T726	9		T882	1
values[30]	343	1			T559	1		T726	2		T882	1
values[31]	349	1			T559	9		T726	6		T882	1
values[32]	323	1			T559	6		T726	2		T882	1
values[33]	359	1			T559	2		T726	1		T882	1
values[34]	339	1			T559	2		T726	3		T882	1
values[35]	345	1			T559	1		T726	5		T882	1
values[36]	309	1			T559	3		T726	1		T882	1
values[37]	331	1			T559	2		T726	3		T882	1
values[38]	315	1			T559	6		T726	1		T882	1
values[39]	309	1			T559	4		T726	1		T882	1
values[40]	254	1			T559	2		T726	2		T882	1
values[41]	296	1			T559	2		T726	2		T882	1
values[42]	313	1			T559	4		T726	3		T882	1
values[43]	310	1			T559	5		T726	3		T882	1
values[44]	308	1			T559	3		T726	1		T882	1
values[45]	299	1			T559	1		T726	2		T882	1
values[46]	313	1			T559	3		T726	1		T882	1
values[47]	266	1			T559	7		T726	4		T882	1
values[48]	286	1			T559	5		T726	3		T882	1
values[49]	309	1			T559	1		T726	4		T882	1
values[50]	230	1			T559	3		T726	2		T882	1
values[51]	239	1			T559	2		T726	3		T882	1
values[52]	280	1			T559	6		T726	4		T882	1
values[53]	255	1			T559	2		T726	7		T882	1
values[54]	276	1			T559	3		T726	5		T882	1
values[55]	258	1			T559	4		T726	8		T882	1
values[56]	269	1			T559	1		T726	7		T882	1
values[57]	287	1			T559	3		T726	1		T882	1
values[58]	204	1			T559	1		T726	10		T882	1
values[59]	208	1			T559	2		T726	20		T882	1
values[60]	201	1			T559	2		T726	7		T882	1
values[61]	221	1			T559	2		T726	3		T882	1
values[62]	216	1			T559	4		T726	8		T882	1
values[63]	186	1			T559	4		T726	3		T882	1
values[64]	168	1			T559	7		T726	6		T882	1
values[65]	176	1			T559	1		T726	3		T882	2
values[66]	200	1			T559	1		T726	10		T882	1
values[67]	148	1			T559	2		T726	1		T882	1
values[68]	169	1			T559	2		T726	1		T882	1
values[69]	211	1			T559	2		T726	3		T882	1
values[70]	166	1			T559	2		T726	2		T882	1
values[71]	117	1			T559	2		T726	1		T882	1
values[72]	115	1			T559	1		T726	3		T882	1
values[73]	145	1			T559	1		T726	1		T882	1
values[74]	137	1			T559	2		T726	4		T882	1
values[75]	153	1			T559	1		T726	3		T882	1
values[76]	126	1			T559	5		T726	2		T882	1
values[77]	113	1			T559	4		T726	1		T882	1
values[78]	113	1			T559	2		T726	6		T882	1
values[79]	98	1			T559	2		T726	11		T882	1
values[80]	93	1			T559	3		T726	8		T882	1
values[81]	83	1			T559	2		T726	7		T882	1
values[82]	93	1			T559	4		T726	2		T882	1
values[83]	69	1			T559	2		T726	3		T882	1
values[84]	78	1			T559	4		T726	5		T882	1
values[85]	78	1			T559	2		T726	5		T882	1
values[86]	91	1			T559	7		T726	6		T882	1
values[87]	91	1			T559	5		T726	5		T882	1
values[88]	113	1			T559	10		T726	10		T882	1
values[89]	105	1			T559	1		T726	12		T882	1
values[90]	98	1			T559	3		T726	13		T882	1
values[91]	102	1			T559	2		T726	15		T882	1
values[92]	70	1			T559	1		T726	6		T882	1
values[93]	90	1			T559	9		T726	5		T882	1
values[94]	100	1			T559	6		T726	3		T882	1
values[95]	100	1			T559	5		T726	8		T882	1
values[96]	104	1			T559	5		T726	7		T882	1
values[97]	100	1			T559	3		T726	3		T882	1
values[98]	86	1			T559	3		T726	5		T882	1
values[99]	84	1			T559	1		T726	5		T882	3
values[100]	73	1			T559	3		T726	3		T882	3
values[101]	84	1			T559	4		T882	2		T535	4
values[102]	61	1			T559	2		T882	1		T535	4
values[103]	92	1			T559	6		T882	1		T535	8
values[104]	83	1			T559	5		T882	1		T535	6
values[105]	92	1			T559	8		T882	1		T535	4
values[106]	80	1			T559	9		T882	1		T535	3
values[107]	83	1			T559	12		T882	2		T535	4
values[108]	58	1			T559	3		T882	2		T535	2
values[109]	72	1			T559	3		T882	3		T535	5
values[110]	74	1			T559	2		T882	2		T535	4
values[111]	68	1			T559	1		T882	2		T535	5
values[112]	80	1			T559	1		T882	3		T535	2
values[113]	69	1			T559	3		T882	2		T535	1
values[114]	78	1			T559	5		T882	2		T535	3
values[115]	65	1			T559	2		T882	1		T535	2
values[116]	78	1			T559	9		T882	1		T535	4
values[117]	78	1			T559	4		T882	7		T535	3
values[118]	75	1			T559	11		T882	1		T535	2
values[119]	85	1			T559	8		T882	2		T535	2
values[120]	72	1			T559	3		T882	1		T535	2
values[121]	69	1			T559	3		T882	4		T535	2
values[122]	64	1			T559	3		T882	3		T535	1
values[123]	82	1			T559	6		T882	1		T535	6
values[124]	84	1			T559	4		T882	1		T535	2
values[125]	103	1			T559	3		T882	1		T535	5
values[126]	185	1			T559	10		T882	8		T535	7
values[127]	899	1			T559	38		T882	29		T535	3
values[128]	6447	1			T559	26		T882	371		T535	1