Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	145552	1			T71	48		T72	6		T73	5
values[2]	11390	1			T71	2		T131	8		T440	6
values[3]	4796	1			T564	1		T551	1		T502	1
values[4]	2909	1			T551	1		T740	2		T726	22
values[5]	1763	1			T551	1		T740	2		T726	17
values[6]	1204	1			T551	1		T740	2		T726	17
values[7]	899	1			T551	1		T740	2		T726	9
values[8]	753	1			T551	1		T740	2		T726	9
values[9]	701	1			T551	1		T740	2		T726	9
values[10]	505	1			T551	1		T740	2		T726	7
values[11]	435	1			T551	1		T740	2		T726	7
values[12]	396	1			T551	1		T740	2		T726	10
values[13]	406	1			T551	1		T740	2		T726	9
values[14]	337	1			T551	1		T740	2		T726	8
values[15]	290	1			T551	1		T740	2		T726	1
values[16]	330	1			T551	1		T740	2		T726	3
values[17]	300	1			T551	1		T740	2		T726	2
values[18]	332	1			T551	1		T740	2		T726	3
values[19]	346	1			T551	1		T740	2		T726	4
values[20]	293	1			T551	1		T740	2		T726	4
values[21]	276	1			T551	1		T740	2		T726	2
values[22]	289	1			T551	1		T740	2		T726	4
values[23]	282	1			T551	1		T740	2		T726	2
values[24]	337	1			T551	1		T740	2		T726	2
values[25]	332	1			T551	1		T740	2		T726	8
values[26]	281	1			T551	1		T740	2		T726	3
values[27]	261	1			T551	1		T740	2		T726	1
values[28]	280	1			T551	1		T740	2		T726	2
values[29]	292	1			T551	1		T740	2		T726	2
values[30]	315	1			T551	1		T740	2		T726	3
values[31]	327	1			T551	1		T740	2		T726	2
values[32]	316	1			T551	1		T740	2		T726	3
values[33]	301	1			T551	1		T740	2		T505	11
values[34]	276	1			T551	1		T740	2		T505	10
values[35]	275	1			T551	1		T740	2		T505	7
values[36]	239	1			T551	1		T740	2		T505	5
values[37]	266	1			T551	1		T740	2		T505	12
values[38]	250	1			T551	1		T740	2		T505	9
values[39]	262	1			T551	1		T740	2		T505	12
values[40]	263	1			T551	1		T740	2		T505	20
values[41]	269	1			T551	1		T740	2		T505	17
values[42]	273	1			T551	1		T740	2		T505	12
values[43]	269	1			T551	1		T740	2		T505	12
values[44]	273	1			T551	1		T740	2		T505	8
values[45]	260	1			T551	1		T740	2		T505	11
values[46]	272	1			T551	1		T740	2		T505	9
values[47]	263	1			T551	1		T740	2		T505	6
values[48]	252	1			T551	1		T740	2		T505	7
values[49]	237	1			T551	1		T740	2		T505	5
values[50]	228	1			T551	1		T740	2		T505	8
values[51]	239	1			T551	1		T740	2		T505	13
values[52]	244	1			T551	1		T740	2		T505	4
values[53]	240	1			T551	1		T740	2		T505	18
values[54]	261	1			T551	1		T740	2		T505	16
values[55]	209	1			T551	1		T740	2		T505	9
values[56]	206	1			T551	1		T740	2		T505	9
values[57]	222	1			T551	1		T740	2		T505	9
values[58]	178	1			T551	1		T740	2		T505	4
values[59]	193	1			T551	1		T740	2		T505	8
values[60]	209	1			T551	1		T740	2		T505	10
values[61]	170	1			T551	1		T740	2		T505	9
values[62]	175	1			T551	1		T740	2		T505	7
values[63]	122	1			T551	1		T740	2		T505	8
values[64]	141	1			T551	1		T740	2		T505	10
values[65]	133	1			T551	1		T740	2		T505	12
values[66]	136	1			T551	1		T740	2		T505	14
values[67]	134	1			T551	1		T740	2		T505	8
values[68]	117	1			T551	1		T740	2		T505	7
values[69]	125	1			T551	1		T740	2		T505	11
values[70]	127	1			T551	1		T740	2		T505	13
values[71]	161	1			T551	1		T740	2		T505	12
values[72]	164	1			T551	1		T740	2		T505	11
values[73]	121	1			T551	1		T740	2		T505	18
values[74]	126	1			T551	1		T740	2		T505	16
values[75]	127	1			T551	1		T740	2		T505	13
values[76]	123	1			T551	1		T740	2		T505	15
values[77]	105	1			T551	1		T740	2		T505	14
values[78]	114	1			T551	1		T740	2		T505	10
values[79]	101	1			T551	1		T740	2		T505	9
values[80]	98	1			T551	1		T740	2		T505	4
values[81]	94	1			T551	1		T740	2		T505	6
values[82]	90	1			T551	1		T740	2		T505	7
values[83]	108	1			T551	1		T740	2		T505	11
values[84]	115	1			T551	1		T740	2		T505	11
values[85]	92	1			T551	1		T740	2		T505	9
values[86]	75	1			T551	1		T740	2		T505	8
values[87]	91	1			T551	1		T740	2		T505	16
values[88]	93	1			T551	1		T740	2		T505	11
values[89]	99	1			T551	1		T740	2		T505	8
values[90]	94	1			T551	1		T740	2		T505	13
values[91]	87	1			T551	1		T740	2		T505	4
values[92]	100	1			T551	2		T740	2		T505	9
values[93]	105	1			T551	2		T740	2		T505	5
values[94]	87	1			T551	2		T740	2		T505	7
values[95]	93	1			T551	4		T740	2		T505	9
values[96]	91	1			T551	4		T740	4		T505	9
values[97]	76	1			T551	1		T740	3		T505	8
values[98]	77	1			T551	3		T740	4		T505	11
values[99]	74	1			T551	3		T740	5		T505	15
values[100]	88	1			T551	1		T740	2		T505	20
values[101]	91	1			T551	2		T740	2		T505	16
values[102]	76	1			T551	2		T740	2		T505	13
values[103]	87	1			T551	3		T740	10		T505	13
values[104]	72	1			T551	1		T740	4		T505	9
values[105]	82	1			T551	1		T740	7		T505	7
values[106]	86	1			T551	3		T740	4		T505	8
values[107]	81	1			T551	2		T740	2		T505	8
values[108]	89	1			T551	1		T740	7		T505	11
values[109]	97	1			T551	1		T740	6		T505	10
values[110]	91	1			T551	2		T740	12		T505	9
values[111]	73	1			T551	3		T740	4		T505	7
values[112]	71	1			T551	2		T740	2		T505	12
values[113]	90	1			T551	1		T740	6		T505	13
values[114]	71	1			T551	2		T740	7		T505	8
values[115]	83	1			T551	5		T740	4		T505	17
values[116]	67	1			T551	2		T740	4		T505	17
values[117]	64	1			T551	1		T740	2		T505	6
values[118]	56	1			T551	1		T740	2		T505	6
values[119]	68	1			T551	1		T740	6		T505	15
values[120]	66	1			T551	1		T740	2		T505	11
values[121]	84	1			T551	7		T740	3		T505	7
values[122]	56	1			T551	2		T740	2		T505	9
values[123]	74	1			T551	2		T740	4		T505	16
values[124]	51	1			T551	2		T740	3		T505	11
values[125]	77	1			T551	1		T740	3		T505	14
values[126]	130	1			T551	2		T740	8		T505	57
values[127]	720	1			T551	28		T740	72		T505	121
values[128]	5683	1			T551	342		T740	693		T505	55