Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	173070	1			T71	59		T72	6		T73	5
values[2]	4616	1			T73	1		T131	3		T440	2
values[3]	2467	1			T429	14		T551	1		T552	12
values[4]	1940	1			T429	16		T551	1		T552	7
values[5]	1667	1			T429	20		T551	1		T552	22
values[6]	1431	1			T429	33		T551	1		T552	38
values[7]	1374	1			T429	24		T551	1		T552	65
values[8]	1120	1			T429	18		T551	1		T552	51
values[9]	999	1			T429	18		T551	1		T552	49
values[10]	812	1			T429	14		T551	1		T552	39
values[11]	709	1			T429	9		T551	1		T552	15
values[12]	600	1			T429	16		T551	1		T552	8
values[13]	623	1			T429	20		T551	1		T552	8
values[14]	564	1			T429	19		T551	1		T552	11
values[15]	540	1			T429	25		T551	1		T552	15
values[16]	479	1			T429	19		T551	1		T552	17
values[17]	479	1			T429	42		T551	1		T552	8
values[18]	398	1			T429	23		T551	1		T552	8
values[19]	335	1			T429	21		T551	1		T552	3
values[20]	403	1			T429	27		T551	1		T552	11
values[21]	390	1			T429	22		T551	1		T552	18
values[22]	426	1			T429	31		T551	1		T552	18
values[23]	271	1			T429	15		T551	1		T552	9
values[24]	262	1			T429	14		T551	1		T552	2
values[25]	218	1			T429	8		T551	1		T552	2
values[26]	234	1			T429	21		T551	1		T552	3
values[27]	244	1			T429	18		T551	1		T552	3
values[28]	230	1			T429	7		T551	1		T552	4
values[29]	257	1			T429	2		T551	1		T552	6
values[30]	244	1			T551	1		T552	1		T560	1
values[31]	225	1			T551	1		T552	1		T560	1
values[32]	268	1			T551	1		T552	2		T560	1
values[33]	302	1			T551	1		T552	1		T560	1
values[34]	230	1			T551	1		T552	1		T560	1
values[35]	232	1			T551	1		T552	5		T560	1
values[36]	191	1			T551	1		T552	5		T560	1
values[37]	185	1			T551	1		T552	2		T560	1
values[38]	184	1			T551	1		T552	1		T560	1
values[39]	150	1			T551	1		T552	3		T560	1
values[40]	150	1			T551	1		T552	5		T560	1
values[41]	154	1			T551	1		T552	4		T560	1
values[42]	119	1			T551	1		T552	3		T560	1
values[43]	93	1			T551	1		T552	1		T560	1
values[44]	60	1			T551	1		T552	1		T560	1
values[45]	59	1			T551	1		T552	2		T560	1
values[46]	69	1			T551	1		T552	4		T560	1
values[47]	66	1			T551	1		T552	1		T560	1
values[48]	70	1			T551	1		T552	3		T560	1
values[49]	49	1			T551	1		T552	3		T560	1
values[50]	54	1			T551	1		T552	1		T560	1
values[51]	46	1			T551	1		T552	3		T560	1
values[52]	47	1			T551	1		T552	1		T560	1
values[53]	56	1			T551	1		T552	1		T560	1
values[54]	40	1			T551	1		T552	2		T560	1
values[55]	43	1			T551	1		T552	2		T560	1
values[56]	49	1			T551	1		T552	4		T560	1
values[57]	37	1			T551	1		T552	1		T560	1
values[58]	42	1			T551	1		T552	3		T560	1
values[59]	42	1			T551	1		T552	2		T560	1
values[60]	52	1			T551	1		T552	1		T560	1
values[61]	52	1			T551	1		T552	2		T560	1
values[62]	43	1			T551	1		T552	1		T560	1
values[63]	45	1			T551	1		T552	1		T560	1
values[64]	48	1			T551	1		T552	1		T560	1
values[65]	51	1			T551	1		T552	1		T560	1
values[66]	57	1			T551	1		T552	2		T560	1
values[67]	57	1			T551	1		T552	2		T560	1
values[68]	52	1			T551	1		T552	1		T560	1
values[69]	56	1			T551	1		T552	3		T560	1
values[70]	49	1			T551	1		T552	2		T560	1
values[71]	41	1			T551	1		T552	3		T560	1
values[72]	40	1			T551	1		T552	2		T560	1
values[73]	51	1			T551	1		T552	4		T560	1
values[74]	62	1			T551	1		T552	1		T560	1
values[75]	63	1			T551	1		T552	1		T560	4
values[76]	56	1			T551	1		T552	5		T560	4
values[77]	60	1			T551	1		T552	2		T560	2
values[78]	57	1			T551	1		T552	2		T560	1
values[79]	65	1			T551	1		T552	1		T560	6
values[80]	70	1			T551	1		T552	1		T560	1
values[81]	73	1			T551	1		T552	9		T560	3
values[82]	72	1			T551	1		T552	8		T560	4
values[83]	56	1			T551	1		T552	7		T560	4
values[84]	58	1			T551	1		T552	2		T560	3
values[85]	65	1			T551	1		T552	4		T560	1
values[86]	65	1			T551	1		T552	2		T560	1
values[87]	62	1			T551	1		T552	2		T560	3
values[88]	56	1			T551	1		T552	6		T560	7
values[89]	64	1			T551	1		T552	8		T560	4
values[90]	64	1			T551	1		T552	7		T560	4
values[91]	51	1			T551	1		T552	3		T560	4
values[92]	70	1			T551	1		T552	4		T560	2
values[93]	78	1			T551	1		T552	2		T560	1
values[94]	64	1			T551	1		T552	4		T560	2
values[95]	58	1			T551	1		T552	5		T560	1
values[96]	69	1			T551	1		T552	7		T560	1
values[97]	73	1			T551	1		T552	2		T560	3
values[98]	67	1			T551	1		T552	2		T560	4
values[99]	73	1			T551	1		T552	8		T560	1
values[100]	71	1			T551	4		T552	3		T560	3
values[101]	78	1			T551	5		T552	5		T560	1
values[102]	82	1			T551	4		T552	6		T560	3
values[103]	74	1			T551	7		T552	3		T560	3
values[104]	64	1			T551	1		T552	5		T560	1
values[105]	88	1			T551	3		T552	8		T560	4
values[106]	74	1			T551	3		T552	2		T560	3
values[107]	66	1			T551	5		T552	1		T560	1
values[108]	67	1			T551	2		T552	4		T560	1
values[109]	90	1			T551	1		T552	5		T560	1
values[110]	86	1			T551	1		T552	8		T560	2
values[111]	88	1			T551	1		T552	6		T560	1
values[112]	73	1			T551	1		T552	4		T560	1
values[113]	76	1			T551	1		T552	3		T560	3
values[114]	90	1			T551	2		T552	4		T560	4
values[115]	85	1			T551	2		T552	13		T560	2
values[116]	99	1			T551	4		T552	5		T560	3
values[117]	97	1			T551	2		T552	4		T560	1
values[118]	88	1			T551	5		T552	1		T560	1
values[119]	78	1			T551	1		T552	4		T560	1
values[120]	80	1			T551	1		T552	6		T560	1
values[121]	84	1			T551	1		T552	10		T560	2
values[122]	104	1			T551	5		T552	11		T560	1
values[123]	129	1			T551	2		T552	2		T560	3
values[124]	215	1			T551	5		T552	12		T560	4
values[125]	383	1			T551	1		T552	16		T560	4
values[126]	708	1			T551	11		T552	24		T560	11
values[127]	2512	1			T551	93		T552	16		T560	90
values[128]	4312	1			T551	198		T552	1		T560	195