Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
123133 | 
1 | 
 | 
 | 
T71 | 
49 | 
 | 
T72 | 
3 | 
 | 
T73 | 
1 | 
| auto[1] | 
70595 | 
1 | 
 | 
 | 
T71 | 
19 | 
 | 
T72 | 
4 | 
 | 
T73 | 
1 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
48793 | 
1 | 
 | 
 | 
T71 | 
13 | 
 | 
T72 | 
3 | 
 | 
T77 | 
1 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
135801 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
57927 | 
1 | 
 | 
 | 
T71 | 
10 | 
 | 
T72 | 
1 | 
 | 
T77 | 
4 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
15394 | 
1 | 
 | 
 | 
T71 | 
2 | 
 | 
T72 | 
1 | 
 | 
T131 | 
47 | 
 
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
131981 | 
1 | 
 | 
 | 
T71 | 
29 | 
 | 
T77 | 
15 | 
 | 
T131 | 
514 | 
| auto[1] | 
72251 | 
1 | 
 | 
 | 
T71 | 
33 | 
 | 
T73 | 
5 | 
 | 
T77 | 
13 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
50781 | 
1 | 
 | 
 | 
T71 | 
8 | 
 | 
T73 | 
2 | 
 | 
T77 | 
5 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
143724 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
60508 | 
1 | 
 | 
 | 
T71 | 
12 | 
 | 
T73 | 
1 | 
 | 
T77 | 
7 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
15747 | 
1 | 
 | 
 | 
T77 | 
3 | 
 | 
T131 | 
67 | 
 | 
T555 | 
2 | 
 
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
134660 | 
1 | 
 | 
 | 
T71 | 
45 | 
 | 
T72 | 
1 | 
 | 
T77 | 
13 | 
| auto[1] | 
69609 | 
1 | 
 | 
 | 
T71 | 
6 | 
 | 
T72 | 
5 | 
 | 
T73 | 
2 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
50669 | 
1 | 
 | 
 | 
T71 | 
5 | 
 | 
T72 | 
1 | 
 | 
T73 | 
1 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
143854 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
60415 | 
1 | 
 | 
 | 
T71 | 
14 | 
 | 
T72 | 
3 | 
 | 
T77 | 
5 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
15638 | 
1 | 
 | 
 | 
T71 | 
2 | 
 | 
T131 | 
102 | 
 | 
T555 | 
1 | 
 
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
127834 | 
1 | 
 | 
 | 
T71 | 
42 | 
 | 
T72 | 
5 | 
 | 
T73 | 
4 | 
| auto[1] | 
69379 | 
1 | 
 | 
 | 
T71 | 
8 | 
 | 
T72 | 
1 | 
 | 
T73 | 
1 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
48508 | 
1 | 
 | 
 | 
T71 | 
4 | 
 | 
T72 | 
3 | 
 | 
T73 | 
1 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
138954 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
58259 | 
1 | 
 | 
 | 
T71 | 
10 | 
 | 
T72 | 
1 | 
 | 
T73 | 
1 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
15022 | 
1 | 
 | 
 | 
T71 | 
2 | 
 | 
T77 | 
1 | 
 | 
T131 | 
30 | 
 
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
129713 | 
1 | 
 | 
 | 
T71 | 
37 | 
 | 
T72 | 
2 | 
 | 
T73 | 
3 | 
| auto[1] | 
71470 | 
1 | 
 | 
 | 
T71 | 
18 | 
 | 
T72 | 
3 | 
 | 
T77 | 
1 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
49955 | 
1 | 
 | 
 | 
T71 | 
5 | 
 | 
T72 | 
1 | 
 | 
T73 | 
1 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
140556 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
60627 | 
1 | 
 | 
 | 
T71 | 
13 | 
 | 
T72 | 
2 | 
 | 
T73 | 
2 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
15777 | 
1 | 
 | 
 | 
T71 | 
3 | 
 | 
T72 | 
1 | 
 | 
T131 | 
94 |