Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	470	1			T555	1		T440	1		T552	1
all_values[1]	474	1			T131	1		T552	1		T731	5
all_values[2]	485	1			T131	1		T440	1		T552	2
all_values[3]	490	1			T440	2		T552	1		T731	4
all_values[4]	480	1			T131	1		T874	1		T552	1
all_values[5]	497	1			T131	1		T440	3		T429	1
all_values[6]	461	1			T131	1		T440	1		T552	1
all_values[7]	494	1			T131	1		T555	1		T440	1
all_values[8]	466	1			T555	1		T440	2		T429	1
all_values[9]	511	1			T131	1		T731	7		T871	10
all_values[10]	506	1			T440	1		T429	2		T551	1
all_values[11]	486	1			T555	2		T440	3		T429	2
all_values[12]	501	1			T555	3		T429	2		T731	2
all_values[13]	477	1			T131	1		T555	2		T440	1
all_values[14]	540	1			T555	1		T440	1		T429	1
all_values[15]	508	1			T131	2		T440	1		T429	1
all_values[16]	509	1			T555	1		T440	4		T429	1
all_values[17]	489	1			T440	2		T429	3		T731	5
all_values[18]	468	1			T440	2		T429	1		T552	2
all_values[19]	519	1			T552	1		T731	4		T871	6
all_values[20]	503	1			T440	4		T731	4		T871	4
all_values[21]	452	1			T440	1		T874	1		T552	1
all_values[22]	511	1			T555	1		T440	4		T731	10
all_values[23]	492	1			T555	1		T429	1		T731	3
all_values[24]	498	1			T131	1		T440	3		T429	1
all_values[25]	486	1			T131	1		T555	1		T440	2
all_values[26]	478	1			T440	3		T551	1		T731	4
all_values[27]	496	1			T555	2		T552	1		T731	2
all_values[28]	500	1			T440	1		T429	1		T552	1
all_values[29]	503	1			T131	1		T555	1		T440	1
all_values[30]	494	1			T440	1		T731	3		T560	1
all_values[31]	499	1			T440	2		T731	3		T871	3
all_values[32]	464	1			T131	1		T440	1		T883	1
all_values[33]	504	1			T440	3		T429	1		T552	2
all_values[34]	466	1			T131	1		T440	2		T551	1
all_values[35]	474	1			T555	3		T440	1		T874	1
all_values[36]	508	1			T555	1		T440	3		T731	2
all_values[37]	516	1			T555	2		T440	2		T429	1
all_values[38]	512	1			T429	1		T731	6		T871	6
all_values[39]	499	1			T555	1		T440	1		T731	1
all_values[40]	510	1			T555	1		T440	1		T883	1
all_values[41]	469	1			T131	2		T440	1		T731	2
all_values[42]	461	1			T555	1		T440	2		T429	1
all_values[43]	515	1			T552	1		T731	2		T871	4
all_values[44]	531	1			T552	1		T731	3		T871	4
all_values[45]	489	1			T555	2		T440	3		T429	1
all_values[46]	476	1			T440	1		T429	1		T731	2
all_values[47]	438	1			T440	2		T731	1		T871	1
all_values[48]	533	1			T440	2		T429	4		T552	1
all_values[49]	488	1			T555	2		T440	1		T731	1