Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3654	1			T131	1		T440	11		T429	5
all_values[1]	3689	1			T131	3		T440	13		T429	1
all_values[2]	3720	1			T131	2		T440	13		T429	4
all_values[3]	3750	1			T131	5		T440	11		T429	5
all_values[4]	3842	1			T131	2		T555	1		T440	15
all_values[5]	3747	1			T131	1		T440	16		T429	2
all_values[6]	3649	1			T440	23		T429	8		T437	3
all_values[7]	3723	1			T131	4		T440	17		T429	4
all_values[8]	3765	1			T131	2		T440	6		T429	3
all_values[9]	3708	1			T131	2		T555	1		T440	8
all_values[10]	3715	1			T440	17		T429	1		T437	1
all_values[11]	3739	1			T555	1		T440	17		T429	5
all_values[12]	3697	1			T131	1		T555	2		T440	14
all_values[13]	3866	1			T131	2		T555	1		T440	9
all_values[14]	3794	1			T131	3		T555	1		T440	11
all_values[15]	3749	1			T131	1		T555	1		T440	10
all_values[16]	3739	1			T131	2		T440	11		T429	4
all_values[17]	3710	1			T131	1		T440	20		T429	3
all_values[18]	3706	1			T131	3		T555	2		T440	17
all_values[19]	3756	1			T131	5		T440	8		T429	1
all_values[20]	3740	1			T131	2		T440	12		T429	7
all_values[21]	3726	1			T131	1		T440	11		T429	8
all_values[22]	3816	1			T131	3		T555	1		T440	10
all_values[23]	3651	1			T131	2		T440	11		T429	2
all_values[24]	3724	1			T131	2		T440	18		T429	5
all_values[25]	3771	1			T131	2		T440	8		T429	2
all_values[26]	3689	1			T131	5		T440	12		T429	3
all_values[27]	3736	1			T131	1		T440	14		T429	3
all_values[28]	3672	1			T131	2		T555	1		T440	10
all_values[29]	3786	1			T131	4		T440	13		T429	3
all_values[30]	3740	1			T131	2		T440	13		T437	3
all_values[31]	3763	1			T131	2		T440	12		T429	2
all_values[32]	3747	1			T131	3		T440	9		T429	2
all_values[33]	3686	1			T440	13		T429	8		T437	4
all_values[34]	3761	1			T131	1		T440	14		T429	3
all_values[35]	3722	1			T131	3		T440	7		T429	5
all_values[36]	3664	1			T131	2		T555	1		T440	10
all_values[37]	3680	1			T131	2		T440	9		T429	3
all_values[38]	3803	1			T131	3		T440	13		T429	4
all_values[39]	3728	1			T131	3		T440	10		T429	2
all_values[40]	3651	1			T131	4		T440	11		T429	5
all_values[41]	3624	1			T131	2		T440	13		T429	5
all_values[42]	3788	1			T131	1		T555	1		T440	14
all_values[43]	3756	1			T131	4		T440	14		T429	8
all_values[44]	3685	1			T131	1		T440	14		T429	6
all_values[45]	3666	1			T131	1		T440	8		T429	6
all_values[46]	3736	1			T555	2		T440	17		T429	2
all_values[47]	3672	1			T131	1		T555	1		T440	14
all_values[48]	3693	1			T131	2		T440	12		T429	4
all_values[49]	3648	1			T131	2		T440	21		T429	4
all_values[50]	3722	1			T131	1		T440	12		T429	3
all_values[51]	3719	1			T131	3		T555	1		T440	11
all_values[52]	3769	1			T131	3		T440	9		T429	2
all_values[53]	3718	1			T131	4		T440	16		T429	4
all_values[54]	3592	1			T131	1		T440	9		T429	5
all_values[55]	3730	1			T131	3		T440	10		T429	4
all_values[56]	3627	1			T131	6		T440	7		T429	2
all_values[57]	3773	1			T440	17		T429	4		T437	1
all_values[58]	3806	1			T131	2		T555	1		T440	18
all_values[59]	3873	1			T131	2		T440	9		T429	6
all_values[60]	3699	1			T131	2		T440	7		T429	5
all_values[61]	3795	1			T131	1		T440	8		T429	4
all_values[62]	3803	1			T131	4		T440	9		T429	4
all_values[63]	3777	1			T131	2		T440	9		T429	1