Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	151132	1			T78	50		T79	7		T80	65
values[2]	4706	1			T513	6		T504	82		T521	2
values[3]	2344	1			T513	2		T504	73		T438	1
values[4]	1610	1			T513	3		T504	70		T438	1
values[5]	1336	1			T513	4		T504	57		T895	1
values[6]	1106	1			T513	2		T504	34		T895	1
values[7]	842	1			T513	11		T504	44		T895	1
values[8]	627	1			T513	9		T504	38		T895	1
values[9]	481	1			T513	3		T504	26		T895	1
values[10]	404	1			T513	2		T504	3		T895	1
values[11]	354	1			T513	1		T895	1		T891	1
values[12]	333	1			T513	2		T895	1		T891	1
values[13]	319	1			T513	5		T895	1		T891	1
values[14]	331	1			T513	2		T895	1		T891	1
values[15]	368	1			T513	3		T895	1		T891	1
values[16]	320	1			T513	6		T895	1		T891	1
values[17]	228	1			T513	2		T895	1		T891	1
values[18]	197	1			T513	1		T895	1		T891	1
values[19]	149	1			T513	1		T895	1		T891	1
values[20]	145	1			T513	2		T895	1		T891	1
values[21]	161	1			T513	3		T895	1		T891	1
values[22]	199	1			T513	2		T895	1		T891	1
values[23]	157	1			T513	4		T895	1		T891	1
values[24]	139	1			T513	2		T895	1		T891	1
values[25]	147	1			T513	1		T895	1		T891	1
values[26]	138	1			T513	2		T895	1		T891	1
values[27]	152	1			T513	5		T895	1		T891	1
values[28]	148	1			T513	4		T895	1		T891	1
values[29]	104	1			T513	4		T895	1		T891	1
values[30]	97	1			T513	1		T895	1		T891	1
values[31]	88	1			T513	1		T895	1		T891	1
values[32]	78	1			T513	2		T895	1		T891	1
values[33]	92	1			T513	2		T895	1		T891	1
values[34]	75	1			T513	3		T895	1		T891	1
values[35]	82	1			T513	7		T895	1		T891	1
values[36]	80	1			T513	4		T895	1		T891	1
values[37]	97	1			T513	4		T895	1		T891	1
values[38]	95	1			T513	3		T895	1		T891	1
values[39]	98	1			T513	2		T895	1		T891	1
values[40]	94	1			T513	3		T895	1		T891	1
values[41]	86	1			T513	2		T895	1		T891	1
values[42]	110	1			T513	1		T895	1		T891	1
values[43]	90	1			T513	1		T895	1		T891	1
values[44]	72	1			T513	1		T895	1		T891	1
values[45]	80	1			T513	3		T895	1		T891	1
values[46]	72	1			T513	3		T895	1		T891	1
values[47]	65	1			T513	4		T895	1		T891	1
values[48]	60	1			T513	3		T895	1		T891	1
values[49]	60	1			T513	4		T895	1		T891	1
values[50]	55	1			T513	3		T895	1		T891	1
values[51]	62	1			T513	2		T895	1		T891	1
values[52]	61	1			T513	3		T895	1		T891	1
values[53]	57	1			T513	4		T895	1		T891	1
values[54]	55	1			T513	3		T895	1		T891	1
values[55]	54	1			T513	3		T895	1		T891	1
values[56]	56	1			T513	6		T895	1		T891	1
values[57]	66	1			T513	7		T895	1		T891	1
values[58]	57	1			T513	1		T895	1		T891	1
values[59]	56	1			T513	2		T895	1		T891	1
values[60]	55	1			T513	4		T895	1		T891	1
values[61]	66	1			T513	3		T895	1		T891	1
values[62]	60	1			T513	3		T895	1		T891	1
values[63]	59	1			T513	3		T895	1		T891	1
values[64]	69	1			T513	3		T895	1		T891	1
values[65]	60	1			T513	2		T895	1		T891	1
values[66]	68	1			T513	3		T895	1		T891	1
values[67]	64	1			T513	1		T895	1		T891	1
values[68]	70	1			T513	4		T895	1		T891	1
values[69]	59	1			T513	5		T895	1		T891	1
values[70]	71	1			T513	5		T895	1		T891	1
values[71]	64	1			T513	2		T895	1		T891	1
values[72]	58	1			T513	4		T895	1		T891	1
values[73]	62	1			T513	4		T895	1		T891	1
values[74]	66	1			T513	5		T895	1		T891	1
values[75]	67	1			T513	3		T895	1		T891	1
values[76]	67	1			T513	6		T895	1		T891	1
values[77]	66	1			T513	8		T895	1		T891	1
values[78]	65	1			T513	7		T895	1		T891	1
values[79]	78	1			T513	5		T895	1		T891	1
values[80]	107	1			T513	8		T895	1		T891	1
values[81]	79	1			T513	6		T895	1		T891	1
values[82]	75	1			T513	5		T895	1		T891	1
values[83]	93	1			T513	6		T895	1		T891	1
values[84]	63	1			T513	5		T895	1		T891	1
values[85]	87	1			T513	8		T895	1		T891	1
values[86]	96	1			T513	17		T895	1		T891	2
values[87]	85	1			T513	9		T895	1		T891	1
values[88]	77	1			T513	3		T895	1		T891	1
values[89]	80	1			T513	1		T895	1		T891	1
values[90]	94	1			T513	4		T895	1		T891	1
values[91]	75	1			T513	5		T895	1		T891	1
values[92]	68	1			T513	6		T895	1		T891	1
values[93]	91	1			T513	5		T895	1		T891	1
values[94]	84	1			T513	9		T895	1		T891	1
values[95]	89	1			T513	7		T895	1		T891	1
values[96]	71	1			T513	3		T895	1		T891	1
values[97]	75	1			T513	3		T895	1		T891	1
values[98]	62	1			T513	1		T895	1		T891	1
values[99]	82	1			T513	4		T895	1		T891	1
values[100]	105	1			T513	8		T895	1		T891	1
values[101]	99	1			T513	5		T895	1		T891	2
values[102]	84	1			T513	7		T895	1		T891	6
values[103]	63	1			T513	3		T895	1		T891	2
values[104]	80	1			T513	2		T895	1		T891	2
values[105]	85	1			T513	3		T895	1		T891	2
values[106]	86	1			T513	3		T895	1		T891	2
values[107]	98	1			T513	5		T895	1		T891	1
values[108]	98	1			T513	5		T895	2		T891	2
values[109]	92	1			T513	3		T895	1		T891	3
values[110]	121	1			T513	4		T895	1		T891	2
values[111]	101	1			T513	3		T895	1		T891	3
values[112]	106	1			T513	5		T895	1		T891	5
values[113]	108	1			T513	2		T895	1		T891	3
values[114]	95	1			T513	3		T895	1		T891	1
values[115]	100	1			T513	4		T895	1		T891	2
values[116]	130	1			T513	4		T895	1		T891	1
values[117]	121	1			T513	1		T895	1		T891	4
values[118]	104	1			T513	3		T895	1		T891	1
values[119]	102	1			T513	6		T895	2		T891	1
values[120]	104	1			T513	4		T895	10		T891	1
values[121]	125	1			T513	2		T895	2		T891	2
values[122]	139	1			T513	9		T895	1		T891	2
values[123]	149	1			T513	1		T895	1		T891	1
values[124]	246	1			T513	7		T895	3		T891	3
values[125]	486	1			T513	22		T895	2		T891	7
values[126]	912	1			T513	24		T895	26		T891	16
values[127]	2931	1			T513	18		T895	149		T891	112
values[128]	4613	1			T513	3		T895	259		T891	191