Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.32 95.56 94.49 95.31 95.42 97.53 99.60


Total tests in report: 2937
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
39.72 39.72 44.72 44.72 43.01 43.01 32.84 32.84 57.91 57.91 59.44 59.44 0.42 0.42 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2393260461
52.31 12.58 58.55 13.83 58.10 15.09 38.60 5.76 71.72 13.81 85.84 26.40 1.03 0.61 /workspace/coverage/default/0.chip_jtag_csr_rw.2318513320
57.84 5.53 63.40 4.85 62.57 4.46 43.17 4.57 71.95 0.23 85.84 0.00 20.13 19.09 /workspace/coverage/cover_reg_top/60.xbar_stress_all.3024160352
63.00 5.16 74.72 11.33 69.88 7.31 45.38 2.20 82.07 10.12 85.84 0.00 20.13 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_20.2839003448
67.23 4.23 74.72 0.00 69.88 0.00 45.38 0.00 82.07 0.00 85.84 0.00 45.48 25.36 /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.2088047217
70.41 3.19 79.85 5.12 73.86 3.98 49.03 3.65 83.89 1.82 90.38 4.55 45.48 0.00 /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2032961475
73.55 3.14 79.85 0.00 73.89 0.02 49.03 0.00 83.89 0.00 90.38 0.00 64.29 18.81 /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.158896083
76.32 2.77 79.85 0.00 73.89 0.00 65.62 16.60 83.89 0.00 90.38 0.00 64.29 0.00 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.870917969
78.77 2.45 79.85 0.00 74.05 0.16 65.62 0.00 83.89 0.00 90.38 0.00 78.85 14.56 /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.2998930296
81.02 2.25 82.24 2.39 76.63 2.58 71.76 6.14 85.91 2.03 90.73 0.35 78.85 0.00 /workspace/coverage/default/1.rom_e2e_asm_init_dev.2282711636
82.65 1.63 84.90 2.66 77.99 1.36 75.57 3.81 86.81 0.89 91.78 1.05 78.85 0.00 /workspace/coverage/default/1.chip_sw_power_virus.3632697899
84.01 1.36 86.63 1.73 81.90 3.91 75.98 0.41 87.71 0.90 91.78 0.00 80.06 1.21 /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.503923007
85.16 1.15 88.74 2.11 83.90 2.01 76.45 0.47 90.00 2.29 91.78 0.00 80.06 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_0.1133624739
86.28 1.12 88.74 0.00 83.90 0.00 76.45 0.00 90.00 0.00 91.78 0.00 86.79 6.73 /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.1454889265
87.37 1.09 88.83 0.08 83.91 0.01 82.89 6.44 90.00 0.01 91.78 0.00 86.79 0.00 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2150048631
88.20 0.84 89.12 0.30 84.00 0.09 83.56 0.67 90.11 0.11 95.63 3.85 86.79 0.00 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3652852697
89.00 0.80 90.21 1.09 85.71 1.71 83.72 0.16 91.94 1.83 95.63 0.00 86.79 0.00 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2149420713
89.71 0.71 91.12 0.90 85.83 0.12 84.82 1.10 91.98 0.04 95.63 0.00 88.90 2.10 /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1056590102
90.33 0.62 91.12 0.00 85.85 0.02 84.82 0.00 91.98 0.00 95.63 0.00 92.60 3.70 /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2033475076
90.79 0.46 91.92 0.81 86.48 0.64 85.42 0.60 92.67 0.69 95.63 0.00 92.60 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_10.3630245891
91.23 0.44 92.47 0.55 86.98 0.49 85.87 0.44 93.24 0.57 96.15 0.52 92.64 0.05 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2487485889
91.59 0.36 92.49 0.02 87.01 0.04 86.33 0.47 93.24 0.00 96.15 0.00 94.30 1.66 /workspace/coverage/default/2.chip_sw_alert_test.284828618
91.95 0.36 92.50 0.01 87.02 0.01 88.49 2.16 93.24 0.00 96.15 0.00 94.30 0.00 /workspace/coverage/default/2.chip_sw_edn_auto_mode.2308237914
92.28 0.32 92.65 0.15 87.60 0.58 89.17 0.68 93.77 0.53 96.15 0.00 94.30 0.00 /workspace/coverage/default/2.chip_jtag_csr_rw.1774665741
92.56 0.28 93.41 0.75 87.97 0.37 89.31 0.13 94.01 0.24 96.33 0.17 94.31 0.01 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2367754156
92.81 0.25 93.41 0.01 89.42 1.44 89.31 0.00 94.01 0.00 96.33 0.00 94.36 0.05 /workspace/coverage/cover_reg_top/0.chip_tl_errors.3806298165
93.03 0.22 93.87 0.46 89.73 0.31 89.66 0.35 94.23 0.22 96.33 0.00 94.36 0.00 /workspace/coverage/default/1.chip_sw_gpio.751073732
93.25 0.22 93.87 0.00 89.74 0.02 89.66 0.00 94.23 0.00 96.33 0.00 95.65 1.29 /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.1841198370
93.46 0.22 93.87 0.00 89.74 0.00 90.79 1.13 94.23 0.00 96.50 0.17 95.65 0.00 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.27074321
93.64 0.18 93.87 0.00 89.89 0.14 90.79 0.00 94.25 0.02 96.50 0.00 96.56 0.90 /workspace/coverage/cover_reg_top/44.xbar_stress_all.2987519390
93.81 0.17 93.87 0.00 89.89 0.00 90.79 0.00 94.25 0.00 96.50 0.00 97.56 1.00 /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.4075006599
93.96 0.15 94.08 0.21 90.21 0.32 91.14 0.36 94.25 0.00 96.50 0.00 97.56 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4087412075
94.09 0.13 94.11 0.03 90.55 0.34 91.25 0.11 94.56 0.32 96.50 0.00 97.56 0.00 /workspace/coverage/default/1.chip_jtag_csr_rw.3662804781
94.21 0.12 94.11 0.00 91.26 0.71 91.25 0.00 94.56 0.00 96.50 0.00 97.56 0.00 /workspace/coverage/cover_reg_top/5.chip_tl_errors.3586395050
94.32 0.12 94.16 0.05 91.90 0.64 91.26 0.01 94.56 0.00 96.50 0.00 97.56 0.00 /workspace/coverage/cover_reg_top/14.chip_csr_rw.3223480090
94.44 0.11 94.16 0.00 91.90 0.00 91.91 0.65 94.56 0.00 96.50 0.00 97.59 0.04 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2991680250
94.53 0.09 94.22 0.06 91.93 0.03 92.16 0.25 94.58 0.02 96.68 0.17 97.60 0.01 /workspace/coverage/default/14.chip_sw_all_escalation_resets.2068729947
94.61 0.08 94.23 0.01 92.13 0.20 92.20 0.04 94.81 0.23 96.68 0.00 97.60 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.4031509911
94.69 0.08 94.24 0.01 92.15 0.02 92.47 0.27 94.81 0.00 96.85 0.17 97.60 0.00 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3801196425
94.76 0.08 94.24 0.00 92.15 0.00 92.93 0.45 94.81 0.00 96.85 0.00 97.60 0.00 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2208172071
94.83 0.07 94.33 0.09 92.20 0.06 93.11 0.18 94.86 0.06 96.85 0.00 97.61 0.01 /workspace/coverage/default/98.chip_sw_all_escalation_resets.235486137
94.89 0.06 94.33 0.00 92.24 0.04 93.11 0.00 94.88 0.02 96.85 0.00 97.91 0.29 /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.2805632878
94.93 0.05 94.35 0.03 92.26 0.02 93.14 0.03 94.90 0.02 97.03 0.17 97.92 0.01 /workspace/coverage/default/19.chip_sw_all_escalation_resets.1005815671
94.98 0.05 94.35 0.00 92.26 0.00 93.14 0.00 94.90 0.00 97.03 0.00 98.20 0.28 /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.2032354955
95.03 0.05 94.35 0.00 92.39 0.13 93.14 0.00 95.04 0.15 97.03 0.00 98.20 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3837566601
95.07 0.04 94.37 0.02 92.51 0.11 93.27 0.13 95.05 0.01 97.03 0.00 98.20 0.00 /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3511476623
95.11 0.04 94.37 0.00 92.75 0.25 93.27 0.00 95.05 0.00 97.03 0.00 98.20 0.00 /workspace/coverage/cover_reg_top/10.chip_tl_errors.880224726
95.15 0.04 94.38 0.01 92.77 0.01 93.27 0.00 95.08 0.02 97.20 0.17 98.21 0.01 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1026427065
95.19 0.04 94.38 0.00 92.77 0.00 93.50 0.22 95.08 0.00 97.20 0.00 98.21 0.00 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3635041275
95.23 0.04 94.49 0.11 92.79 0.02 93.59 0.09 95.08 0.00 97.20 0.00 98.21 0.00 /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.2227648957
95.26 0.04 94.49 0.00 92.80 0.01 93.78 0.19 95.08 0.00 97.20 0.00 98.23 0.01 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2038515660
95.30 0.04 94.50 0.01 92.81 0.01 93.79 0.01 95.08 0.01 97.38 0.17 98.24 0.01 /workspace/coverage/default/25.chip_sw_all_escalation_resets.701432418
95.33 0.04 94.50 0.00 92.81 0.00 94.00 0.22 95.08 0.00 97.38 0.00 98.24 0.00 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.724427300
95.37 0.04 94.50 0.00 92.81 0.00 94.04 0.04 95.08 0.00 97.55 0.17 98.24 0.00 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.2192290657
95.41 0.03 94.55 0.05 92.91 0.10 94.08 0.04 95.10 0.02 97.55 0.00 98.24 0.00 /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.329564830
95.44 0.03 94.55 0.00 92.97 0.05 94.08 0.00 95.12 0.02 97.55 0.00 98.37 0.13 /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.2159251065
95.47 0.03 94.55 0.00 93.08 0.11 94.08 0.00 95.15 0.03 97.55 0.00 98.40 0.04 /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.830443549
95.50 0.03 94.62 0.07 93.08 0.00 94.18 0.10 95.16 0.01 97.55 0.00 98.40 0.00 /workspace/coverage/default/1.chip_tap_straps_rma.415775857
95.53 0.03 94.62 0.01 93.11 0.03 94.31 0.13 95.16 0.00 97.55 0.00 98.40 0.00 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2901810899
95.55 0.03 94.69 0.07 93.14 0.03 94.32 0.01 95.20 0.05 97.55 0.00 98.40 0.00 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1385181846
95.58 0.03 94.73 0.04 93.22 0.08 94.32 0.00 95.24 0.03 97.55 0.00 98.40 0.00 /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2802288521
95.60 0.03 94.77 0.03 93.23 0.01 94.42 0.09 95.24 0.00 97.55 0.00 98.41 0.01 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2520112422
95.62 0.02 94.77 0.00 93.34 0.10 94.42 0.00 95.24 0.00 97.55 0.00 98.41 0.00 /workspace/coverage/cover_reg_top/11.chip_tl_errors.1674334875
95.64 0.02 94.77 0.00 93.44 0.10 94.42 0.00 95.24 0.00 97.55 0.00 98.41 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_0.1944241502
95.65 0.02 94.77 0.00 93.46 0.02 94.42 0.00 95.24 0.00 97.55 0.00 98.50 0.08 /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.658764194
95.67 0.02 94.78 0.01 93.50 0.04 94.43 0.01 95.26 0.02 97.55 0.00 98.50 0.00 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2780433281
95.68 0.01 94.78 0.00 93.50 0.00 94.52 0.09 95.26 0.00 97.55 0.00 98.50 0.00 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1270071456
95.70 0.01 94.78 0.00 93.50 0.01 94.52 0.00 95.26 0.00 97.55 0.00 98.58 0.08 /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1242337085
95.71 0.01 94.78 0.00 93.50 0.00 94.61 0.09 95.26 0.00 97.55 0.00 98.58 0.00 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2877866663
95.73 0.01 94.79 0.01 93.52 0.02 94.64 0.04 95.28 0.02 97.55 0.00 98.58 0.00 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1162485467
95.74 0.01 94.79 0.00 93.52 0.00 94.72 0.08 95.28 0.00 97.55 0.00 98.58 0.00 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2494113294
95.75 0.01 94.79 0.00 93.59 0.07 94.72 0.00 95.28 0.00 97.55 0.00 98.58 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_20.3687878259
95.76 0.01 94.79 0.01 93.64 0.05 94.72 0.00 95.29 0.02 97.55 0.00 98.58 0.00 /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.4165698980
95.78 0.01 94.80 0.01 93.68 0.04 94.72 0.01 95.32 0.02 97.55 0.00 98.58 0.00 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.267303986
95.79 0.01 94.80 0.00 93.73 0.05 94.72 0.00 95.33 0.02 97.55 0.00 98.58 0.00 /workspace/coverage/cover_reg_top/7.xbar_stress_all.549321968
95.80 0.01 94.80 0.00 93.73 0.00 94.79 0.07 95.33 0.00 97.55 0.00 98.58 0.00 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2124097802
95.81 0.01 94.80 0.00 93.80 0.07 94.79 0.00 95.33 0.00 97.55 0.00 98.58 0.00 /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.1442502678
95.82 0.01 94.81 0.01 93.80 0.01 94.84 0.05 95.33 0.00 97.55 0.00 98.58 0.00 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2146485448
95.83 0.01 94.84 0.02 93.81 0.01 94.86 0.02 95.35 0.02 97.55 0.00 98.58 0.00 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1237005321
95.84 0.01 94.87 0.03 93.83 0.02 94.86 0.00 95.36 0.01 97.55 0.00 98.58 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.522252059
95.85 0.01 94.91 0.03 93.85 0.02 94.86 0.00 95.37 0.01 97.55 0.00 98.58 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.2523095928
95.86 0.01 94.91 0.00 93.92 0.06 94.86 0.00 95.37 0.00 97.55 0.00 98.58 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_0.1802024148
95.87 0.01 94.91 0.00 93.95 0.04 94.86 0.00 95.39 0.02 97.55 0.00 98.58 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1241828788
95.88 0.01 94.93 0.02 93.96 0.01 94.87 0.01 95.41 0.02 97.55 0.00 98.58 0.00 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1904046494
95.89 0.01 94.93 0.00 94.01 0.05 94.87 0.00 95.41 0.00 97.55 0.00 98.58 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_20.2989055303
95.90 0.01 94.93 0.00 94.02 0.01 94.91 0.05 95.41 0.00 97.55 0.00 98.58 0.00 /workspace/coverage/default/0.rom_e2e_shutdown_output.2289508422
95.91 0.01 94.95 0.02 94.02 0.00 94.93 0.02 95.41 0.00 97.55 0.00 98.59 0.01 /workspace/coverage/default/94.chip_sw_all_escalation_resets.108144020
95.92 0.01 94.95 0.00 94.05 0.04 94.93 0.00 95.41 0.00 97.55 0.00 98.60 0.01 /workspace/coverage/cover_reg_top/13.chip_tl_errors.511423837
95.92 0.01 94.95 0.00 94.05 0.00 94.93 0.00 95.41 0.00 97.55 0.00 98.65 0.05 /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.1551579999
95.93 0.01 94.95 0.00 94.08 0.02 94.95 0.02 95.41 0.00 97.55 0.00 98.65 0.00 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.108167210
95.94 0.01 94.95 0.00 94.08 0.00 95.00 0.04 95.41 0.00 97.55 0.00 98.65 0.00 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3570067225
95.95 0.01 94.95 0.00 94.11 0.03 95.00 0.00 95.41 0.00 97.55 0.00 98.66 0.01 /workspace/coverage/cover_reg_top/2.chip_tl_errors.3130697488
95.95 0.01 94.95 0.00 94.14 0.04 95.00 0.00 95.41 0.00 97.55 0.00 98.66 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_10.950211063
95.96 0.01 94.95 0.00 94.14 0.00 95.00 0.00 95.41 0.00 97.55 0.00 98.70 0.04 /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3438251370
95.96 0.01 94.95 0.01 94.16 0.02 95.01 0.01 95.41 0.00 97.55 0.00 98.70 0.00 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3172674027
95.97 0.01 94.95 0.00 94.16 0.00 95.04 0.03 95.41 0.00 97.55 0.00 98.70 0.00 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2136401841
95.97 0.01 94.95 0.00 94.17 0.01 95.04 0.00 95.41 0.00 97.55 0.00 98.72 0.02 /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1702932530
95.98 0.01 94.96 0.01 94.17 0.01 95.06 0.02 95.41 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3866529626
95.98 0.01 94.96 0.00 94.17 0.00 95.09 0.03 95.41 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.4154372606
95.99 0.01 94.96 0.00 94.20 0.02 95.09 0.00 95.41 0.00 97.55 0.00 98.72 0.00 /workspace/coverage/cover_reg_top/25.xbar_stress_all.2952571568
95.99 0.01 94.96 0.00 94.20 0.00 95.09 0.00 95.41 0.00 97.55 0.00 98.74 0.02 /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.1895848725
95.99 0.01 94.96 0.00 94.20 0.00 95.09 0.00 95.41 0.00 97.55 0.00 98.77 0.02 /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2933871149
96.00 0.01 94.96 0.01 94.21 0.01 95.09 0.01 95.41 0.00 97.55 0.00 98.77 0.00 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3934547437
96.00 0.01 94.96 0.00 94.23 0.02 95.09 0.00 95.41 0.00 97.55 0.00 98.77 0.00 /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1760910849
96.01 0.01 94.96 0.00 94.24 0.01 95.09 0.01 95.41 0.00 97.55 0.00 98.78 0.01 /workspace/coverage/default/27.chip_sw_all_escalation_resets.1039535365
96.01 0.01 94.96 0.00 94.24 0.01 95.09 0.00 95.41 0.00 97.55 0.00 98.79 0.01 /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.248560470
96.01 0.01 94.96 0.00 94.24 0.00 95.11 0.02 95.41 0.00 97.55 0.00 98.79 0.00 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2427458531
96.01 0.01 94.96 0.00 94.24 0.00 95.13 0.02 95.41 0.00 97.55 0.00 98.79 0.00 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2270233926
96.02 0.01 94.96 0.00 94.24 0.00 95.15 0.02 95.41 0.00 97.55 0.00 98.79 0.00 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3935505062
96.02 0.01 94.96 0.00 94.26 0.02 95.15 0.00 95.41 0.00 97.55 0.00 98.79 0.00 /workspace/coverage/cover_reg_top/28.xbar_stress_all.4281598158
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96.22 0.01 94.98 0.00 94.45 0.01 95.29 0.00 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.508946631
96.22 0.01 94.98 0.00 94.46 0.01 95.29 0.00 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.1547255879
96.22 0.01 94.98 0.00 94.46 0.01 95.29 0.00 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.1151158734
96.22 0.01 94.98 0.00 94.46 0.01 95.29 0.00 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.1732116132
96.22 0.01 94.98 0.00 94.47 0.01 95.29 0.00 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.3806271647
96.22 0.01 94.98 0.00 94.47 0.01 95.29 0.00 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.3822785891
96.22 0.01 94.98 0.00 94.47 0.01 95.29 0.00 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/default/0.chip_sw_gpio.4135355908
96.22 0.01 94.98 0.00 94.48 0.01 95.29 0.00 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3963179694
96.22 0.01 94.98 0.00 94.48 0.01 95.29 0.00 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3721282556
96.22 0.01 94.98 0.00 94.48 0.01 95.29 0.00 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2324020061
96.22 0.01 94.98 0.00 94.49 0.01 95.29 0.00 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.947337927
96.22 0.01 94.98 0.00 94.49 0.00 95.30 0.01 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/default/0.chip_tap_straps_rma.1185521710
96.22 0.01 94.99 0.01 94.49 0.00 95.30 0.00 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1886996117
96.22 0.01 94.99 0.00 94.49 0.00 95.30 0.01 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2781869723
96.22 0.01 94.99 0.00 94.49 0.00 95.30 0.01 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/default/0.chip_sw_aon_timer_irq.4232219440
96.23 0.01 94.99 0.00 94.49 0.00 95.30 0.01 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1657550311
96.23 0.01 94.99 0.00 94.49 0.00 95.31 0.01 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/default/0.chip_sw_edn_boot_mode.2319127826
96.23 0.01 94.99 0.00 94.49 0.00 95.31 0.01 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.389338827
96.23 0.01 94.99 0.00 94.49 0.00 95.31 0.01 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.660419163
96.23 0.01 94.99 0.00 94.49 0.00 95.31 0.01 95.42 0.00 97.55 0.00 99.60 0.00 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2492579099

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3184901867
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3022712596
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.780404336
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1113530733
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1264387817
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.326505389
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3363436975
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.137919569
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.187168801
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.4250892132
/workspace/coverage/cover_reg_top/0.xbar_error_random.2007841796
/workspace/coverage/cover_reg_top/0.xbar_random.3198439556
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1215495405
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3154180801
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2968695496
/workspace/coverage/cover_reg_top/0.xbar_same_source.2004927416
/workspace/coverage/cover_reg_top/0.xbar_smoke.244284314
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1522130668
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2401475370
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.909050448
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3382604131
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3489483506
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3378454785
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2601855613
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.331682976
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.314462001
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1355488549
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.390965021
/workspace/coverage/cover_reg_top/1.chip_csr_rw.710135226
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2673270539
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2479178560
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1478519544
/workspace/coverage/cover_reg_top/1.chip_tl_errors.2951767058
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1958287953
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2187839030
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2976447275
/workspace/coverage/cover_reg_top/1.xbar_error_random.1113972105
/workspace/coverage/cover_reg_top/1.xbar_random.3533755307
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.510215721
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.760089575
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3818667240
/workspace/coverage/cover_reg_top/1.xbar_same_source.446730586
/workspace/coverage/cover_reg_top/1.xbar_smoke.1162524716
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.539250959
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1093118347
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.4263758372
/workspace/coverage/cover_reg_top/1.xbar_stress_all.221955725
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.76905126
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.973822245
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1258604151
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3164010256
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3847816227
/workspace/coverage/cover_reg_top/10.chip_csr_rw.4163528098
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1735094067
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.2052522620
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3988753890
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.106269780
/workspace/coverage/cover_reg_top/10.xbar_error_random.2664989230
/workspace/coverage/cover_reg_top/10.xbar_random.3137087885
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1064510730
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3411613539
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.4266168716
/workspace/coverage/cover_reg_top/10.xbar_same_source.2737796376
/workspace/coverage/cover_reg_top/10.xbar_smoke.2368412391
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2596048561
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1705171426
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.15757202
/workspace/coverage/cover_reg_top/10.xbar_stress_all.3683448702
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.65687988
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3664447875
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.2567377118
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3455166331
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1401227054
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.3250868019
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3017988964
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.49795
/workspace/coverage/cover_reg_top/11.xbar_error_random.1679249492
/workspace/coverage/cover_reg_top/11.xbar_random.3829709901
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.2514237782
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2096251165
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3556689051
/workspace/coverage/cover_reg_top/11.xbar_same_source.3154978365
/workspace/coverage/cover_reg_top/11.xbar_smoke.2113512960
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1562023656
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.756833775
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2662668927
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3905134468
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3134269267
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.4022738325
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2202396511
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.4170481668
/workspace/coverage/cover_reg_top/12.chip_csr_rw.3885755457
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1636320059
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2353213589
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3771153570
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.421452969
/workspace/coverage/cover_reg_top/12.xbar_error_random.3231894686
/workspace/coverage/cover_reg_top/12.xbar_random.1016738509
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1291015984
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.499783595
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1087368216
/workspace/coverage/cover_reg_top/12.xbar_same_source.1731032804
/workspace/coverage/cover_reg_top/12.xbar_smoke.2864544075
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.209441767
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2825957978
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.471595073
/workspace/coverage/cover_reg_top/12.xbar_stress_all.2366675220
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3942449079
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.4003310983
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1033482061
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.4265516085
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3887430061
/workspace/coverage/cover_reg_top/13.chip_csr_rw.465171059
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2933312259
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2879984442
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2834067547
/workspace/coverage/cover_reg_top/13.xbar_error_random.2977373388
/workspace/coverage/cover_reg_top/13.xbar_random.2964728813
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3755238199
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3167064616
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3364512054
/workspace/coverage/cover_reg_top/13.xbar_same_source.950628507
/workspace/coverage/cover_reg_top/13.xbar_smoke.3293720214
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3367437265
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3049068089
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.644589752
/workspace/coverage/cover_reg_top/13.xbar_stress_all.2705013366
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2218689031
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2047047820
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2842134932
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2811259563
/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.1624003419
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.298444336
/workspace/coverage/cover_reg_top/14.chip_tl_errors.1220906388
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.2840976050
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.990834814
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.39177289
/workspace/coverage/cover_reg_top/14.xbar_error_random.1930006716
/workspace/coverage/cover_reg_top/14.xbar_random.713319525
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2539765265
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.379196178
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3440451568
/workspace/coverage/cover_reg_top/14.xbar_same_source.542046769
/workspace/coverage/cover_reg_top/14.xbar_smoke.3984652552
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.2023857042
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2656657032
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.645377882
/workspace/coverage/cover_reg_top/14.xbar_stress_all.2337567860
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.3181373811
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2339964796
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1861130352
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.82852082
/workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.4030741814
/workspace/coverage/cover_reg_top/15.chip_csr_rw.2870391090
/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.909159694
/workspace/coverage/cover_reg_top/15.chip_tl_errors.534554732
/workspace/coverage/cover_reg_top/15.xbar_access_same_device.2505110738
/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.1912862485
/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2275781867
/workspace/coverage/cover_reg_top/15.xbar_error_random.77075329
/workspace/coverage/cover_reg_top/15.xbar_random.849399871
/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.4261884292
/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.1920246054
/workspace/coverage/cover_reg_top/15.xbar_same_source.4216283146
/workspace/coverage/cover_reg_top/15.xbar_smoke.681456662
/workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.2612990292
/workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.180411055
/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.38792013
/workspace/coverage/cover_reg_top/15.xbar_stress_all.469744951
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3434043070
/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.2537841544
/workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.480590514
/workspace/coverage/cover_reg_top/16.chip_csr_rw.816045434
/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.2562376108
/workspace/coverage/cover_reg_top/16.chip_tl_errors.1170490950
/workspace/coverage/cover_reg_top/16.xbar_access_same_device.2401025286
/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3888144153
/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3820245953
/workspace/coverage/cover_reg_top/16.xbar_error_random.1004846221
/workspace/coverage/cover_reg_top/16.xbar_random.1817993403
/workspace/coverage/cover_reg_top/16.xbar_random_large_delays.1407825750
/workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.3677874895
/workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.1955753809
/workspace/coverage/cover_reg_top/16.xbar_same_source.3427472573
/workspace/coverage/cover_reg_top/16.xbar_smoke.27305364
/workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.1796280180
/workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1509659226
/workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.4037973087
/workspace/coverage/cover_reg_top/16.xbar_stress_all.3993030070
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.2067108349
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2849898878
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.138908730
/workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.464786838
/workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.3171558679
/workspace/coverage/cover_reg_top/17.chip_csr_rw.189934367
/workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.3262548935
/workspace/coverage/cover_reg_top/17.chip_tl_errors.3272073110
/workspace/coverage/cover_reg_top/17.xbar_access_same_device.656329753
/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.711585037
/workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2938567617
/workspace/coverage/cover_reg_top/17.xbar_error_random.2891276141
/workspace/coverage/cover_reg_top/17.xbar_random.3954100127
/workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.37810828
/workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.1576666294
/workspace/coverage/cover_reg_top/17.xbar_same_source.1925441132
/workspace/coverage/cover_reg_top/17.xbar_smoke.405014993
/workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.3703010435
/workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2932212423
/workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.2061350495
/workspace/coverage/cover_reg_top/17.xbar_stress_all.1169301498
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.1313030681
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1743906601
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.4119924935
/workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.3801207547
/workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.2777225583
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/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2806968137
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.298732355
/workspace/coverage/default/3.chip_tap_straps_dev.3613704713
/workspace/coverage/default/3.chip_tap_straps_prod.4121046815
/workspace/coverage/default/3.chip_tap_straps_rma.278703259
/workspace/coverage/default/3.chip_tap_straps_testunlock0.135365742
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3197137502
/workspace/coverage/default/33.chip_sw_all_escalation_resets.4095192267
/workspace/coverage/default/35.chip_sw_all_escalation_resets.3139104192
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1989461091
/workspace/coverage/default/36.chip_sw_all_escalation_resets.354613073
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2775194431
/workspace/coverage/default/37.chip_sw_all_escalation_resets.2491140638
/workspace/coverage/default/38.chip_sw_all_escalation_resets.2011161095
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1506033254
/workspace/coverage/default/4.chip_sw_all_escalation_resets.3527916585
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2194130999
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3083913176
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.943890959
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2496839025
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1393382262
/workspace/coverage/default/4.chip_sw_uart_tx_rx.299902556
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.4198336730
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2457513776
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3718922972
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1300745096
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1881702963
/workspace/coverage/default/4.chip_tap_straps_dev.1014519503
/workspace/coverage/default/4.chip_tap_straps_prod.346367988
/workspace/coverage/default/4.chip_tap_straps_rma.743997245
/workspace/coverage/default/4.chip_tap_straps_testunlock0.3700733728
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1419153141
/workspace/coverage/default/42.chip_sw_all_escalation_resets.1440978205
/workspace/coverage/default/43.chip_sw_all_escalation_resets.2986138140
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3203481059
/workspace/coverage/default/44.chip_sw_all_escalation_resets.725504232
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3446930269
/workspace/coverage/default/45.chip_sw_all_escalation_resets.2472384172
/workspace/coverage/default/46.chip_sw_all_escalation_resets.3287966180
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2212615231
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2340208427
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1411078460
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2070200580
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1324655850
/workspace/coverage/default/49.chip_sw_all_escalation_resets.3829088444
/workspace/coverage/default/5.chip_sw_all_escalation_resets.1259534803
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.701676974
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2891909806
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3329396994
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1785108219
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1021411051
/workspace/coverage/default/50.chip_sw_all_escalation_resets.2293329175
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.13358023
/workspace/coverage/default/51.chip_sw_all_escalation_resets.3779872559
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1977546216
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1782818193
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2905444848
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3154580429
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2448413037
/workspace/coverage/default/56.chip_sw_all_escalation_resets.48351738
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2933884959
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3786338385
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1942823015
/workspace/coverage/default/58.chip_sw_all_escalation_resets.258014776
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3858772983
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2583175808
/workspace/coverage/default/6.chip_sw_all_escalation_resets.3466379947
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.4011508076
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1012487765
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2905443392
/workspace/coverage/default/60.chip_sw_all_escalation_resets.944615073
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1675920301
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3166564398
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.704262671
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1077266231
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2011292718
/workspace/coverage/default/64.chip_sw_all_escalation_resets.904557537
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.637099778
/workspace/coverage/default/65.chip_sw_all_escalation_resets.1245644746
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1899647513
/workspace/coverage/default/66.chip_sw_all_escalation_resets.1781500923
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.769417340
/workspace/coverage/default/68.chip_sw_all_escalation_resets.3555404310
/workspace/coverage/default/69.chip_sw_all_escalation_resets.928042782
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.4023501964
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2122644452
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2881454182
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2909611874
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3846941602
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2934860372
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1314522045
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3163343780
/workspace/coverage/default/73.chip_sw_all_escalation_resets.3985108114
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3396589493
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3666923042
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3543118053
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2006675754
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3792366269
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1429440783
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1071726761
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3879354717
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.4191206821
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.749125527
/workspace/coverage/default/8.chip_sw_all_escalation_resets.1930382624
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3316303101
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2769116411
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1602570660
/workspace/coverage/default/80.chip_sw_all_escalation_resets.654227030
/workspace/coverage/default/81.chip_sw_all_escalation_resets.1642064016
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1242970092
/workspace/coverage/default/82.chip_sw_all_escalation_resets.834151314
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3048255071
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3406728301
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3751795800
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2213833557
/workspace/coverage/default/85.chip_sw_all_escalation_resets.1413517932
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1329877854
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3747124431
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3196641010
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.831573694
/workspace/coverage/default/9.chip_sw_all_escalation_resets.257441676
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1129281444
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.596051054
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1638484547
/workspace/coverage/default/90.chip_sw_all_escalation_resets.157552484
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2804920333
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3288059589
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3226146695
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3885765172
/workspace/coverage/default/96.chip_sw_all_escalation_resets.58893641
/workspace/coverage/default/97.chip_sw_all_escalation_resets.2341735757
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1469992269
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1361299678
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3687778866
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2750230462
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2473627151
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.736304152
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3994187970
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.921444536



Total test records in report: 2937
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html | tests62.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/2.chip_sw_kmac_app_rom.2249255282 Aug 15 07:24:08 PM PDT 24 Aug 15 07:27:26 PM PDT 24 3217791144 ps
T2 /workspace/coverage/default/54.chip_sw_all_escalation_resets.2905444848 Aug 15 07:36:56 PM PDT 24 Aug 15 07:45:55 PM PDT 24 3977819512 ps
T3 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3866529626 Aug 15 07:05:49 PM PDT 24 Aug 15 07:16:24 PM PDT 24 5921012912 ps
T4 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.3652911414 Aug 15 07:09:05 PM PDT 24 Aug 15 07:35:08 PM PDT 24 6035811336 ps
T5 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2393260461 Aug 15 07:04:45 PM PDT 24 Aug 15 07:13:00 PM PDT 24 6296013834 ps
T90 /workspace/coverage/default/2.chip_sw_aes_smoketest.1054904352 Aug 15 07:28:46 PM PDT 24 Aug 15 07:32:56 PM PDT 24 2445102958 ps
T91 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2146485448 Aug 15 07:05:05 PM PDT 24 Aug 15 07:14:35 PM PDT 24 4132273400 ps
T6 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2021232136 Aug 15 07:31:37 PM PDT 24 Aug 15 07:40:31 PM PDT 24 7425429281 ps
T15 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2901810899 Aug 15 07:31:39 PM PDT 24 Aug 15 07:42:14 PM PDT 24 4883837518 ps
T92 /workspace/coverage/default/2.chip_sw_power_idle_load.1938490392 Aug 15 07:26:36 PM PDT 24 Aug 15 07:39:15 PM PDT 24 4264234504 ps
T47 /workspace/coverage/default/1.rom_e2e_asm_init_dev.2282711636 Aug 15 07:21:16 PM PDT 24 Aug 15 08:22:51 PM PDT 24 15224963304 ps
T255 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1821726389 Aug 15 07:23:39 PM PDT 24 Aug 15 07:40:45 PM PDT 24 4975606776 ps
T357 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3455737293 Aug 15 07:23:22 PM PDT 24 Aug 15 07:31:35 PM PDT 24 4453866120 ps
T185 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3652852697 Aug 15 07:07:21 PM PDT 24 Aug 15 07:12:42 PM PDT 24 2840525540 ps
T128 /workspace/coverage/default/2.chip_sw_edn_auto_mode.2308237914 Aug 15 07:23:01 PM PDT 24 Aug 15 07:48:50 PM PDT 24 6715212376 ps
T68 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1419153141 Aug 15 07:35:29 PM PDT 24 Aug 15 07:40:47 PM PDT 24 3271597368 ps
T154 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3217647499 Aug 15 07:20:32 PM PDT 24 Aug 15 07:44:33 PM PDT 24 7645482504 ps
T129 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.279661083 Aug 15 07:16:10 PM PDT 24 Aug 15 07:21:20 PM PDT 24 2813562806 ps
T213 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3963179694 Aug 15 07:04:43 PM PDT 24 Aug 15 07:18:36 PM PDT 24 5437202858 ps
T149 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.108167210 Aug 15 07:31:10 PM PDT 24 Aug 15 07:54:47 PM PDT 24 8346437206 ps
T69 /workspace/coverage/default/98.chip_sw_all_escalation_resets.235486137 Aug 15 07:38:37 PM PDT 24 Aug 15 07:46:21 PM PDT 24 5661644308 ps
T155 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1088093124 Aug 15 07:20:14 PM PDT 24 Aug 15 07:23:56 PM PDT 24 3100022019 ps
T298 /workspace/coverage/default/2.chip_sw_hmac_smoketest.2747080071 Aug 15 07:28:23 PM PDT 24 Aug 15 07:36:11 PM PDT 24 3729857308 ps
T160 /workspace/coverage/default/87.chip_sw_all_escalation_resets.2830612024 Aug 15 07:38:19 PM PDT 24 Aug 15 07:46:45 PM PDT 24 5342229226 ps
T324 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1240715046 Aug 15 07:34:13 PM PDT 24 Aug 15 07:41:15 PM PDT 24 3788026650 ps
T304 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2367754156 Aug 15 07:37:19 PM PDT 24 Aug 15 07:43:14 PM PDT 24 3609421480 ps
T7 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1187849862 Aug 15 07:07:37 PM PDT 24 Aug 15 07:17:30 PM PDT 24 9173346315 ps
T8 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.27074321 Aug 15 07:09:16 PM PDT 24 Aug 15 07:20:14 PM PDT 24 5944938232 ps
T51 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.904064777 Aug 15 07:10:39 PM PDT 24 Aug 15 07:17:34 PM PDT 24 6270470588 ps
T309 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3571354800 Aug 15 07:34:24 PM PDT 24 Aug 15 07:41:12 PM PDT 24 3409905256 ps
T127 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.974039815 Aug 15 07:08:01 PM PDT 24 Aug 15 07:16:19 PM PDT 24 7488371936 ps
T115 /workspace/coverage/default/1.chip_sw_power_sleep_load.1713679775 Aug 15 07:17:03 PM PDT 24 Aug 15 07:26:27 PM PDT 24 10409726116 ps
T310 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.2282016205 Aug 15 07:08:22 PM PDT 24 Aug 15 07:12:49 PM PDT 24 2800578518 ps
T48 /workspace/coverage/default/0.rom_e2e_smoke.2255641211 Aug 15 07:12:36 PM PDT 24 Aug 15 08:26:58 PM PDT 24 15269367700 ps
T311 /workspace/coverage/default/1.chip_sw_edn_sw_mode.2053644346 Aug 15 07:11:00 PM PDT 24 Aug 15 07:29:57 PM PDT 24 6562340920 ps
T734 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.4085763114 Aug 15 07:06:23 PM PDT 24 Aug 15 07:14:11 PM PDT 24 3259131296 ps
T207 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1536573631 Aug 15 07:05:23 PM PDT 24 Aug 15 07:10:57 PM PDT 24 2961126178 ps
T132 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1237005321 Aug 15 07:35:25 PM PDT 24 Aug 15 07:43:27 PM PDT 24 6421899746 ps
T121 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3409596946 Aug 15 07:32:39 PM PDT 24 Aug 15 07:47:42 PM PDT 24 5681413720 ps
T246 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1441383758 Aug 15 07:26:14 PM PDT 24 Aug 15 07:36:43 PM PDT 24 4793568426 ps
T248 /workspace/coverage/default/14.chip_sw_all_escalation_resets.2068729947 Aug 15 07:31:59 PM PDT 24 Aug 15 07:43:06 PM PDT 24 5793557860 ps
T256 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.434623079 Aug 15 07:10:37 PM PDT 24 Aug 15 07:15:14 PM PDT 24 2434188060 ps
T49 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2885951663 Aug 15 07:06:39 PM PDT 24 Aug 15 07:14:40 PM PDT 24 5411750339 ps
T292 /workspace/coverage/default/49.chip_sw_all_escalation_resets.3829088444 Aug 15 07:35:37 PM PDT 24 Aug 15 07:46:16 PM PDT 24 4911123464 ps
T50 /workspace/coverage/default/2.chip_jtag_csr_rw.1774665741 Aug 15 07:18:07 PM PDT 24 Aug 15 07:42:42 PM PDT 24 12112289429 ps
T293 /workspace/coverage/default/39.chip_sw_all_escalation_resets.4058139206 Aug 15 07:33:41 PM PDT 24 Aug 15 07:43:25 PM PDT 24 5582758632 ps
T294 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2520112422 Aug 15 07:22:52 PM PDT 24 Aug 15 07:36:28 PM PDT 24 15162354190 ps
T177 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.870917969 Aug 15 07:14:19 PM PDT 24 Aug 15 07:51:57 PM PDT 24 11067333160 ps
T16 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1423255464 Aug 15 07:21:02 PM PDT 24 Aug 15 07:27:57 PM PDT 24 4171168480 ps
T107 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1920723145 Aug 15 07:07:20 PM PDT 24 Aug 15 07:16:47 PM PDT 24 5847363720 ps
T73 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2877866663 Aug 15 07:21:44 PM PDT 24 Aug 15 10:06:29 PM PDT 24 58993938103 ps
T108 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.3422137662 Aug 15 07:12:07 PM PDT 24 Aug 15 07:39:36 PM PDT 24 8046662474 ps
T109 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3782177850 Aug 15 07:29:08 PM PDT 24 Aug 15 07:41:06 PM PDT 24 4175764524 ps
T110 /workspace/coverage/default/2.chip_plic_all_irqs_10.3630245891 Aug 15 07:25:43 PM PDT 24 Aug 15 07:36:18 PM PDT 24 4386406120 ps
T111 /workspace/coverage/default/41.chip_sw_all_escalation_resets.1268249598 Aug 15 07:33:40 PM PDT 24 Aug 15 07:42:40 PM PDT 24 4989071340 ps
T112 /workspace/coverage/default/2.rom_keymgr_functest.1307886585 Aug 15 07:27:13 PM PDT 24 Aug 15 07:36:49 PM PDT 24 4590830504 ps
T113 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.185577925 Aug 15 07:12:06 PM PDT 24 Aug 15 07:38:08 PM PDT 24 9260021368 ps
T114 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3620174747 Aug 15 07:07:32 PM PDT 24 Aug 15 07:20:23 PM PDT 24 7128266708 ps
T186 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2200472584 Aug 15 07:24:03 PM PDT 24 Aug 15 07:38:29 PM PDT 24 8316615082 ps
T124 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2156656572 Aug 15 07:14:59 PM PDT 24 Aug 15 07:34:41 PM PDT 24 12636653986 ps
T957 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1328449652 Aug 15 07:05:30 PM PDT 24 Aug 15 07:10:52 PM PDT 24 3080911648 ps
T44 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3386542757 Aug 15 07:12:42 PM PDT 24 Aug 15 08:06:12 PM PDT 24 11200160904 ps
T958 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.33894186 Aug 15 07:30:48 PM PDT 24 Aug 15 07:36:39 PM PDT 24 3187872876 ps
T411 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.866668964 Aug 15 07:17:09 PM PDT 24 Aug 15 07:21:22 PM PDT 24 2556684120 ps
T301 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3889416774 Aug 15 07:34:42 PM PDT 24 Aug 15 07:41:41 PM PDT 24 4111426654 ps
T718 /workspace/coverage/default/1.chip_sw_aes_masking_off.3661442011 Aug 15 07:10:20 PM PDT 24 Aug 15 07:13:43 PM PDT 24 3029878937 ps
T130 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3638344330 Aug 15 07:21:31 PM PDT 24 Aug 15 07:29:39 PM PDT 24 7130042398 ps
T959 /workspace/coverage/default/0.chip_sw_aes_entropy.2599012113 Aug 15 07:10:54 PM PDT 24 Aug 15 07:13:58 PM PDT 24 2201204752 ps
T369 /workspace/coverage/default/0.rom_e2e_self_hash.2240090215 Aug 15 07:12:55 PM PDT 24 Aug 15 08:45:42 PM PDT 24 26019529662 ps
T170 /workspace/coverage/default/0.chip_sival_flash_info_access.3368875076 Aug 15 07:06:24 PM PDT 24 Aug 15 07:11:22 PM PDT 24 3334640860 ps
T120 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4284938323 Aug 15 07:28:24 PM PDT 24 Aug 15 07:54:11 PM PDT 24 11374835486 ps
T343 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3704475551 Aug 15 07:11:40 PM PDT 24 Aug 15 07:21:20 PM PDT 24 4083908244 ps
T516 /workspace/coverage/default/37.chip_sw_all_escalation_resets.2491140638 Aug 15 07:34:50 PM PDT 24 Aug 15 07:45:30 PM PDT 24 4897227672 ps
T35 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.1939796193 Aug 15 07:20:16 PM PDT 24 Aug 15 07:25:38 PM PDT 24 3365736600 ps
T125 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2124097802 Aug 15 07:16:14 PM PDT 24 Aug 15 07:26:53 PM PDT 24 4127700268 ps
T122 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2215390737 Aug 15 07:06:39 PM PDT 24 Aug 15 07:21:06 PM PDT 24 4454239962 ps
T217 /workspace/coverage/default/19.chip_sw_all_escalation_resets.1005815671 Aug 15 07:33:43 PM PDT 24 Aug 15 07:45:31 PM PDT 24 6045644640 ps
T266 /workspace/coverage/default/1.chip_sw_kmac_smoketest.3435728943 Aug 15 07:18:51 PM PDT 24 Aug 15 07:24:46 PM PDT 24 3271781048 ps
T267 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.161143241 Aug 15 07:06:26 PM PDT 24 Aug 15 07:14:22 PM PDT 24 4095850188 ps
T167 /workspace/coverage/default/15.chip_sw_all_escalation_resets.4265047308 Aug 15 07:32:55 PM PDT 24 Aug 15 07:43:39 PM PDT 24 5323913080 ps
T268 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2792284816 Aug 15 07:07:23 PM PDT 24 Aug 15 07:10:55 PM PDT 24 2826432883 ps
T269 /workspace/coverage/default/27.chip_sw_all_escalation_resets.1039535365 Aug 15 07:33:02 PM PDT 24 Aug 15 07:42:48 PM PDT 24 5771226960 ps
T260 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.701676974 Aug 15 07:29:49 PM PDT 24 Aug 15 07:55:28 PM PDT 24 7869657992 ps
T126 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1645226466 Aug 15 07:24:10 PM PDT 24 Aug 15 07:34:49 PM PDT 24 4824458864 ps
T254 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3492388867 Aug 15 07:27:29 PM PDT 24 Aug 15 07:31:11 PM PDT 24 2962536856 ps
T216 /workspace/coverage/default/3.chip_sw_uart_tx_rx.3385292318 Aug 15 07:28:43 PM PDT 24 Aug 15 07:36:31 PM PDT 24 4128651684 ps
T412 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.706250774 Aug 15 07:32:27 PM PDT 24 Aug 15 07:38:46 PM PDT 24 3871224952 ps
T960 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1669311980 Aug 15 07:07:21 PM PDT 24 Aug 15 07:18:54 PM PDT 24 4943969880 ps
T764 /workspace/coverage/default/0.chip_sw_hmac_oneshot.1647117579 Aug 15 07:07:30 PM PDT 24 Aug 15 07:13:00 PM PDT 24 2665452352 ps
T18 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2487485889 Aug 15 07:08:51 PM PDT 24 Aug 15 07:15:50 PM PDT 24 7464893250 ps
T333 /workspace/coverage/default/1.chip_sw_otbn_randomness.1328924579 Aug 15 07:14:51 PM PDT 24 Aug 15 07:32:27 PM PDT 24 6101191460 ps
T346 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1797071730 Aug 15 07:28:10 PM PDT 24 Aug 15 07:40:22 PM PDT 24 5628349607 ps
T74 /workspace/coverage/default/3.chip_tap_straps_testunlock0.135365742 Aug 15 07:33:26 PM PDT 24 Aug 15 07:38:10 PM PDT 24 4527809429 ps
T370 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3334749985 Aug 15 07:10:43 PM PDT 24 Aug 15 08:00:58 PM PDT 24 14928465742 ps
T178 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3635041275 Aug 15 07:12:31 PM PDT 24 Aug 15 07:15:31 PM PDT 24 3264131291 ps
T17 /workspace/coverage/default/1.chip_sw_gpio_smoketest.2468479506 Aug 15 07:24:20 PM PDT 24 Aug 15 07:29:15 PM PDT 24 2602050344 ps
T52 /workspace/coverage/default/0.chip_jtag_csr_rw.2318513320 Aug 15 06:58:46 PM PDT 24 Aug 15 07:33:43 PM PDT 24 19861698240 ps
T53 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.967029300 Aug 15 07:09:41 PM PDT 24 Aug 15 07:19:29 PM PDT 24 5274986296 ps
T408 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2633805438 Aug 15 07:16:25 PM PDT 24 Aug 15 07:38:55 PM PDT 24 7744187541 ps
T384 /workspace/coverage/default/44.chip_sw_all_escalation_resets.725504232 Aug 15 07:35:21 PM PDT 24 Aug 15 07:43:08 PM PDT 24 5951753438 ps
T161 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1942823015 Aug 15 07:37:06 PM PDT 24 Aug 15 07:44:36 PM PDT 24 4547054622 ps
T89 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3784031436 Aug 15 07:04:32 PM PDT 24 Aug 15 10:15:35 PM PDT 24 64190131059 ps
T351 /workspace/coverage/default/75.chip_sw_all_escalation_resets.3543118053 Aug 15 07:39:59 PM PDT 24 Aug 15 07:48:54 PM PDT 24 5869198790 ps
T347 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2780433281 Aug 15 07:17:36 PM PDT 24 Aug 15 07:30:16 PM PDT 24 4765007711 ps
T341 /workspace/coverage/default/1.chip_sw_aon_timer_irq.3445360741 Aug 15 07:14:51 PM PDT 24 Aug 15 07:22:36 PM PDT 24 3886937480 ps
T218 /workspace/coverage/default/16.chip_sw_all_escalation_resets.3736054427 Aug 15 07:33:56 PM PDT 24 Aug 15 07:42:31 PM PDT 24 5047328824 ps
T220 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1642640820 Aug 15 07:23:40 PM PDT 24 Aug 15 07:45:06 PM PDT 24 7654208068 ps
T771 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2189628386 Aug 15 07:25:45 PM PDT 24 Aug 15 07:33:27 PM PDT 24 5456162098 ps
T961 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1600366291 Aug 15 07:23:08 PM PDT 24 Aug 15 07:30:01 PM PDT 24 6175481668 ps
T349 /workspace/coverage/default/35.chip_sw_all_escalation_resets.3139104192 Aug 15 07:34:22 PM PDT 24 Aug 15 07:43:17 PM PDT 24 5880463690 ps
T392 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3197137502 Aug 15 07:35:24 PM PDT 24 Aug 15 07:42:21 PM PDT 24 4267680754 ps
T242 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.2192290657 Aug 15 07:18:44 PM PDT 24 Aug 15 07:31:25 PM PDT 24 5838117450 ps
T274 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.249114656 Aug 15 07:05:47 PM PDT 24 Aug 15 07:14:44 PM PDT 24 3930893160 ps
T168 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2150048631 Aug 15 07:12:28 PM PDT 24 Aug 15 08:42:55 PM PDT 24 49674397577 ps
T275 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3858772983 Aug 15 07:35:57 PM PDT 24 Aug 15 07:42:15 PM PDT 24 4326456224 ps
T276 /workspace/coverage/default/2.chip_sw_aes_enc.614268552 Aug 15 07:22:12 PM PDT 24 Aug 15 07:28:02 PM PDT 24 3029000450 ps
T40 /workspace/coverage/default/1.chip_sw_spi_device_tpm.3433791294 Aug 15 07:12:45 PM PDT 24 Aug 15 07:17:54 PM PDT 24 3481877182 ps
T27 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1241828788 Aug 15 07:04:32 PM PDT 24 Aug 15 07:11:15 PM PDT 24 3446453440 ps
T277 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1982972854 Aug 15 07:13:06 PM PDT 24 Aug 15 07:27:20 PM PDT 24 9459978140 ps
T244 /workspace/coverage/default/9.chip_sw_all_escalation_resets.257441676 Aug 15 07:30:11 PM PDT 24 Aug 15 07:37:47 PM PDT 24 4989633864 ps
T175 /workspace/coverage/default/2.chip_sw_flash_init.4105278230 Aug 15 07:29:40 PM PDT 24 Aug 15 07:58:21 PM PDT 24 21218580760 ps
T962 /workspace/coverage/default/0.chip_sw_example_flash.2310474083 Aug 15 07:03:52 PM PDT 24 Aug 15 07:07:35 PM PDT 24 3017316576 ps
T261 /workspace/coverage/default/1.chip_sw_edn_boot_mode.2143030148 Aug 15 07:14:13 PM PDT 24 Aug 15 07:25:15 PM PDT 24 3053096152 ps
T133 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.423205167 Aug 15 07:24:05 PM PDT 24 Aug 15 07:35:13 PM PDT 24 6731567008 ps
T83 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3251223155 Aug 15 07:16:24 PM PDT 24 Aug 15 07:22:53 PM PDT 24 3890640280 ps
T153 /workspace/coverage/default/0.rom_raw_unlock.2284492540 Aug 15 07:12:38 PM PDT 24 Aug 15 07:17:40 PM PDT 24 5917622722 ps
T45 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2739667502 Aug 15 07:14:07 PM PDT 24 Aug 15 09:00:30 PM PDT 24 23049668280 ps
T302 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2286315561 Aug 15 07:13:15 PM PDT 24 Aug 15 07:35:09 PM PDT 24 8007378128 ps
T963 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1596806644 Aug 15 07:05:36 PM PDT 24 Aug 15 07:56:01 PM PDT 24 29992862204 ps
T964 /workspace/coverage/default/1.chip_sival_flash_info_access.2261887898 Aug 15 07:11:58 PM PDT 24 Aug 15 07:16:47 PM PDT 24 3573255720 ps
T720 /workspace/coverage/default/0.chip_sw_aes_masking_off.3960728695 Aug 15 07:08:29 PM PDT 24 Aug 15 07:12:51 PM PDT 24 2570726822 ps
T150 /workspace/coverage/default/1.chip_sw_otbn_smoketest.1167441736 Aug 15 07:18:12 PM PDT 24 Aug 15 07:44:24 PM PDT 24 7796865440 ps
T782 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2983310316 Aug 15 07:39:48 PM PDT 24 Aug 15 07:44:52 PM PDT 24 3671988440 ps
T316 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3785894505 Aug 15 07:21:22 PM PDT 24 Aug 15 07:32:16 PM PDT 24 4502016828 ps
T965 /workspace/coverage/default/0.chip_sw_example_manufacturer.262521290 Aug 15 07:03:58 PM PDT 24 Aug 15 07:07:15 PM PDT 24 2855457760 ps
T414 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1778129818 Aug 15 07:22:22 PM PDT 24 Aug 15 07:40:29 PM PDT 24 6383742984 ps
T399 /workspace/coverage/default/94.chip_sw_all_escalation_resets.108144020 Aug 15 07:40:27 PM PDT 24 Aug 15 07:52:11 PM PDT 24 6610115848 ps
T118 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1657550311 Aug 15 07:08:51 PM PDT 24 Aug 16 01:15:21 AM PDT 24 152219851770 ps
T844 /workspace/coverage/default/88.chip_sw_all_escalation_resets.1028817244 Aug 15 07:39:15 PM PDT 24 Aug 15 07:49:32 PM PDT 24 4979246172 ps
T328 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2806968137 Aug 15 07:29:13 PM PDT 24 Aug 15 07:39:35 PM PDT 24 4826277346 ps
T966 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3316303101 Aug 15 07:31:16 PM PDT 24 Aug 15 08:10:46 PM PDT 24 11456470066 ps
T967 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.4091638747 Aug 15 07:19:46 PM PDT 24 Aug 15 07:23:52 PM PDT 24 2441445740 ps
T358 /workspace/coverage/default/2.chip_sw_aon_timer_irq.2704852734 Aug 15 07:22:50 PM PDT 24 Aug 15 07:31:36 PM PDT 24 4785107728 ps
T968 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1518257014 Aug 15 07:20:58 PM PDT 24 Aug 15 07:27:09 PM PDT 24 4230428600 ps
T849 /workspace/coverage/default/59.chip_sw_all_escalation_resets.3676004321 Aug 15 07:35:05 PM PDT 24 Aug 15 07:43:09 PM PDT 24 4447601720 ps
T169 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3628067957 Aug 15 07:05:21 PM PDT 24 Aug 15 07:07:06 PM PDT 24 2466321903 ps
T969 /workspace/coverage/default/2.chip_sw_uart_smoketest.2427028576 Aug 15 07:32:31 PM PDT 24 Aug 15 07:38:05 PM PDT 24 3306690150 ps
T721 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3713623349 Aug 15 07:08:21 PM PDT 24 Aug 15 07:13:24 PM PDT 24 3565956728 ps
T312 /workspace/coverage/default/48.chip_sw_all_escalation_resets.2070200580 Aug 15 07:34:41 PM PDT 24 Aug 15 07:46:01 PM PDT 24 4977139808 ps
T46 /workspace/coverage/default/0.rom_e2e_shutdown_output.2289508422 Aug 15 07:17:03 PM PDT 24 Aug 15 08:19:34 PM PDT 24 26642745855 ps
T970 /workspace/coverage/default/0.chip_sw_edn_auto_mode.3873897949 Aug 15 07:08:50 PM PDT 24 Aug 15 07:39:06 PM PDT 24 6588780472 ps
T409 /workspace/coverage/default/29.chip_sw_all_escalation_resets.2326332108 Aug 15 07:33:11 PM PDT 24 Aug 15 07:45:45 PM PDT 24 6377047820 ps
T971 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3405492355 Aug 15 07:24:32 PM PDT 24 Aug 15 07:34:44 PM PDT 24 4854790846 ps
T783 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2775194431 Aug 15 07:35:45 PM PDT 24 Aug 15 07:42:40 PM PDT 24 3985376316 ps
T972 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.4177108897 Aug 15 07:11:21 PM PDT 24 Aug 15 07:17:20 PM PDT 24 2750257290 ps
T176 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2005492592 Aug 15 07:22:38 PM PDT 24 Aug 15 08:51:49 PM PDT 24 46357910192 ps
T229 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.677633843 Aug 15 07:16:08 PM PDT 24 Aug 15 07:49:49 PM PDT 24 19935108654 ps
T973 /workspace/coverage/default/2.chip_sw_example_flash.707849688 Aug 15 07:19:03 PM PDT 24 Aug 15 07:23:20 PM PDT 24 2157864156 ps
T410 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3992022565 Aug 15 07:16:32 PM PDT 24 Aug 15 07:22:45 PM PDT 24 3690286080 ps
T116 /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.2720889713 Aug 15 07:17:40 PM PDT 24 Aug 15 08:08:24 PM PDT 24 21367526663 ps
T303 /workspace/coverage/default/1.chip_plic_all_irqs_20.2839003448 Aug 15 07:14:40 PM PDT 24 Aug 15 07:26:52 PM PDT 24 5117693006 ps
T215 /workspace/coverage/default/2.chip_sw_pattgen_ios.2467245779 Aug 15 07:20:09 PM PDT 24 Aug 15 07:24:09 PM PDT 24 2600980070 ps
T974 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3266667781 Aug 15 07:20:45 PM PDT 24 Aug 15 07:39:45 PM PDT 24 10961872044 ps
T123 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1717583489 Aug 15 07:14:33 PM PDT 24 Aug 15 07:31:16 PM PDT 24 6543865762 ps
T975 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.719577585 Aug 15 07:28:22 PM PDT 24 Aug 15 07:47:07 PM PDT 24 6315926594 ps
T219 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2260686415 Aug 15 07:13:21 PM PDT 24 Aug 15 07:40:21 PM PDT 24 8375923332 ps
T221 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2596835383 Aug 15 07:14:50 PM PDT 24 Aug 15 07:39:08 PM PDT 24 6985509620 ps
T976 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.23475964 Aug 15 07:06:48 PM PDT 24 Aug 15 07:10:20 PM PDT 24 3022026961 ps
T131 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1484221441 Aug 15 07:15:05 PM PDT 24 Aug 15 07:26:37 PM PDT 24 5726515348 ps
T385 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.4191206821 Aug 15 07:39:19 PM PDT 24 Aug 15 07:45:47 PM PDT 24 3402086920 ps
T211 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3396589493 Aug 15 07:37:39 PM PDT 24 Aug 15 07:43:55 PM PDT 24 3987043050 ps
T375 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.430076869 Aug 15 07:23:06 PM PDT 24 Aug 15 08:16:44 PM PDT 24 15634609592 ps
T117 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2359740296 Aug 15 07:11:53 PM PDT 24 Aug 15 07:20:20 PM PDT 24 17756006000 ps
T376 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.13358023 Aug 15 07:36:08 PM PDT 24 Aug 15 07:44:09 PM PDT 24 3515787944 ps
T377 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2006675754 Aug 15 07:37:36 PM PDT 24 Aug 15 07:43:04 PM PDT 24 4089954008 ps
T70 /workspace/coverage/default/0.chip_tap_straps_testunlock0.1630883394 Aug 15 07:06:10 PM PDT 24 Aug 15 07:09:51 PM PDT 24 2590250808 ps
T270 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3780874235 Aug 15 07:12:39 PM PDT 24 Aug 15 08:21:44 PM PDT 24 14180191464 ps
T378 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3446930269 Aug 15 07:34:20 PM PDT 24 Aug 15 07:40:55 PM PDT 24 4521428016 ps
T119 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.4171093652 Aug 15 07:17:23 PM PDT 24 Aug 15 07:49:37 PM PDT 24 10078348148 ps
T379 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1638484547 Aug 15 07:31:37 PM PDT 24 Aug 15 07:56:35 PM PDT 24 8265484850 ps
T314 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2909096512 Aug 15 07:34:05 PM PDT 24 Aug 15 08:01:16 PM PDT 24 8238552025 ps
T222 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.718807711 Aug 15 07:23:46 PM PDT 24 Aug 15 07:42:55 PM PDT 24 6953179334 ps
T350 /workspace/coverage/default/7.chip_sw_all_escalation_resets.358975150 Aug 15 07:30:17 PM PDT 24 Aug 15 07:40:34 PM PDT 24 5331365416 ps
T722 /workspace/coverage/default/78.chip_sw_all_escalation_resets.3879354717 Aug 15 07:38:00 PM PDT 24 Aug 15 07:47:12 PM PDT 24 4974739336 ps
T88 /workspace/coverage/default/0.chip_sw_usbdev_vbus.115443106 Aug 15 07:06:23 PM PDT 24 Aug 15 07:10:09 PM PDT 24 3268362480 ps
T84 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2991680250 Aug 15 07:04:47 PM PDT 24 Aug 15 07:08:22 PM PDT 24 2945911850 ps
T144 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3164959109 Aug 15 07:18:41 PM PDT 24 Aug 15 07:25:24 PM PDT 24 5467378440 ps
T809 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.4160647627 Aug 15 07:34:12 PM PDT 24 Aug 15 07:39:21 PM PDT 24 3265987528 ps
T151 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3088838620 Aug 15 07:08:46 PM PDT 24 Aug 15 08:09:40 PM PDT 24 24383789611 ps
T182 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3801196425 Aug 15 07:24:31 PM PDT 24 Aug 15 07:34:54 PM PDT 24 4850892221 ps
T285 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2881454182 Aug 15 07:31:15 PM PDT 24 Aug 15 07:40:39 PM PDT 24 6023481915 ps
T286 /workspace/coverage/default/2.chip_sw_hmac_enc.1539521160 Aug 15 07:24:51 PM PDT 24 Aug 15 07:31:29 PM PDT 24 3246548680 ps
T287 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3452655293 Aug 15 07:10:38 PM PDT 24 Aug 15 07:15:34 PM PDT 24 2985703868 ps
T288 /workspace/coverage/default/70.chip_sw_all_escalation_resets.3846941602 Aug 15 07:35:59 PM PDT 24 Aug 15 07:43:47 PM PDT 24 5230974664 ps
T289 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3067175099 Aug 15 07:27:57 PM PDT 24 Aug 15 08:06:22 PM PDT 24 12575807658 ps
T290 /workspace/coverage/default/22.chip_sw_all_escalation_resets.586660994 Aug 15 07:31:35 PM PDT 24 Aug 15 07:42:32 PM PDT 24 5324165624 ps
T291 /workspace/coverage/default/2.rom_e2e_asm_init_rma.3097362630 Aug 15 07:32:17 PM PDT 24 Aug 15 08:20:10 PM PDT 24 15209212480 ps
T19 /workspace/coverage/default/0.chip_sw_usbdev_stream.2353273509 Aug 15 07:07:44 PM PDT 24 Aug 15 08:28:22 PM PDT 24 18562490808 ps
T87 /workspace/coverage/default/0.chip_sw_gpio_smoketest.2127005211 Aug 15 07:07:20 PM PDT 24 Aug 15 07:10:58 PM PDT 24 2759786342 ps
T977 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3936227416 Aug 15 07:13:52 PM PDT 24 Aug 15 07:22:03 PM PDT 24 4178801486 ps
T978 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.913814333 Aug 15 07:21:46 PM PDT 24 Aug 15 07:42:02 PM PDT 24 6766664404 ps
T354 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.70997380 Aug 15 07:24:13 PM PDT 24 Aug 15 07:29:22 PM PDT 24 3473062608 ps
T807 /workspace/coverage/default/1.chip_sw_flash_crash_alert.1509164403 Aug 15 07:15:59 PM PDT 24 Aug 15 07:25:41 PM PDT 24 6538053888 ps
T979 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.2206192437 Aug 15 07:07:32 PM PDT 24 Aug 15 07:11:48 PM PDT 24 2448624899 ps
T753 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.539426919 Aug 15 07:10:31 PM PDT 24 Aug 15 07:14:20 PM PDT 24 2966593276 ps
T81 /workspace/coverage/default/1.chip_jtag_mem_access.2691008676 Aug 15 07:07:39 PM PDT 24 Aug 15 07:28:10 PM PDT 24 13850650798 ps
T842 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3128147997 Aug 15 07:32:46 PM PDT 24 Aug 15 07:39:29 PM PDT 24 4118741512 ps
T980 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2126980957 Aug 15 07:06:11 PM PDT 24 Aug 15 07:26:22 PM PDT 24 5864528077 ps
T257 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.1505416959 Aug 15 07:10:11 PM PDT 24 Aug 15 07:54:44 PM PDT 24 24815053105 ps
T57 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2515969722 Aug 15 07:27:22 PM PDT 24 Aug 15 07:36:27 PM PDT 24 4248581624 ps
T981 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1726296039 Aug 15 07:05:27 PM PDT 24 Aug 15 07:18:52 PM PDT 24 4481586710 ps
T982 /workspace/coverage/default/2.chip_sw_aes_entropy.1658098391 Aug 15 07:22:59 PM PDT 24 Aug 15 07:26:48 PM PDT 24 2195567320 ps
T353 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2516006525 Aug 15 07:14:01 PM PDT 24 Aug 15 07:27:58 PM PDT 24 3882011946 ps
T983 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3648938426 Aug 15 07:04:22 PM PDT 24 Aug 15 07:18:44 PM PDT 24 5610018328 ps
T243 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3459830964 Aug 15 07:23:38 PM PDT 24 Aug 15 07:34:04 PM PDT 24 3846394246 ps
T984 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.4054812881 Aug 15 07:08:55 PM PDT 24 Aug 15 07:11:55 PM PDT 24 2824792118 ps
T985 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.429930042 Aug 15 07:13:55 PM PDT 24 Aug 15 07:18:03 PM PDT 24 2694232680 ps
T777 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.521072896 Aug 15 07:32:47 PM PDT 24 Aug 15 07:41:20 PM PDT 24 3577240472 ps
T278 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.2331929795 Aug 15 07:06:31 PM PDT 24 Aug 15 07:20:39 PM PDT 24 5187347150 ps
T20 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.4084952784 Aug 15 07:28:45 PM PDT 24 Aug 15 07:38:37 PM PDT 24 5341825056 ps
T152 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3575857049 Aug 15 07:17:03 PM PDT 24 Aug 15 08:14:22 PM PDT 24 25236065050 ps
T986 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3487017380 Aug 15 07:09:31 PM PDT 24 Aug 15 07:30:29 PM PDT 24 5190803914 ps
T234 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3576674913 Aug 15 07:12:39 PM PDT 24 Aug 15 08:43:26 PM PDT 24 49591102770 ps
T21 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1308500419 Aug 15 07:16:49 PM PDT 24 Aug 15 07:41:51 PM PDT 24 21942645912 ps
T232 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2208172071 Aug 15 07:06:21 PM PDT 24 Aug 15 08:36:57 PM PDT 24 50627843720 ps
T271 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3636145397 Aug 15 07:12:34 PM PDT 24 Aug 15 08:17:19 PM PDT 24 15491249636 ps
T279 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2891909806 Aug 15 07:30:24 PM PDT 24 Aug 15 07:43:11 PM PDT 24 5911720916 ps
T305 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1021411051 Aug 15 07:35:14 PM PDT 24 Aug 15 07:42:43 PM PDT 24 3422280692 ps
T796 /workspace/coverage/default/24.chip_sw_all_escalation_resets.3894431420 Aug 15 07:32:47 PM PDT 24 Aug 15 07:40:05 PM PDT 24 5154528384 ps
T233 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1417341055 Aug 15 07:15:07 PM PDT 24 Aug 15 08:39:15 PM PDT 24 49304817304 ps
T235 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2038515660 Aug 15 07:11:05 PM PDT 24 Aug 15 07:18:48 PM PDT 24 5324112960 ps
T156 /workspace/coverage/default/0.chip_plic_all_irqs_10.950211063 Aug 15 07:06:20 PM PDT 24 Aug 15 07:13:53 PM PDT 24 4381740660 ps
T71 /workspace/coverage/default/1.chip_tap_straps_rma.415775857 Aug 15 07:14:24 PM PDT 24 Aug 15 07:23:32 PM PDT 24 5604462766 ps
T987 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1146490159 Aug 15 07:15:01 PM PDT 24 Aug 15 08:24:40 PM PDT 24 15518704909 ps
T804 /workspace/coverage/default/86.chip_sw_all_escalation_resets.1329877854 Aug 15 07:39:48 PM PDT 24 Aug 15 07:49:51 PM PDT 24 6074620808 ps
T735 /workspace/coverage/default/99.chip_sw_all_escalation_resets.1469992269 Aug 15 07:40:23 PM PDT 24 Aug 15 07:49:40 PM PDT 24 5801223556 ps
T391 /workspace/coverage/default/69.chip_sw_all_escalation_resets.928042782 Aug 15 07:36:40 PM PDT 24 Aug 15 07:49:37 PM PDT 24 5517730912 ps
T158 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1224045891 Aug 15 07:35:16 PM PDT 24 Aug 15 07:42:25 PM PDT 24 3731267960 ps
T183 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1239085401 Aug 15 07:07:45 PM PDT 24 Aug 15 07:18:13 PM PDT 24 4820146496 ps
T988 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3156485251 Aug 15 07:23:37 PM PDT 24 Aug 15 07:33:13 PM PDT 24 5177751540 ps
T781 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2476428187 Aug 15 07:35:59 PM PDT 24 Aug 15 07:43:24 PM PDT 24 4147590344 ps
T989 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.4237646809 Aug 15 07:08:55 PM PDT 24 Aug 15 07:33:20 PM PDT 24 8654781608 ps
T990 /workspace/coverage/default/2.rom_e2e_smoke.726080484 Aug 15 07:32:49 PM PDT 24 Aug 15 08:24:52 PM PDT 24 15032653060 ps
T991 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2494113294 Aug 15 07:27:49 PM PDT 24 Aug 15 08:36:53 PM PDT 24 29533837917 ps
T61 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.675887025 Aug 15 07:26:17 PM PDT 24 Aug 15 07:49:46 PM PDT 24 22361246560 ps
T245 /workspace/coverage/default/65.chip_sw_all_escalation_resets.1245644746 Aug 15 07:35:52 PM PDT 24 Aug 15 07:46:36 PM PDT 24 5905512040 ps
T400 /workspace/coverage/default/21.chip_sw_all_escalation_resets.2164752425 Aug 15 07:32:15 PM PDT 24 Aug 15 07:43:50 PM PDT 24 5995667818 ps
T869 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1506033254 Aug 15 07:33:50 PM PDT 24 Aug 15 07:40:59 PM PDT 24 4050322334 ps
T774 /workspace/coverage/default/52.chip_sw_all_escalation_resets.1977546216 Aug 15 07:34:59 PM PDT 24 Aug 15 07:44:19 PM PDT 24 4872676766 ps
T65 /workspace/coverage/default/2.chip_sw_alert_test.284828618 Aug 15 07:23:52 PM PDT 24 Aug 15 07:29:39 PM PDT 24 3392242280 ps
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