Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	138108	1			T78	66		T79	4		T80	63
values[2]	11179	1			T78	1		T442	113		T513	82
values[3]	4433	1			T442	29		T513	28		T895	1
values[4]	2698	1			T442	24		T513	9		T895	1
values[5]	1690	1			T442	14		T513	7		T895	1
values[6]	1156	1			T442	9		T513	2		T895	1
values[7]	982	1			T442	1		T513	1		T895	1
values[8]	783	1			T513	1		T895	1		T427	3
values[9]	615	1			T513	1		T895	1		T427	2
values[10]	467	1			T513	1		T895	1		T896	2
values[11]	415	1			T895	1		T896	2		T725	19
values[12]	346	1			T895	1		T896	2		T725	5
values[13]	387	1			T895	1		T896	2		T543	10
values[14]	363	1			T895	1		T896	2		T543	6
values[15]	341	1			T895	1		T896	2		T543	7
values[16]	360	1			T895	1		T896	2		T543	5
values[17]	346	1			T895	1		T896	2		T543	7
values[18]	338	1			T895	1		T896	2		T543	10
values[19]	308	1			T895	1		T896	2		T543	8
values[20]	292	1			T895	1		T896	3		T543	7
values[21]	346	1			T895	1		T896	2		T543	5
values[22]	407	1			T895	1		T896	2		T543	9
values[23]	386	1			T895	1		T896	2		T543	17
values[24]	307	1			T895	1		T896	2		T543	4
values[25]	338	1			T895	1		T896	2		T543	5
values[26]	307	1			T895	1		T896	2		T543	36
values[27]	354	1			T895	1		T896	2		T543	3
values[28]	315	1			T895	1		T896	2		T543	3
values[29]	338	1			T895	1		T896	2		T543	8
values[30]	316	1			T895	1		T896	2		T543	5
values[31]	289	1			T895	1		T896	2		T543	3
values[32]	369	1			T895	1		T896	2		T543	7
values[33]	342	1			T895	1		T896	2		T543	3
values[34]	348	1			T895	2		T896	2		T543	6
values[35]	317	1			T895	1		T896	2		T543	13
values[36]	294	1			T895	1		T896	2		T543	15
values[37]	383	1			T895	1		T896	2		T543	3
values[38]	338	1			T895	1		T896	2		T543	4
values[39]	293	1			T895	1		T896	2		T543	3
values[40]	347	1			T895	1		T896	2		T543	6
values[41]	314	1			T895	1		T896	2		T543	3
values[42]	306	1			T895	1		T896	2		T543	4
values[43]	390	1			T895	1		T896	2		T543	4
values[44]	302	1			T895	1		T896	2		T543	4
values[45]	273	1			T895	1		T896	2		T543	6
values[46]	294	1			T895	1		T896	2		T543	3
values[47]	293	1			T895	1		T896	2		T543	14
values[48]	314	1			T895	1		T896	2		T543	15
values[49]	278	1			T895	1		T896	2		T543	10
values[50]	279	1			T895	1		T896	2		T543	18
values[51]	335	1			T895	1		T896	2		T543	10
values[52]	244	1			T895	1		T896	2		T543	2
values[53]	292	1			T895	1		T896	2		T543	16
values[54]	234	1			T895	1		T896	2		T543	7
values[55]	240	1			T895	1		T896	2		T543	2
values[56]	248	1			T895	1		T896	2		T543	7
values[57]	249	1			T895	1		T896	2		T543	6
values[58]	292	1			T895	1		T896	2		T543	8
values[59]	248	1			T895	1		T896	2		T543	3
values[60]	274	1			T895	1		T896	2		T543	3
values[61]	228	1			T895	1		T896	2		T543	6
values[62]	283	1			T895	1		T896	2		T543	13
values[63]	293	1			T895	1		T896	2		T543	6
values[64]	270	1			T895	1		T896	2		T543	15
values[65]	299	1			T895	1		T896	2		T543	9
values[66]	239	1			T895	1		T896	2		T543	3
values[67]	195	1			T895	1		T896	2		T543	3
values[68]	190	1			T895	1		T896	2		T543	7
values[69]	187	1			T895	1		T896	2		T543	13
values[70]	146	1			T895	1		T896	2		T543	4
values[71]	153	1			T895	1		T896	2		T543	2
values[72]	177	1			T895	1		T896	2		T543	6
values[73]	134	1			T895	1		T896	2		T543	4
values[74]	120	1			T895	1		T896	2		T704	8
values[75]	121	1			T895	1		T896	2		T704	6
values[76]	97	1			T895	1		T896	2		T704	3
values[77]	71	1			T895	1		T896	2		T704	4
values[78]	74	1			T895	1		T896	2		T704	6
values[79]	89	1			T895	1		T896	3		T704	11
values[80]	84	1			T895	1		T896	3		T704	11
values[81]	65	1			T895	1		T896	5		T704	1
values[82]	76	1			T895	1		T896	3		T461	1
values[83]	72	1			T895	1		T896	3		T461	1
values[84]	89	1			T895	1		T896	6		T461	1
values[85]	95	1			T895	1		T896	2		T461	1
values[86]	69	1			T895	1		T896	3		T461	1
values[87]	71	1			T895	1		T896	11		T461	1
values[88]	56	1			T895	1		T896	7		T461	1
values[89]	57	1			T895	1		T896	3		T461	1
values[90]	60	1			T895	1		T896	6		T461	1
values[91]	56	1			T895	1		T896	4		T461	1
values[92]	56	1			T895	1		T896	8		T461	1
values[93]	75	1			T895	1		T896	2		T461	1
values[94]	65	1			T895	1		T896	7		T461	2
values[95]	79	1			T895	1		T896	10		T461	3
values[96]	59	1			T895	1		T896	2		T461	1
values[97]	68	1			T895	1		T896	2		T461	4
values[98]	75	1			T895	1		T896	6		T461	7
values[99]	87	1			T895	1		T896	3		T461	10
values[100]	78	1			T895	1		T896	11		T461	2
values[101]	76	1			T895	1		T896	8		T461	3
values[102]	62	1			T895	1		T896	5		T461	1
values[103]	66	1			T895	1		T896	18		T461	2
values[104]	65	1			T895	1		T896	12		T461	1
values[105]	52	1			T895	1		T896	6		T461	1
values[106]	60	1			T895	1		T896	5		T461	1
values[107]	51	1			T895	1		T896	3		T461	4
values[108]	48	1			T895	1		T896	4		T461	1
values[109]	59	1			T895	1		T896	4		T461	2
values[110]	61	1			T895	1		T896	7		T461	2
values[111]	49	1			T895	1		T896	6		T461	3
values[112]	50	1			T895	1		T896	2		T461	2
values[113]	52	1			T895	1		T896	3		T461	4
values[114]	57	1			T895	1		T896	4		T461	2
values[115]	51	1			T895	1		T896	4		T461	1
values[116]	50	1			T895	1		T896	2		T461	1
values[117]	65	1			T895	1		T896	10		T461	6
values[118]	44	1			T895	1		T896	3		T461	4
values[119]	50	1			T895	1		T896	5		T461	4
values[120]	54	1			T895	1		T896	6		T461	4
values[121]	50	1			T895	1		T896	2		T461	3
values[122]	61	1			T895	1		T896	2		T461	4
values[123]	68	1			T895	1		T896	3		T461	10
values[124]	45	1			T895	1		T896	2		T461	1
values[125]	70	1			T895	1		T896	3		T461	1
values[126]	115	1			T895	1		T896	5		T461	1
values[127]	743	1			T895	27		T896	44		T461	31
values[128]	6973	1			T895	284		T896	521		T461	288