Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	156375	1			T78	64		T79	9		T80	52
values[2]	4430	1			T442	79		T513	4		T504	2
values[3]	2017	1			T442	61		T521	2		T436	8
values[4]	1444	1			T442	43		T436	5		T891	1
values[5]	1109	1			T442	31		T436	1		T891	1
values[6]	982	1			T442	17		T436	5		T891	1
values[7]	703	1			T442	13		T436	7		T891	1
values[8]	685	1			T442	22		T436	11		T891	1
values[9]	579	1			T442	6		T436	7		T891	1
values[10]	566	1			T442	1		T436	5		T891	1
values[11]	446	1			T436	3		T891	1		T726	5
values[12]	391	1			T436	7		T891	1		T726	12
values[13]	379	1			T436	5		T891	1		T726	1
values[14]	296	1			T436	2		T891	1		T887	5
values[15]	268	1			T436	3		T891	1		T887	1
values[16]	225	1			T436	8		T891	1		T461	1
values[17]	238	1			T436	11		T891	1		T461	1
values[18]	205	1			T436	8		T891	1		T461	1
values[19]	179	1			T436	4		T891	1		T461	1
values[20]	145	1			T436	5		T891	1		T461	1
values[21]	181	1			T436	3		T891	1		T461	1
values[22]	155	1			T436	4		T891	1		T461	1
values[23]	145	1			T436	11		T891	1		T461	1
values[24]	145	1			T436	10		T891	1		T461	1
values[25]	126	1			T436	3		T891	1		T461	1
values[26]	98	1			T436	4		T891	1		T461	1
values[27]	97	1			T436	8		T891	1		T461	1
values[28]	108	1			T436	7		T891	1		T461	1
values[29]	132	1			T436	3		T891	1		T461	1
values[30]	137	1			T436	2		T891	1		T461	1
values[31]	105	1			T436	1		T891	1		T461	1
values[32]	86	1			T436	3		T891	1		T461	1
values[33]	87	1			T436	10		T891	1		T461	1
values[34]	88	1			T436	12		T891	1		T461	1
values[35]	84	1			T436	4		T891	1		T461	1
values[36]	85	1			T436	9		T891	1		T461	1
values[37]	102	1			T436	15		T891	1		T461	1
values[38]	88	1			T436	3		T891	1		T461	1
values[39]	101	1			T436	3		T891	1		T461	1
values[40]	74	1			T436	4		T891	1		T461	1
values[41]	74	1			T436	1		T891	1		T461	1
values[42]	84	1			T436	3		T891	1		T461	1
values[43]	79	1			T436	4		T891	1		T461	1
values[44]	81	1			T436	3		T891	1		T461	1
values[45]	80	1			T436	1		T891	1		T461	1
values[46]	81	1			T436	9		T891	1		T461	1
values[47]	77	1			T436	10		T891	1		T461	1
values[48]	74	1			T436	8		T891	1		T461	1
values[49]	67	1			T436	1		T891	1		T461	1
values[50]	64	1			T891	1		T461	1		T890	1
values[51]	63	1			T891	1		T461	1		T890	1
values[52]	56	1			T891	1		T461	1		T890	1
values[53]	58	1			T891	1		T461	1		T890	1
values[54]	54	1			T891	1		T461	1		T890	1
values[55]	46	1			T891	1		T461	1		T890	1
values[56]	54	1			T891	1		T461	1		T890	1
values[57]	52	1			T891	1		T461	1		T890	1
values[58]	56	1			T891	1		T461	1		T890	1
values[59]	60	1			T891	1		T461	1		T890	1
values[60]	60	1			T891	1		T461	1		T890	1
values[61]	53	1			T891	1		T461	1		T890	1
values[62]	58	1			T891	1		T461	1		T890	1
values[63]	54	1			T891	1		T461	1		T890	1
values[64]	50	1			T891	1		T461	1		T890	1
values[65]	68	1			T891	1		T461	1		T890	1
values[66]	63	1			T891	1		T461	1		T890	1
values[67]	67	1			T891	1		T461	1		T890	1
values[68]	65	1			T891	1		T461	1		T890	1
values[69]	53	1			T891	1		T461	1		T890	1
values[70]	58	1			T891	1		T461	1		T890	1
values[71]	67	1			T891	1		T461	1		T890	1
values[72]	58	1			T891	1		T461	1		T890	1
values[73]	51	1			T891	1		T461	1		T890	1
values[74]	48	1			T891	1		T461	1		T890	1
values[75]	48	1			T891	1		T461	1		T890	1
values[76]	63	1			T891	1		T461	1		T890	1
values[77]	61	1			T891	1		T461	1		T890	1
values[78]	63	1			T891	1		T461	1		T890	1
values[79]	85	1			T891	1		T461	1		T890	1
values[80]	86	1			T891	1		T461	1		T890	1
values[81]	92	1			T891	1		T461	1		T890	1
values[82]	82	1			T891	1		T461	2		T890	1
values[83]	91	1			T891	1		T461	1		T890	1
values[84]	64	1			T891	1		T461	1		T890	1
values[85]	78	1			T891	1		T461	1		T890	1
values[86]	78	1			T891	3		T461	1		T890	1
values[87]	74	1			T891	5		T461	1		T890	1
values[88]	88	1			T891	3		T461	1		T890	1
values[89]	67	1			T891	2		T461	1		T890	1
values[90]	80	1			T891	9		T461	1		T890	1
values[91]	85	1			T891	4		T461	1		T890	1
values[92]	83	1			T891	3		T461	1		T890	1
values[93]	88	1			T891	4		T461	1		T890	1
values[94]	83	1			T891	4		T461	1		T890	1
values[95]	81	1			T891	4		T461	1		T890	1
values[96]	69	1			T891	2		T461	1		T890	1
values[97]	83	1			T891	4		T461	1		T890	1
values[98]	79	1			T891	6		T461	1		T890	1
values[99]	88	1			T891	3		T461	1		T890	1
values[100]	87	1			T891	3		T461	1		T890	1
values[101]	97	1			T891	4		T461	4		T890	1
values[102]	102	1			T891	2		T461	2		T890	3
values[103]	135	1			T891	4		T461	5		T890	6
values[104]	120	1			T891	4		T461	3		T890	2
values[105]	98	1			T891	2		T461	6		T890	2
values[106]	99	1			T891	1		T461	2		T890	3
values[107]	94	1			T891	1		T461	4		T890	6
values[108]	92	1			T891	3		T461	1		T890	1
values[109]	89	1			T891	4		T461	5		T890	2
values[110]	93	1			T891	1		T461	2		T890	5
values[111]	93	1			T891	1		T461	1		T890	5
values[112]	96	1			T891	2		T461	1		T890	1
values[113]	116	1			T891	1		T461	1		T890	6
values[114]	121	1			T891	2		T461	4		T890	2
values[115]	106	1			T891	2		T461	3		T890	1
values[116]	97	1			T891	2		T461	1		T890	1
values[117]	106	1			T891	2		T461	2		T890	3
values[118]	92	1			T891	1		T461	1		T890	1
values[119]	103	1			T891	3		T461	4		T890	2
values[120]	90	1			T891	2		T461	2		T890	2
values[121]	88	1			T891	1		T461	2		T890	1
values[122]	126	1			T891	1		T461	1		T890	2
values[123]	124	1			T891	3		T461	1		T890	4
values[124]	171	1			T891	2		T461	1		T890	4
values[125]	292	1			T891	3		T461	1		T890	1
values[126]	754	1			T891	12		T461	11		T890	15
values[127]	2998	1			T891	117		T461	108		T890	109
values[128]	5472	1			T891	175		T461	270		T890	170