Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	134309	1			T78	53		T79	11		T80	60
values[2]	9182	1			T78	1		T442	5		T513	2
values[3]	3536	1			T504	143		T891	1		T724	49
values[4]	2220	1			T504	79		T891	1		T724	19
values[5]	1417	1			T504	52		T891	1		T724	19
values[6]	864	1			T504	18		T891	1		T724	23
values[7]	602	1			T504	2		T891	1		T724	7
values[8]	558	1			T891	1		T724	10		T726	3
values[9]	431	1			T891	1		T724	7		T726	3
values[10]	373	1			T891	1		T724	13		T726	1
values[11]	274	1			T891	1		T724	2		T726	1
values[12]	267	1			T891	1		T724	12		T726	1
values[13]	239	1			T891	1		T724	10		T726	4
values[14]	247	1			T891	1		T724	4		T726	3
values[15]	228	1			T891	1		T724	1		T726	5
values[16]	257	1			T891	1		T726	4		T904	1
values[17]	258	1			T891	1		T726	1		T904	1
values[18]	236	1			T891	1		T726	1		T904	1
values[19]	220	1			T891	1		T726	4		T904	1
values[20]	271	1			T891	1		T726	5		T904	1
values[21]	237	1			T891	1		T726	6		T904	1
values[22]	250	1			T891	1		T726	9		T904	1
values[23]	173	1			T891	1		T726	9		T904	1
values[24]	209	1			T891	1		T726	6		T904	1
values[25]	190	1			T891	1		T726	8		T904	1
values[26]	214	1			T891	1		T726	8		T904	1
values[27]	219	1			T891	1		T726	8		T904	1
values[28]	200	1			T891	1		T726	4		T904	1
values[29]	216	1			T891	1		T726	1		T904	1
values[30]	212	1			T891	1		T726	3		T904	1
values[31]	244	1			T891	2		T726	4		T904	1
values[32]	249	1			T891	1		T726	5		T904	1
values[33]	206	1			T891	1		T726	3		T904	1
values[34]	204	1			T891	1		T726	5		T904	1
values[35]	204	1			T891	1		T726	10		T904	1
values[36]	228	1			T891	1		T726	5		T904	1
values[37]	188	1			T891	1		T726	3		T904	1
values[38]	200	1			T891	1		T726	3		T904	1
values[39]	231	1			T891	1		T726	2		T904	1
values[40]	221	1			T891	1		T726	4		T904	1
values[41]	186	1			T891	1		T726	5		T904	2
values[42]	183	1			T891	1		T726	1		T904	1
values[43]	205	1			T891	1		T726	1		T904	1
values[44]	241	1			T891	1		T726	2		T904	1
values[45]	196	1			T891	1		T726	2		T904	1
values[46]	187	1			T891	1		T726	4		T904	1
values[47]	197	1			T891	1		T726	1		T904	1
values[48]	215	1			T891	2		T726	2		T904	1
values[49]	187	1			T891	1		T726	1		T904	1
values[50]	142	1			T891	1		T726	4		T904	1
values[51]	179	1			T891	1		T726	2		T904	1
values[52]	148	1			T891	1		T726	1		T904	1
values[53]	170	1			T891	1		T726	3		T904	1
values[54]	161	1			T891	1		T726	1		T904	1
values[55]	148	1			T891	1		T726	2		T904	1
values[56]	154	1			T891	1		T726	2		T904	1
values[57]	150	1			T891	1		T726	1		T904	1
values[58]	154	1			T891	1		T726	1		T904	1
values[59]	173	1			T891	1		T726	8		T904	1
values[60]	138	1			T891	1		T726	4		T904	1
values[61]	163	1			T891	1		T726	2		T904	1
values[62]	127	1			T891	1		T726	3		T904	1
values[63]	126	1			T891	1		T726	3		T904	1
values[64]	143	1			T891	1		T726	4		T904	1
values[65]	123	1			T891	1		T726	1		T904	1
values[66]	99	1			T891	1		T726	3		T904	1
values[67]	69	1			T891	1		T726	1		T904	1
values[68]	83	1			T891	1		T726	1		T904	1
values[69]	64	1			T891	1		T726	1		T904	1
values[70]	84	1			T891	1		T726	2		T904	1
values[71]	67	1			T891	1		T726	1		T904	1
values[72]	55	1			T891	1		T726	2		T904	1
values[73]	80	1			T891	1		T726	9		T904	1
values[74]	82	1			T891	1		T726	8		T904	1
values[75]	75	1			T891	1		T726	2		T904	1
values[76]	58	1			T891	1		T726	1		T904	1
values[77]	69	1			T891	1		T726	5		T904	1
values[78]	65	1			T891	1		T726	4		T904	1
values[79]	50	1			T891	1		T726	5		T904	1
values[80]	53	1			T891	1		T726	2		T904	1
values[81]	47	1			T891	1		T726	3		T904	1
values[82]	41	1			T891	1		T726	1		T904	1
values[83]	50	1			T891	1		T726	1		T904	1
values[84]	46	1			T891	1		T726	3		T904	1
values[85]	42	1			T891	1		T726	2		T904	1
values[86]	54	1			T891	1		T726	6		T904	1
values[87]	58	1			T891	1		T726	4		T904	1
values[88]	38	1			T891	1		T726	4		T904	1
values[89]	40	1			T891	1		T726	7		T904	1
values[90]	41	1			T891	1		T726	2		T904	1
values[91]	38	1			T891	1		T726	1		T904	1
values[92]	60	1			T891	1		T726	2		T904	1
values[93]	70	1			T891	1		T726	10		T904	1
values[94]	48	1			T891	1		T726	6		T904	1
values[95]	50	1			T891	1		T726	3		T904	1
values[96]	47	1			T891	1		T726	5		T904	1
values[97]	44	1			T891	2		T726	2		T904	1
values[98]	38	1			T891	1		T904	1		T451	6
values[99]	34	1			T891	1		T904	1		T451	1
values[100]	42	1			T891	1		T904	1		T451	6
values[101]	43	1			T891	1		T904	1		T451	5
values[102]	32	1			T891	1		T904	1		T451	1
values[103]	26	1			T891	1		T904	1		T451	3
values[104]	47	1			T891	1		T904	1		T451	4
values[105]	30	1			T891	1		T904	1		T451	2
values[106]	47	1			T891	1		T904	2		T451	8
values[107]	46	1			T891	1		T904	1		T451	7
values[108]	45	1			T891	1		T904	1		T451	1
values[109]	34	1			T891	1		T904	1		T451	1
values[110]	32	1			T891	1		T904	1		T924	1
values[111]	30	1			T891	1		T904	1		T924	1
values[112]	29	1			T891	1		T904	1		T924	1
values[113]	26	1			T891	1		T904	1		T924	1
values[114]	36	1			T891	1		T904	1		T924	1
values[115]	30	1			T891	1		T904	2		T924	1
values[116]	34	1			T891	1		T904	1		T924	1
values[117]	37	1			T891	1		T904	1		T924	1
values[118]	23	1			T891	1		T904	1		T924	1
values[119]	27	1			T891	1		T904	3		T924	1
values[120]	30	1			T891	1		T904	3		T924	1
values[121]	28	1			T891	1		T904	1		T924	3
values[122]	35	1			T891	2		T904	1		T924	2
values[123]	31	1			T891	1		T904	6		T924	2
values[124]	45	1			T891	1		T904	1		T924	7
values[125]	45	1			T891	1		T904	4		T924	6
values[126]	42	1			T891	3		T904	3		T924	2
values[127]	451	1			T891	40		T904	44		T924	38
values[128]	4027	1			T891	355		T904	382		T924	343