Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
118560 | 
1 | 
 | 
 | 
T78 | 
67 | 
 | 
T79 | 
7 | 
 | 
T80 | 
59 | 
| auto[1] | 
66780 | 
1 | 
 | 
 | 
T78 | 
9 | 
 | 
T79 | 
3 | 
 | 
T80 | 
2 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
46773 | 
1 | 
 | 
 | 
T78 | 
27 | 
 | 
T79 | 
5 | 
 | 
T80 | 
9 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
130302 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
55038 | 
1 | 
 | 
 | 
T78 | 
23 | 
 | 
T79 | 
4 | 
 | 
T80 | 
15 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
14690 | 
1 | 
 | 
 | 
T78 | 
7 | 
 | 
T79 | 
3 | 
 | 
T80 | 
1 | 
 
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
119363 | 
1 | 
 | 
 | 
T78 | 
52 | 
 | 
T80 | 
56 | 
 | 
T82 | 
5 | 
| auto[1] | 
65325 | 
1 | 
 | 
 | 
T78 | 
13 | 
 | 
T79 | 
3 | 
 | 
T80 | 
2 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
46491 | 
1 | 
 | 
 | 
T78 | 
22 | 
 | 
T79 | 
1 | 
 | 
T80 | 
8 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
129975 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
54713 | 
1 | 
 | 
 | 
T78 | 
21 | 
 | 
T79 | 
1 | 
 | 
T80 | 
13 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
14549 | 
1 | 
 | 
 | 
T78 | 
11 | 
 | 
T80 | 
2 | 
 | 
T389 | 
4 | 
 
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
110891 | 
1 | 
 | 
 | 
T78 | 
35 | 
 | 
T79 | 
3 | 
 | 
T80 | 
10 | 
| auto[1] | 
62019 | 
1 | 
 | 
 | 
T78 | 
27 | 
 | 
T79 | 
1 | 
 | 
T80 | 
37 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
43333 | 
1 | 
 | 
 | 
T78 | 
19 | 
 | 
T79 | 
1 | 
 | 
T80 | 
6 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
121758 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
51152 | 
1 | 
 | 
 | 
T78 | 
15 | 
 | 
T79 | 
2 | 
 | 
T80 | 
19 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
13591 | 
1 | 
 | 
 | 
T78 | 
5 | 
 | 
T79 | 
1 | 
 | 
T82 | 
1 | 
 
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
112204 | 
1 | 
 | 
 | 
T78 | 
19 | 
 | 
T79 | 
4 | 
 | 
T80 | 
16 | 
| auto[1] | 
61454 | 
1 | 
 | 
 | 
T78 | 
40 | 
 | 
T80 | 
43 | 
 | 
T389 | 
5 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
43998 | 
1 | 
 | 
 | 
T78 | 
22 | 
 | 
T80 | 
6 | 
 | 
T82 | 
1 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
121882 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
51776 | 
1 | 
 | 
 | 
T78 | 
19 | 
 | 
T79 | 
1 | 
 | 
T80 | 
13 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
13820 | 
1 | 
 | 
 | 
T78 | 
9 | 
 | 
T80 | 
1 | 
 | 
T389 | 
1 | 
 
Summary for Variable cp_error
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for cp_error
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
118899 | 
1 | 
 | 
 | 
T78 | 
39 | 
 | 
T79 | 
3 | 
 | 
T80 | 
28 | 
| auto[1] | 
67762 | 
1 | 
 | 
 | 
T78 | 
30 | 
 | 
T79 | 
7 | 
 | 
T80 | 
41 | 
Summary for Variable cp_opcode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_opcode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
47878 | 
1 | 
 | 
 | 
T78 | 
26 | 
 | 
T79 | 
3 | 
 | 
T80 | 
8 | 
Summary for Variable cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_size
Excluded/Illegal bins
| NAME | COUNT | STATUS | 
| others | 
130131 | 
Excluded | 
Covered bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| biggest_size | 
56530 | 
1 | 
 | 
 | 
T78 | 
21 | 
 | 
T79 | 
4 | 
 | 
T80 | 
14 | 
Summary for Cross tl_d_chan_cov_cg_cc
Samples crossed: cp_opcode cp_size
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc
Bins
| cp_opcode | cp_size | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| values[0x1] | 
biggest_size | 
14952 | 
1 | 
 | 
 | 
T78 | 
5 | 
 | 
T79 | 
1 | 
 | 
T80 | 
2 |