Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_req_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_req_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
500 |
1 |
|
|
T79 |
1 |
|
T210 |
1 |
|
T768 |
1 |
small_delay |
658 |
1 |
|
|
T82 |
1 |
|
T442 |
1 |
|
T513 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
Summary for Variable cp_rsp_dly
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_rsp_dly
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
big_delay |
200 |
1 |
|
|
T210 |
1 |
|
T768 |
1 |
|
T520 |
1 |
small_delay |
958 |
1 |
|
|
T79 |
1 |
|
T82 |
1 |
|
T442 |
1 |
zero |
642 |
1 |
|
|
T78 |
1 |
|
T80 |
1 |
|
T389 |
1 |
0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |