Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	468	1			T442	3		T415	1		T433	2
all_values[1]	476	1			T442	2		T415	2		T438	2
all_values[2]	482	1			T442	1		T513	1		T415	2
all_values[3]	459	1			T442	2		T415	4		T944	1
all_values[4]	493	1			T442	2		T415	1		T433	2
all_values[5]	480	1			T442	2		T433	1		T438	3
all_values[6]	484	1			T442	4		T513	1		T504	2
all_values[7]	466	1			T442	3		T504	2		T415	1
all_values[8]	480	1			T442	3		T513	1		T504	1
all_values[9]	490	1			T442	1		T415	2		T810	1
all_values[10]	456	1			T442	2		T504	1		T415	2
all_values[11]	465	1			T442	2		T415	1		T438	7
all_values[12]	467	1			T442	2		T513	1		T415	2
all_values[13]	511	1			T442	1		T513	1		T504	1
all_values[14]	477	1			T442	1		T504	2		T415	2
all_values[15]	470	1			T442	2		T810	2		T438	1
all_values[16]	514	1			T442	4		T504	1		T415	1
all_values[17]	498	1			T442	3		T415	3		T438	1
all_values[18]	492	1			T442	3		T438	4		T421	1
all_values[19]	492	1			T442	1		T513	1		T504	1
all_values[20]	488	1			T442	2		T504	3		T415	2
all_values[21]	516	1			T442	2		T438	1		T427	3
all_values[22]	508	1			T442	1		T504	2		T415	2
all_values[23]	496	1			T442	1		T415	1		T438	2
all_values[24]	490	1			T442	1		T513	1		T415	1
all_values[25]	443	1			T442	3		T504	1		T415	3
all_values[26]	465	1			T442	1		T415	2		T438	2
all_values[27]	455	1			T442	3		T415	1		T810	1
all_values[28]	489	1			T442	4		T433	1		T810	1
all_values[29]	482	1			T442	3		T415	1		T438	5
all_values[30]	490	1			T442	2		T513	2		T433	1
all_values[31]	470	1			T442	1		T513	1		T433	1
all_values[32]	520	1			T513	1		T504	2		T415	1
all_values[33]	496	1			T442	1		T504	2		T415	1
all_values[34]	521	1			T442	3		T513	1		T415	1
all_values[35]	535	1			T442	3		T504	1		T415	1
all_values[36]	511	1			T415	2		T810	1		T438	1
all_values[37]	520	1			T442	3		T504	1		T415	1
all_values[38]	480	1			T438	2		T421	1		T420	2
all_values[39]	478	1			T442	4		T513	1		T415	1
all_values[40]	477	1			T442	2		T433	4		T438	2
all_values[41]	479	1			T442	1		T504	2		T415	2
all_values[42]	484	1			T442	1		T513	1		T433	1
all_values[43]	517	1			T442	3		T438	1		T427	4
all_values[44]	483	1			T442	4		T504	1		T415	2
all_values[45]	449	1			T442	4		T504	2		T438	4
all_values[46]	530	1			T442	2		T504	1		T415	2
all_values[47]	442	1			T442	1		T415	1		T433	1
all_values[48]	465	1			T442	4		T415	2		T810	1
all_values[49]	468	1			T442	3		T504	1		T415	2