Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3636	1			T442	18		T513	2		T504	4
all_values[1]	3704	1			T442	19		T513	3		T504	3
all_values[2]	3550	1			T442	15		T513	2		T504	1
all_values[3]	3623	1			T442	25		T513	1		T504	3
all_values[4]	3605	1			T442	14		T513	4		T504	2
all_values[5]	3650	1			T442	14		T513	3		T504	4
all_values[6]	3529	1			T442	23		T513	1		T504	3
all_values[7]	3621	1			T442	12		T513	2		T504	3
all_values[8]	3566	1			T442	10		T504	1		T415	17
all_values[9]	3585	1			T442	18		T513	2		T504	3
all_values[10]	3556	1			T442	17		T513	2		T504	4
all_values[11]	3484	1			T442	19		T513	3		T504	3
all_values[12]	3552	1			T442	17		T513	2		T504	2
all_values[13]	3556	1			T442	18		T504	5		T415	27
all_values[14]	3569	1			T442	14		T513	6		T504	2
all_values[15]	3603	1			T442	17		T513	3		T504	3
all_values[16]	3505	1			T442	18		T504	4		T415	11
all_values[17]	3707	1			T442	9		T513	2		T504	3
all_values[18]	3550	1			T442	16		T513	3		T504	3
all_values[19]	3587	1			T442	23		T513	4		T504	2
all_values[20]	3544	1			T442	17		T504	3		T415	21
all_values[21]	3599	1			T442	23		T513	2		T504	3
all_values[22]	3575	1			T442	17		T415	19		T433	8
all_values[23]	3574	1			T442	11		T513	2		T504	1
all_values[24]	3600	1			T442	18		T513	1		T504	2
all_values[25]	3625	1			T442	13		T513	2		T504	8
all_values[26]	3614	1			T442	9		T513	5		T504	3
all_values[27]	3557	1			T442	14		T513	4		T504	6
all_values[28]	3534	1			T442	15		T513	3		T504	5
all_values[29]	3642	1			T442	11		T513	2		T504	2
all_values[30]	3522	1			T442	19		T513	2		T504	5
all_values[31]	3593	1			T442	23		T513	5		T504	1
all_values[32]	3538	1			T442	17		T513	2		T504	2
all_values[33]	3511	1			T442	16		T513	2		T504	1
all_values[34]	3606	1			T442	24		T504	3		T415	8
all_values[35]	3532	1			T442	19		T513	2		T504	1
all_values[36]	3583	1			T442	21		T513	3		T504	3
all_values[37]	3483	1			T442	12		T513	5		T504	4
all_values[38]	3638	1			T442	14		T513	4		T504	3
all_values[39]	3574	1			T442	20		T513	1		T504	2
all_values[40]	3596	1			T442	11		T513	2		T504	1
all_values[41]	3582	1			T442	16		T513	2		T504	3
all_values[42]	3512	1			T442	18		T513	3		T504	1
all_values[43]	3490	1			T442	18		T513	2		T504	5
all_values[44]	3548	1			T442	22		T513	1		T504	4
all_values[45]	3558	1			T442	15		T513	2		T415	15
all_values[46]	3559	1			T442	15		T504	3		T415	17
all_values[47]	3491	1			T442	16		T504	8		T415	15
all_values[48]	3522	1			T442	17		T513	1		T504	2
all_values[49]	3558	1			T442	16		T513	6		T504	1
all_values[50]	3609	1			T442	22		T513	3		T504	3
all_values[51]	3724	1			T442	23		T513	3		T504	6
all_values[52]	3668	1			T442	14		T513	2		T504	3
all_values[53]	3572	1			T442	19		T513	1		T504	4
all_values[54]	3550	1			T442	17		T513	1		T415	18
all_values[55]	3502	1			T442	25		T513	5		T504	1
all_values[56]	3512	1			T442	18		T513	2		T504	2
all_values[57]	3560	1			T442	20		T513	2		T504	3
all_values[58]	3611	1			T442	16		T513	1		T504	1
all_values[59]	3564	1			T442	15		T513	2		T415	25
all_values[60]	3591	1			T442	19		T513	2		T504	3
all_values[61]	3567	1			T442	16		T513	3		T504	1
all_values[62]	3557	1			T442	21		T513	1		T504	3
all_values[63]	3573	1			T442	21		T513	2		T504	2