Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139359	1			T72	84		T73	51		T74	39
values[2]	9941	1			T74	1		T249	4		T536	2
values[3]	3668	1			T641	1		T516	14		T439	5
values[4]	2160	1			T516	7		T439	5		T612	16
values[5]	1312	1			T516	11		T439	3		T612	9
values[6]	859	1			T516	9		T612	1		T796	46
values[7]	553	1			T516	4		T796	10		T549	5
values[8]	462	1			T516	6		T796	1		T549	1
values[9]	392	1			T516	16		T806	1		T480	2
values[10]	315	1			T516	10		T806	1		T480	4
values[11]	350	1			T516	4		T806	1		T480	27
values[12]	302	1			T516	3		T806	1		T480	6
values[13]	262	1			T516	3		T806	1		T480	4
values[14]	252	1			T516	6		T806	1		T480	6
values[15]	287	1			T516	16		T806	1		T480	14
values[16]	263	1			T516	11		T806	1		T480	6
values[17]	314	1			T516	5		T806	1		T480	3
values[18]	279	1			T516	2		T806	1		T480	5
values[19]	221	1			T516	3		T806	1		T480	3
values[20]	253	1			T516	3		T806	1		T480	15
values[21]	222	1			T516	3		T806	1		T480	11
values[22]	218	1			T516	2		T806	1		T480	4
values[23]	298	1			T516	5		T806	1		T480	6
values[24]	192	1			T516	7		T806	1		T480	8
values[25]	226	1			T516	2		T806	1		T480	11
values[26]	202	1			T516	6		T806	1		T480	5
values[27]	192	1			T516	8		T806	1		T480	8
values[28]	229	1			T516	5		T806	1		T480	3
values[29]	232	1			T516	2		T806	1		T480	4
values[30]	201	1			T516	2		T806	1		T480	4
values[31]	217	1			T516	5		T806	1		T480	4
values[32]	209	1			T516	2		T806	1		T480	8
values[33]	248	1			T516	6		T806	1		T480	30
values[34]	215	1			T516	2		T806	1		T480	6
values[35]	217	1			T516	6		T806	2		T480	5
values[36]	245	1			T516	7		T806	1		T480	7
values[37]	208	1			T516	3		T806	1		T480	11
values[38]	219	1			T516	7		T806	1		T480	6
values[39]	221	1			T516	8		T806	1		T480	6
values[40]	207	1			T516	6		T806	1		T480	15
values[41]	212	1			T516	4		T806	1		T480	8
values[42]	206	1			T516	3		T806	1		T480	3
values[43]	197	1			T516	10		T806	1		T480	4
values[44]	214	1			T516	9		T806	1		T480	5
values[45]	216	1			T516	12		T806	1		T480	5
values[46]	220	1			T516	18		T806	1		T480	10
values[47]	201	1			T516	12		T806	1		T480	10
values[48]	204	1			T516	7		T806	1		T480	6
values[49]	205	1			T516	14		T806	1		T480	18
values[50]	227	1			T516	10		T806	1		T480	17
values[51]	187	1			T516	8		T806	1		T480	6
values[52]	192	1			T516	6		T806	1		T480	9
values[53]	190	1			T516	6		T806	1		T480	13
values[54]	162	1			T516	4		T806	1		T480	4
values[55]	154	1			T516	5		T806	1		T480	4
values[56]	181	1			T516	7		T806	1		T480	6
values[57]	189	1			T516	3		T806	1		T480	7
values[58]	152	1			T516	2		T806	1		T480	6
values[59]	178	1			T516	4		T806	1		T480	2
values[60]	164	1			T516	2		T806	1		T480	5
values[61]	166	1			T516	2		T806	1		T480	4
values[62]	174	1			T516	9		T806	1		T480	3
values[63]	156	1			T516	9		T806	1		T480	10
values[64]	154	1			T516	6		T806	1		T480	7
values[65]	140	1			T516	4		T806	1		T480	7
values[66]	146	1			T516	7		T806	1		T480	4
values[67]	109	1			T516	9		T806	1		T480	11
values[68]	132	1			T516	13		T806	1		T815	6
values[69]	157	1			T516	21		T806	1		T815	5
values[70]	133	1			T516	23		T806	1		T815	10
values[71]	145	1			T516	13		T806	1		T815	5
values[72]	138	1			T516	11		T806	1		T815	5
values[73]	141	1			T516	16		T806	1		T815	6
values[74]	95	1			T516	7		T806	1		T815	3
values[75]	95	1			T516	5		T806	1		T815	21
values[76]	106	1			T516	6		T806	1		T815	6
values[77]	99	1			T516	10		T806	1		T815	8
values[78]	80	1			T516	7		T806	1		T815	4
values[79]	79	1			T516	5		T806	1		T815	9
values[80]	73	1			T516	10		T806	2		T499	6
values[81]	84	1			T516	14		T806	1		T499	17
values[82]	89	1			T516	7		T806	1		T499	12
values[83]	86	1			T516	8		T806	1		T499	23
values[84]	95	1			T516	11		T806	1		T499	15
values[85]	72	1			T516	9		T806	1		T499	7
values[86]	77	1			T516	8		T806	1		T499	6
values[87]	85	1			T516	8		T806	1		T499	12
values[88]	77	1			T516	12		T806	1		T499	5
values[89]	102	1			T516	21		T806	1		T499	2
values[90]	74	1			T516	19		T806	1		T499	8
values[91]	61	1			T516	9		T806	1		T499	8
values[92]	57	1			T516	14		T806	1		T499	3
values[93]	58	1			T516	7		T806	1		T499	3
values[94]	54	1			T516	8		T806	1		T486	18
values[95]	58	1			T516	14		T806	1		T486	15
values[96]	59	1			T516	8		T806	1		T486	19
values[97]	61	1			T516	6		T806	1		T486	17
values[98]	47	1			T516	2		T806	1		T486	5
values[99]	38	1			T516	1		T806	1		T486	7
values[100]	46	1			T516	2		T806	1		T486	5
values[101]	49	1			T516	3		T806	1		T486	4
values[102]	50	1			T516	4		T806	1		T486	14
values[103]	45	1			T516	2		T806	1		T486	7
values[104]	55	1			T516	4		T806	1		T486	11
values[105]	47	1			T516	1		T806	1		T486	12
values[106]	48	1			T516	1		T806	1		T486	8
values[107]	45	1			T516	4		T806	1		T486	5
values[108]	45	1			T516	4		T806	1		T486	2
values[109]	37	1			T516	2		T806	1		T486	3
values[110]	41	1			T516	1		T806	3		T486	3
values[111]	39	1			T516	1		T806	2		T486	4
values[112]	45	1			T516	5		T806	1		T486	6
values[113]	57	1			T516	7		T806	3		T486	4
values[114]	50	1			T516	4		T806	1		T486	7
values[115]	39	1			T516	3		T806	1		T486	5
values[116]	50	1			T516	2		T806	3		T486	4
values[117]	39	1			T516	3		T806	2		T486	3
values[118]	49	1			T516	7		T806	5		T486	3
values[119]	56	1			T516	8		T806	3		T486	6
values[120]	52	1			T516	1		T806	1		T486	1
values[121]	59	1			T806	4		T486	6		T816	1
values[122]	31	1			T806	2		T486	2		T816	3
values[123]	40	1			T806	1		T486	2		T816	6
values[124]	50	1			T806	2		T486	8		T816	3
values[125]	80	1			T806	3		T486	13		T816	14
values[126]	144	1			T806	2		T486	24		T816	49
values[127]	630	1			T806	31		T486	50		T816	91
values[128]	4650	1			T806	337		T486	18		T816	30