Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.19	95.55	94.14	95.45		94.94	97.53	99.52

Total tests in report: 2938

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.51	39.51	44.62	44.62	42.97	42.97	31.81	31.81			57.86	57.86	59.44	59.44	0.39	0.39	/workspace/coverage/default/58.chip_sw_all_escalation_resets.581617972
48.35	8.84	49.59	4.97	57.01	14.04	32.11	0.30			67.26	9.40	82.52	23.08	1.61	1.22	/workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.4292827630
54.48	6.13	62.36	12.77	65.51	8.51	36.02	3.91			78.84	11.58	82.52	0.00	1.61	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1398734889
59.50	5.03	74.25	11.88	67.96	2.44	43.32	7.30			79.63	0.80	82.52	0.00	9.34	7.73	/workspace/coverage/cover_reg_top/71.xbar_same_source.3609543852
64.42	4.92	74.25	0.00	68.09	0.13	43.32	0.00			79.65	0.02	82.52	0.00	38.70	29.36	/workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.2927949617
67.63	3.21	79.51	5.26	72.13	4.04	46.95	3.62			81.45	1.80	87.06	4.55	38.70	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1615086027
70.70	3.07	79.52	0.01	72.15	0.02	65.28	18.33			81.47	0.02	87.06	0.00	38.75	0.05	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1288682735
73.57	2.87	79.52	0.00	72.25	0.11	65.28	0.00			81.47	0.00	87.06	0.00	55.86	17.11	/workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.3919176401
75.55	1.98	79.52	0.00	72.26	0.01	65.28	0.00			81.47	0.00	87.06	0.00	67.70	11.84	/workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1576193684
77.26	1.71	82.19	2.67	75.87	3.61	65.49	0.21			85.23	3.76	87.06	0.00	67.70	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2945486290
78.83	1.57	82.29	0.11	75.89	0.02	74.45	8.95			85.24	0.01	87.41	0.35	67.70	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3575567310
80.36	1.53	83.82	1.53	77.18	1.29	75.54	1.10			86.59	1.35	91.26	3.85	67.75	0.05	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3764193148
81.79	1.43	86.02	2.19	79.97	2.79	77.09	1.55			88.58	2.00	91.26	0.00	67.81	0.06	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1183181130
83.10	1.31	86.02	0.00	80.11	0.15	77.09	0.00			88.58	0.00	91.26	0.00	75.51	7.71	/workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2866915262
84.15	1.06	87.28	1.27	81.23	1.12	80.15	3.05			89.27	0.69	91.26	0.00	75.71	0.20	/workspace/coverage/default/1.chip_jtag_csr_rw.2832170960
85.04	0.89	87.36	0.08	81.91	0.68	80.89	0.75			89.34	0.06	91.26	0.00	79.49	3.77	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.2713151924
85.87	0.83	88.09	0.72	82.11	0.19	80.91	0.01			89.53	0.19	95.10	3.85	79.49	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.633305521
86.69	0.82	88.09	0.00	82.22	0.11	80.91	0.00			89.56	0.03	95.10	0.00	84.24	4.76	/workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.1824256400
87.44	0.75	89.05	0.96	82.95	0.72	82.88	1.97			90.22	0.67	95.28	0.17	84.24	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.4066427756
88.11	0.68	90.30	1.25	83.98	1.04	83.46	0.58			91.42	1.19	95.28	0.00	84.24	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.1999974959
88.78	0.67	90.33	0.03	84.03	0.05	85.45	1.98			91.42	0.00	95.28	0.00	86.18	1.94	/workspace/coverage/default/1.chip_sw_alert_test.1429880943
89.41	0.62	91.49	1.16	85.10	1.07	86.08	0.63			92.29	0.88	95.28	0.00	86.18	0.00	/workspace/coverage/default/1.chip_sw_gpio_smoketest.3952308268
89.96	0.55	91.49	0.00	85.10	0.00	86.08	0.00			92.29	0.00	95.28	0.00	89.51	3.33	/workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.2432888242
90.43	0.47	92.70	1.21	85.45	0.35	86.46	0.37			92.49	0.20	95.98	0.70	89.51	0.00	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.369788808
90.87	0.44	92.70	0.00	85.93	0.48	86.46	0.00			92.51	0.02	95.98	0.00	91.66	2.15	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.741456472
91.27	0.39	92.71	0.01	85.93	0.01	88.81	2.36			92.51	0.00	95.98	0.00	91.66	0.00	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2537423093
91.64	0.37	92.72	0.01	88.05	2.12	88.81	0.00			92.51	0.00	95.98	0.00	91.74	0.08	/workspace/coverage/cover_reg_top/10.chip_tl_errors.3058422823
91.98	0.35	93.22	0.50	89.40	1.35	88.92	0.11			92.65	0.14	95.98	0.00	91.74	0.00	/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3628156295
92.32	0.33	93.22	0.00	89.45	0.05	88.92	0.00			92.65	0.00	95.98	0.00	93.68	1.94	/workspace/coverage/cover_reg_top/71.xbar_stress_all.3095539010
92.56	0.24	93.38	0.16	90.00	0.55	89.08	0.17			93.23	0.58	95.98	0.00	93.68	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.3869421965
92.79	0.23	93.38	0.00	90.08	0.08	89.08	0.00			93.24	0.01	95.98	0.00	94.98	1.30	/workspace/coverage/cover_reg_top/51.xbar_random_large_delays.3942161413
93.02	0.23	93.83	0.44	90.49	0.42	89.19	0.10			93.63	0.39	95.98	0.00	94.98	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.430577335
93.21	0.20	93.86	0.03	90.57	0.08	89.98	0.79			93.70	0.06	96.15	0.17	95.03	0.05	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.482241359
93.40	0.18	93.86	0.00	90.57	0.00	89.98	0.01			93.70	0.00	96.15	0.00	96.13	1.10	/workspace/coverage/cover_reg_top/71.xbar_access_same_device.2905169236
93.57	0.17	93.86	0.00	90.57	0.00	89.98	0.00			93.70	0.00	96.15	0.00	97.16	1.02	/workspace/coverage/cover_reg_top/2.xbar_access_same_device.1065923503
93.73	0.16	93.86	0.00	90.69	0.12	89.98	0.00			93.70	0.00	96.15	0.00	98.03	0.87	/workspace/coverage/cover_reg_top/58.xbar_stress_all.1694495300
93.89	0.16	93.87	0.01	91.11	0.43	90.01	0.02			94.17	0.48	96.15	0.00	98.03	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.4167925781
94.04	0.15	94.07	0.21	91.44	0.32	90.36	0.36			94.17	0.00	96.15	0.00	98.03	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2947894672
94.18	0.15	94.07	0.00	91.44	0.00	91.24	0.88			94.17	0.00	96.15	0.00	98.03	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3882767564
94.31	0.12	94.07	0.00	91.44	0.01	91.92	0.68			94.17	0.00	96.15	0.00	98.07	0.05	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2338211495
94.41	0.10	94.09	0.02	91.51	0.07	92.26	0.34			94.34	0.16	96.15	0.00	98.07	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.952615185
94.50	0.10	94.17	0.07	91.54	0.03	92.38	0.12			94.34	0.00	96.50	0.35	98.07	0.00	/workspace/coverage/default/1.chip_sw_power_virus.3399187434
94.58	0.08	94.17	0.00	91.55	0.01	92.88	0.50			94.34	0.00	96.50	0.00	98.07	0.00	/workspace/coverage/default/69.chip_sw_all_escalation_resets.3349354011
94.67	0.08	94.17	0.00	92.04	0.48	92.88	0.00			94.34	0.00	96.50	0.00	98.08	0.01	/workspace/coverage/cover_reg_top/27.chip_tl_errors.3512126180
94.75	0.08	94.21	0.04	92.11	0.08	93.14	0.27			94.41	0.07	96.50	0.00	98.10	0.01	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.923285837
94.82	0.07	94.42	0.21	92.25	0.14	93.14	0.00			94.51	0.10	96.50	0.00	98.10	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2524058953
94.87	0.05	94.42	0.00	92.28	0.03	93.43	0.29			94.51	0.00	96.50	0.00	98.10	0.00	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3114509203
94.93	0.05	94.46	0.04	92.32	0.03	93.45	0.02			94.54	0.03	96.68	0.17	98.11	0.01	/workspace/coverage/default/38.chip_sw_all_escalation_resets.4247401796
94.97	0.05	94.59	0.13	92.32	0.01	93.59	0.14			94.56	0.02	96.68	0.00	98.11	0.00	/workspace/coverage/default/4.chip_tap_straps_rma.1364502573
95.02	0.04	94.59	0.00	92.32	0.00	93.85	0.26			94.56	0.00	96.68	0.00	98.11	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.4221680884
95.06	0.04	94.61	0.02	92.36	0.04	93.85	0.00			94.57	0.02	96.85	0.17	98.12	0.01	/workspace/coverage/default/95.chip_sw_all_escalation_resets.3920037486
95.10	0.04	94.64	0.03	92.36	0.01	93.87	0.02			94.59	0.02	97.03	0.17	98.13	0.01	/workspace/coverage/default/47.chip_sw_all_escalation_resets.3321190852
95.14	0.04	94.65	0.01	92.46	0.10	93.98	0.11			94.60	0.01	97.03	0.00	98.13	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.1665803528
95.18	0.04	94.66	0.01	92.56	0.09	94.01	0.03			94.69	0.10	97.03	0.00	98.13	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.707084451
95.22	0.04	94.66	0.01	92.57	0.01	94.02	0.01			94.70	0.01	97.20	0.17	98.14	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.3690044151
95.25	0.04	94.67	0.01	92.58	0.01	94.03	0.01			94.71	0.01	97.38	0.17	98.16	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.890992363
95.29	0.04	94.67	0.00	92.58	0.00	94.06	0.04			94.71	0.00	97.55	0.17	98.16	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.4041657044
95.32	0.04	94.67	0.00	92.58	0.00	94.27	0.21			94.71	0.00	97.55	0.00	98.16	0.00	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2710872802
95.36	0.04	94.67	0.00	92.59	0.01	94.27	0.00			94.71	0.00	97.55	0.00	98.36	0.20	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.3742137676
95.39	0.03	94.67	0.00	92.74	0.15	94.27	0.00			94.73	0.02	97.55	0.00	98.39	0.04	/workspace/coverage/cover_reg_top/66.xbar_stress_all.1135046665
95.42	0.03	94.74	0.07	92.76	0.02	94.35	0.07			94.75	0.02	97.55	0.00	98.39	0.00	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1836490982
95.45	0.03	94.74	0.00	92.94	0.18	94.35	0.00			94.75	0.00	97.55	0.00	98.39	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.772154392
95.48	0.03	94.74	0.01	92.97	0.03	94.48	0.13			94.75	0.00	97.55	0.00	98.39	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4049303415
95.51	0.03	94.74	0.00	93.13	0.17	94.48	0.00			94.75	0.00	97.55	0.00	98.39	0.00	/workspace/coverage/cover_reg_top/7.chip_tl_errors.3046357742
95.54	0.03	94.82	0.07	93.16	0.03	94.49	0.01			94.80	0.05	97.55	0.00	98.39	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2174963063
95.56	0.02	94.82	0.00	93.16	0.00	94.63	0.14			94.80	0.00	97.55	0.00	98.39	0.00	/workspace/coverage/default/1.chip_sw_aes_masking_off.3929694284
95.58	0.02	94.82	0.00	93.18	0.02	94.63	0.00			94.80	0.00	97.55	0.00	98.51	0.12	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.4148542794
95.60	0.02	94.82	0.00	93.18	0.00	94.76	0.13			94.80	0.00	97.55	0.00	98.51	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.545442780
95.62	0.02	94.87	0.05	93.23	0.05	94.76	0.00			94.82	0.02	97.55	0.00	98.51	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2158435663
95.64	0.02	94.87	0.00	93.33	0.10	94.76	0.00			94.82	0.00	97.55	0.00	98.51	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.452698943
95.65	0.02	94.88	0.01	93.36	0.03	94.79	0.04			94.83	0.02	97.55	0.00	98.51	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2911617094
95.67	0.02	94.88	0.00	93.39	0.03	94.79	0.00			94.85	0.02	97.55	0.00	98.55	0.05	/workspace/coverage/cover_reg_top/98.xbar_stress_all.2317783332
95.69	0.02	94.88	0.00	93.44	0.05	94.79	0.00			94.89	0.04	97.55	0.00	98.55	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.4062339408
95.70	0.02	94.88	0.00	93.44	0.00	94.89	0.09			94.89	0.00	97.55	0.00	98.55	0.00	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3997595071
95.71	0.01	94.92	0.03	93.47	0.02	94.89	0.00			94.90	0.02	97.55	0.00	98.55	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.4218053991
95.73	0.01	94.92	0.00	93.48	0.01	94.89	0.00			94.90	0.00	97.55	0.00	98.61	0.06	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.2494330293
95.74	0.01	94.92	0.00	93.55	0.07	94.89	0.01			94.90	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2430300666
95.75	0.01	94.92	0.00	93.62	0.07	94.89	0.00			94.90	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.1165679490
95.76	0.01	94.92	0.00	93.67	0.06	94.89	0.00			94.90	0.00	97.55	0.00	98.63	0.01	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.2287138020
95.77	0.01	94.92	0.00	93.67	0.00	94.96	0.07			94.90	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2706839050
95.78	0.01	94.94	0.02	93.70	0.03	94.97	0.01			94.90	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.4091821226
95.79	0.01	94.96	0.02	93.71	0.01	94.98	0.01			94.92	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3066652057
95.80	0.01	94.96	0.00	93.72	0.01	94.98	0.00			94.92	0.00	97.55	0.00	98.66	0.04	/workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.3530205467
95.81	0.01	94.96	0.00	93.73	0.01	95.02	0.05			94.92	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.2419556230
95.81	0.01	94.96	0.01	93.75	0.02	95.04	0.01			94.92	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3941299902
95.82	0.01	94.96	0.00	93.75	0.00	95.08	0.04			94.92	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3541855713
95.83	0.01	94.96	0.00	93.75	0.00	95.12	0.04			94.92	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3231550411
95.84	0.01	94.96	0.00	93.78	0.03	95.12	0.00			94.92	0.00	97.55	0.00	98.67	0.01	/workspace/coverage/cover_reg_top/19.chip_tl_errors.1619585023
95.84	0.01	94.96	0.00	93.78	0.00	95.12	0.00			94.92	0.00	97.55	0.00	98.71	0.04	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.2711231620
95.85	0.01	94.96	0.00	93.78	0.00	95.12	0.00			94.92	0.00	97.55	0.00	98.74	0.04	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.2672571073
95.85	0.01	94.96	0.00	93.78	0.00	95.12	0.00			94.92	0.00	97.55	0.00	98.78	0.04	/workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.4027470113
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96.06	0.01	94.97	0.00	94.05	0.01	95.36	0.00			94.93	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx.522562587
96.07	0.01	94.97	0.00	94.06	0.01	95.36	0.00			94.93	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.938507668
96.07	0.01	94.97	0.00	94.07	0.01	95.36	0.00			94.93	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.174448377
96.07	0.01	94.98	0.01	94.07	0.00	95.37	0.01			94.93	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/10.chip_sw_all_escalation_resets.2997710685
96.07	0.01	94.98	0.00	94.07	0.00	95.38	0.01			94.93	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2060992660
96.07	0.01	94.98	0.00	94.07	0.00	95.39	0.01			94.93	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3383127005
96.07	0.01	94.98	0.00	94.07	0.00	95.40	0.01			94.93	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2786227872
96.08	0.01	94.98	0.00	94.07	0.01	95.40	0.01			94.93	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.4291561416
96.08	0.01	94.98	0.00	94.07	0.00	95.40	0.00			94.94	0.01	97.55	0.00	99.52	0.00	/workspace/coverage/default/2.chip_tap_straps_dev.4186713497
96.08	0.01	94.98	0.00	94.08	0.01	95.40	0.00			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/18.xbar_stress_all.1860677849
96.08	0.01	94.98	0.00	94.09	0.01	95.40	0.00			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.2579381236
96.08	0.01	94.98	0.00	94.10	0.01	95.40	0.00			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/1.chip_sw_gpio.448326316
96.08	0.01	94.98	0.00	94.10	0.00	95.41	0.01			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.373022380
96.08	0.01	94.98	0.00	94.10	0.00	95.41	0.01			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_flash_init.2651691663
96.08	0.01	94.98	0.00	94.10	0.00	95.42	0.01			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_hmac_oneshot.2332652393
96.08	0.01	94.98	0.00	94.10	0.00	95.42	0.01			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1675587067
96.08	0.01	94.98	0.00	94.10	0.00	95.43	0.01			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3300194276
96.08	0.01	94.98	0.00	94.10	0.00	95.43	0.01			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2651547800
96.09	0.01	94.98	0.00	94.10	0.00	95.43	0.01			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1086329949
96.09	0.01	94.98	0.00	94.10	0.01	95.43	0.00			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/12.chip_tl_errors.3471165524
96.09	0.01	94.98	0.00	94.10	0.01	95.43	0.00			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.4156006405
96.09	0.01	94.98	0.00	94.11	0.01	95.43	0.00			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.1883693551
96.09	0.01	94.98	0.00	94.11	0.01	95.43	0.00			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.2678593776
96.09	0.01	94.98	0.00	94.11	0.01	95.43	0.00			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.1615188972
96.09	0.01	94.98	0.00	94.12	0.01	95.43	0.00			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3829414097
96.09	0.01	94.98	0.00	94.12	0.01	95.43	0.00			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.1717789524
96.09	0.01	94.98	0.00	94.12	0.01	95.43	0.00			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.2111816478
96.09	0.01	94.98	0.00	94.13	0.01	95.43	0.00			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/86.xbar_error_random.1341159512
96.09	0.01	94.98	0.00	94.13	0.01	95.43	0.00			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.3229979392
96.09	0.01	94.98	0.00	94.13	0.01	95.43	0.00			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.4229669166
96.09	0.01	94.98	0.00	94.14	0.01	95.43	0.00			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.837495490
96.09	0.01	94.98	0.00	94.14	0.01	95.43	0.00			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2484551549
96.09	0.01	94.98	0.00	94.14	0.01	95.43	0.00			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3801454061
96.09	0.01	94.98	0.00	94.14	0.00	95.44	0.01			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.3496179521
96.09	0.01	94.98	0.00	94.14	0.00	95.44	0.01			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1222872057
96.10	0.01	94.98	0.00	94.14	0.00	95.44	0.01			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3044843713
96.10	0.01	94.98	0.00	94.14	0.00	95.45	0.01			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1411442630
96.10	0.01	94.98	0.00	94.14	0.00	95.45	0.01			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.360348296
96.10	0.01	94.98	0.00	94.14	0.00	95.45	0.01			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2821708579
96.10	0.01	94.98	0.00	94.14	0.00	95.45	0.01			94.94	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.4268414658

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1193030750
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1958909838
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3015910987
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.701251512
/workspace/coverage/cover_reg_top/0.chip_csr_rw.294218503
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.954028739
/workspace/coverage/cover_reg_top/0.chip_tl_errors.1542105672
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.469072026
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.201571969
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.188245845
/workspace/coverage/cover_reg_top/0.xbar_error_random.2397839673
/workspace/coverage/cover_reg_top/0.xbar_random.1548500408
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2216814393
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1166922413
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3416574195
/workspace/coverage/cover_reg_top/0.xbar_same_source.2699086733
/workspace/coverage/cover_reg_top/0.xbar_smoke.1773450559
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1432051112
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.4245057461
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1774207680
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3552361051
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2669253529
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.4190892192
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3395850855
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3153261407
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.431965353
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2377592439
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.997339110
/workspace/coverage/cover_reg_top/1.chip_csr_rw.950148718
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1928500879
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2079726768
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3700784434
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2983166632
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1962847613
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.455746020
/workspace/coverage/cover_reg_top/1.xbar_error_random.3710303983
/workspace/coverage/cover_reg_top/1.xbar_random.3887690176
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2932827070
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1033547320
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2685267298
/workspace/coverage/cover_reg_top/1.xbar_same_source.3818952017
/workspace/coverage/cover_reg_top/1.xbar_smoke.2955069833
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.149887238
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2030573855
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1596833071
/workspace/coverage/cover_reg_top/1.xbar_stress_all.304483949
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2463535232
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2034198124
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2812862548
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.70986569
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3894863377
/workspace/coverage/cover_reg_top/10.chip_csr_rw.4138507222
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3574140396
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.3177151924
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3320166454
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1906908030
/workspace/coverage/cover_reg_top/10.xbar_error_random.1377174502
/workspace/coverage/cover_reg_top/10.xbar_random.3407695826
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1905681349
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2695698170
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.2860350666
/workspace/coverage/cover_reg_top/10.xbar_same_source.1768820293
/workspace/coverage/cover_reg_top/10.xbar_smoke.1938798970
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.389539972
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.4138979436
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.391273471
/workspace/coverage/cover_reg_top/10.xbar_stress_all.711635669
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.4143199605
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3285272900
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.2840538917
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.250480940
/workspace/coverage/cover_reg_top/11.chip_csr_rw.4252036738
/workspace/coverage/cover_reg_top/11.chip_tl_errors.300392912
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.1474148049
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.246128079
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3689925098
/workspace/coverage/cover_reg_top/11.xbar_error_random.3844715679
/workspace/coverage/cover_reg_top/11.xbar_random.3796738830
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3516133347
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1519737388
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3410779236
/workspace/coverage/cover_reg_top/11.xbar_same_source.3937417426
/workspace/coverage/cover_reg_top/11.xbar_smoke.1647547933
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.3718101305
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.22396811
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1873763619
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3103989405
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.409498851
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3327099681
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1095515081
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2805491561
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.2342089495
/workspace/coverage/cover_reg_top/12.chip_csr_rw.2029293004
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3415846412
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3680475047
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.416505863
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1782919075
/workspace/coverage/cover_reg_top/12.xbar_error_random.3606324110
/workspace/coverage/cover_reg_top/12.xbar_random.3024472729
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3024888734
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3240586881
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1475345297
/workspace/coverage/cover_reg_top/12.xbar_same_source.63895789
/workspace/coverage/cover_reg_top/12.xbar_smoke.3008020079
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3595290703
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2024348756
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3651575410
/workspace/coverage/cover_reg_top/12.xbar_stress_all.3342804000
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2968572251
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.4115775811
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.4182595724
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3418581143
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.2337911552
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3707308377
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.4110121774
/workspace/coverage/cover_reg_top/13.chip_tl_errors.704978679
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3082061068
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.599232121
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1248957016
/workspace/coverage/cover_reg_top/13.xbar_error_random.2272247030
/workspace/coverage/cover_reg_top/13.xbar_random.1262566815
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1530392092
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2027533683
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.72365403
/workspace/coverage/cover_reg_top/13.xbar_same_source.3453764114
/workspace/coverage/cover_reg_top/13.xbar_smoke.1686160472
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.4255342863
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3371208770
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3698005885
/workspace/coverage/cover_reg_top/13.xbar_stress_all.1366547197
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3933739861
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.811207931
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2965361701
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.3695392243
/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.823349892
/workspace/coverage/cover_reg_top/14.chip_csr_rw.248563900
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.4049699552
/workspace/coverage/cover_reg_top/14.chip_tl_errors.1990367534
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.443481121
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3490891104
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.4029674367
/workspace/coverage/cover_reg_top/14.xbar_error_random.2095753637
/workspace/coverage/cover_reg_top/14.xbar_random.3659383325
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.239203447
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.4285629546
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.1671213825
/workspace/coverage/cover_reg_top/14.xbar_same_source.3181749715
/workspace/coverage/cover_reg_top/14.xbar_smoke.1987042553
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/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.636314234
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2823275493
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/workspace/coverage/default/2.chip_sw_spi_device_tpm.2090301912
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/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.4241593892
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2548879685
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2637164808
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3533115873
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2136117287
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1658123225
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.559944515
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.392086192
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.900580240
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2920761148
/workspace/coverage/default/2.chip_sw_uart_smoketest.1108396714
/workspace/coverage/default/2.chip_sw_uart_tx_rx.4271373712
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.850152319
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.677697863
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/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1016929436
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/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.619898052
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2051679950
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2472422286
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/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2320240386
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1425386985
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1403643558
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.101991532
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/workspace/coverage/default/32.chip_sw_all_escalation_resets.1479030984
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.326172272
/workspace/coverage/default/33.chip_sw_all_escalation_resets.3266071313
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1985615535
/workspace/coverage/default/35.chip_sw_all_escalation_resets.752721602
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3164517015
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1151309882
/workspace/coverage/default/39.chip_sw_all_escalation_resets.3845825196
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3504655156
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2086557195
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2593401809
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2571387448
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.451366170
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1278253391
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.294573917
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3767678290
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2439990559
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2862301356
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2031330077
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.272061773
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3317232659
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1577260611
/workspace/coverage/default/4.chip_tap_straps_dev.216772741
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/workspace/coverage/default/4.chip_tap_straps_testunlock0.1069589976
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3586239762
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2283854968
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2695444459
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2260755359
/workspace/coverage/default/42.chip_sw_all_escalation_resets.3426203888
/workspace/coverage/default/43.chip_sw_all_escalation_resets.2130817442
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1568002710
/workspace/coverage/default/45.chip_sw_all_escalation_resets.3890546600
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1938820204
/workspace/coverage/default/46.chip_sw_all_escalation_resets.1367687717
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1657576447
/workspace/coverage/default/48.chip_sw_all_escalation_resets.3275451792
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3436726556
/workspace/coverage/default/5.chip_sw_all_escalation_resets.3983287363
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1820306480
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.4033808952
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3631406336
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3620969615
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.602821502
/workspace/coverage/default/50.chip_sw_all_escalation_resets.2328288053
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.483324561
/workspace/coverage/default/52.chip_sw_all_escalation_resets.971548206
/workspace/coverage/default/53.chip_sw_all_escalation_resets.25134923
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.981736318
/workspace/coverage/default/54.chip_sw_all_escalation_resets.471464745
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3862455722
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3672019812
/workspace/coverage/default/56.chip_sw_all_escalation_resets.1668575535
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.231479705
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3355464318
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.879272884
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2322928427
/workspace/coverage/default/59.chip_sw_all_escalation_resets.2045214577
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.4200627550
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1464233600
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1888546457
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.829441414
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1608236992
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.392308829
/workspace/coverage/default/60.chip_sw_all_escalation_resets.4182338905
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3578769536
/workspace/coverage/default/61.chip_sw_all_escalation_resets.65768822
/workspace/coverage/default/62.chip_sw_all_escalation_resets.4234340233
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1451107341
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2671408820
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1510242854
/workspace/coverage/default/64.chip_sw_all_escalation_resets.4216759023
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1660196648
/workspace/coverage/default/65.chip_sw_all_escalation_resets.122102802
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1784221299
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2776847928
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2327260223
/workspace/coverage/default/68.chip_sw_all_escalation_resets.1478036446
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1333755788
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3346795575
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2617571139
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2696566513
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1726271328
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2846667835
/workspace/coverage/default/70.chip_sw_all_escalation_resets.449215478
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2844282805
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3917495853
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.632038328
/workspace/coverage/default/73.chip_sw_all_escalation_resets.3511221096
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1531167216
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1274996515
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3698412704
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1273145152
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2604306999
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2827939194
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1754071904
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2995965011
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1030841000
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1333650153
/workspace/coverage/default/79.chip_sw_all_escalation_resets.808920567
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3964635212
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3443054457
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.4164686150
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.538857163
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.454409183
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3914577989
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1482947107
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1622302048
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2313390419
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3767550464
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1815593254
/workspace/coverage/default/83.chip_sw_all_escalation_resets.565331990
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.652537153
/workspace/coverage/default/84.chip_sw_all_escalation_resets.217112743
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3748584845
/workspace/coverage/default/85.chip_sw_all_escalation_resets.566552404
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2450887815
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1598191206
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2137889394
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2404937105
/workspace/coverage/default/88.chip_sw_all_escalation_resets.2060230359
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.544108924
/workspace/coverage/default/89.chip_sw_all_escalation_resets.309945872
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4018350720
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1583975980
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3185943726
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1329783676
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2890808222
/workspace/coverage/default/90.chip_sw_all_escalation_resets.4249569254
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2528714428
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3422668799
/workspace/coverage/default/96.chip_sw_all_escalation_resets.2259058954
/workspace/coverage/default/97.chip_sw_all_escalation_resets.692387419
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1734829497
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1501032323
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3451733792
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.57717683
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3327233718
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.896871994
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2507404936
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2296039577
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.399556217
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2445630918

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Total test records in report: 2938

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.482241359			Aug 16 07:15:41 PM PDT 24	Aug 16 07:25:16 PM PDT 24	4148051320 ps
T2	/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.889530516			Aug 16 07:13:12 PM PDT 24	Aug 16 07:42:01 PM PDT 24	11566975444 ps
T3	/workspace/coverage/default/0.chip_sw_hmac_oneshot.2332652393			Aug 16 07:16:54 PM PDT 24	Aug 16 07:24:18 PM PDT 24	3296286798 ps
T4	/workspace/coverage/default/58.chip_sw_all_escalation_resets.581617972			Aug 16 07:42:30 PM PDT 24	Aug 16 07:51:52 PM PDT 24	4571315376 ps
T35	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.951898867			Aug 16 07:09:44 PM PDT 24	Aug 16 07:15:28 PM PDT 24	4824765548 ps
T83	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2710872802			Aug 16 07:28:48 PM PDT 24	Aug 16 07:35:26 PM PDT 24	4477815560 ps
T5	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1183181130			Aug 16 07:36:21 PM PDT 24	Aug 16 07:41:22 PM PDT 24	3368006600 ps
T6	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3841005244			Aug 16 07:08:52 PM PDT 24	Aug 16 07:20:07 PM PDT 24	5436708498 ps
T19	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.934872459			Aug 16 07:06:25 PM PDT 24	Aug 16 07:14:14 PM PDT 24	2979247412 ps
T7	/workspace/coverage/default/0.chip_sw_flash_init.2651691663			Aug 16 07:06:54 PM PDT 24	Aug 16 07:42:35 PM PDT 24	22891880800 ps
T64	/workspace/coverage/default/92.chip_sw_all_escalation_resets.637243397			Aug 16 07:40:50 PM PDT 24	Aug 16 07:48:22 PM PDT 24	5179191670 ps
T8	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.923285837			Aug 16 07:21:06 PM PDT 24	Aug 16 10:51:52 PM PDT 24	78171839521 ps
T150	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.829231492			Aug 16 07:22:52 PM PDT 24	Aug 16 07:27:19 PM PDT 24	2412824232 ps
T165	/workspace/coverage/default/0.chip_sival_flash_info_access.1967032558			Aug 16 07:07:24 PM PDT 24	Aug 16 07:12:59 PM PDT 24	3417176900 ps
T144	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1006505211			Aug 16 07:32:23 PM PDT 24	Aug 16 07:41:51 PM PDT 24	4209587028 ps
T123	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1288682735			Aug 16 07:27:39 PM PDT 24	Aug 16 08:20:38 PM PDT 24	15310843398 ps
T107	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2786227872			Aug 16 07:14:36 PM PDT 24	Aug 16 07:24:54 PM PDT 24	19154097902 ps
T119	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3199338083			Aug 16 07:17:49 PM PDT 24	Aug 16 07:26:07 PM PDT 24	6394836516 ps
T13	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3331889142			Aug 16 07:22:05 PM PDT 24	Aug 16 07:26:55 PM PDT 24	3056180332 ps
T632	/workspace/coverage/default/1.chip_sw_aes_masking_off.3929694284			Aug 16 07:15:24 PM PDT 24	Aug 16 07:21:04 PM PDT 24	3294964682 ps
T120	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1298023884			Aug 16 07:24:51 PM PDT 24	Aug 16 07:33:48 PM PDT 24	5521208076 ps
T174	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1998289089			Aug 16 07:18:23 PM PDT 24	Aug 16 07:29:30 PM PDT 24	5404639416 ps
T111	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2537423093			Aug 16 07:27:14 PM PDT 24	Aug 16 07:41:18 PM PDT 24	6522979326 ps
T9	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.952615185			Aug 16 07:07:34 PM PDT 24	Aug 16 07:10:09 PM PDT 24	3023536580 ps
T443	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1487031387			Aug 16 07:17:30 PM PDT 24	Aug 16 07:21:05 PM PDT 24	2722623072 ps
T323	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.454771981			Aug 16 07:28:08 PM PDT 24	Aug 16 07:40:49 PM PDT 24	5096301090 ps
T860	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2167209564			Aug 16 07:16:40 PM PDT 24	Aug 16 07:21:46 PM PDT 24	6111946174 ps
T861	/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.4280634130			Aug 16 07:08:22 PM PDT 24	Aug 16 08:39:08 PM PDT 24	26988162212 ps
T245	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.3009880624			Aug 16 07:14:30 PM PDT 24	Aug 16 07:23:21 PM PDT 24	4045229828 ps
T362	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.1313081574			Aug 16 07:34:58 PM PDT 24	Aug 16 07:42:06 PM PDT 24	4207719944 ps
T49	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.3344010729			Aug 16 07:17:30 PM PDT 24	Aug 16 07:26:32 PM PDT 24	6266817966 ps
T663	/workspace/coverage/default/2.chip_sw_aes_smoketest.1517719306			Aug 16 07:30:27 PM PDT 24	Aug 16 07:34:30 PM PDT 24	3626639624 ps
T209	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.4019455715			Aug 16 07:14:45 PM PDT 24	Aug 16 07:18:35 PM PDT 24	2666795982 ps
T256	/workspace/coverage/default/2.chip_plic_all_irqs_0.1398734889			Aug 16 07:27:49 PM PDT 24	Aug 16 07:47:27 PM PDT 24	5719529864 ps
T82	/workspace/coverage/default/0.chip_sw_usbdev_vbus.2107733407			Aug 16 07:06:04 PM PDT 24	Aug 16 07:10:38 PM PDT 24	2681398464 ps
T156	/workspace/coverage/default/4.chip_sw_all_escalation_resets.2086557195			Aug 16 07:33:13 PM PDT 24	Aug 16 07:43:05 PM PDT 24	5410664604 ps
T400	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2169967882			Aug 16 07:38:07 PM PDT 24	Aug 16 07:44:37 PM PDT 24	3731242172 ps
T16	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1577260611			Aug 16 07:31:22 PM PDT 24	Aug 16 07:44:59 PM PDT 24	4866334580 ps
T352	/workspace/coverage/default/36.chip_sw_all_escalation_resets.1364581856			Aug 16 07:41:39 PM PDT 24	Aug 16 07:52:57 PM PDT 24	6037324688 ps
T862	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.4047075268			Aug 16 07:17:04 PM PDT 24	Aug 16 07:23:56 PM PDT 24	4628156526 ps
T671	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.205623869			Aug 16 07:36:12 PM PDT 24	Aug 16 07:41:55 PM PDT 24	3489480504 ps
T664	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3917495853			Aug 16 07:39:55 PM PDT 24	Aug 16 07:44:21 PM PDT 24	3438027968 ps
T863	/workspace/coverage/default/2.chip_sw_csrng_smoketest.4193855453			Aug 16 07:31:54 PM PDT 24	Aug 16 07:35:21 PM PDT 24	2195136240 ps
T50	/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.373022380			Aug 16 07:07:19 PM PDT 24	Aug 16 10:16:30 PM PDT 24	59454810657 ps
T155	/workspace/coverage/default/27.chip_sw_all_escalation_resets.348891704			Aug 16 07:36:36 PM PDT 24	Aug 16 07:44:14 PM PDT 24	4534146646 ps
T166	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3372930699			Aug 16 07:13:47 PM PDT 24	Aug 16 07:25:04 PM PDT 24	4770044576 ps
T121	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1222872057			Aug 16 07:07:22 PM PDT 24	Aug 16 07:15:05 PM PDT 24	2998222454 ps
T213	/workspace/coverage/default/1.chip_sw_pattgen_ios.4063366704			Aug 16 07:11:48 PM PDT 24	Aug 16 07:16:35 PM PDT 24	2811511848 ps
T395	/workspace/coverage/default/2.chip_sw_hmac_oneshot.533235184			Aug 16 07:26:28 PM PDT 24	Aug 16 07:33:11 PM PDT 24	3404275036 ps
T371	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.939204505			Aug 16 07:35:45 PM PDT 24	Aug 16 07:41:32 PM PDT 24	3337086506 ps
T375	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2528460223			Aug 16 07:38:08 PM PDT 24	Aug 16 07:44:35 PM PDT 24	3846741096 ps
T210	/workspace/coverage/default/54.chip_sw_all_escalation_resets.471464745			Aug 16 07:37:51 PM PDT 24	Aug 16 07:45:49 PM PDT 24	4820890218 ps
T242	/workspace/coverage/default/47.chip_sw_all_escalation_resets.3321190852			Aug 16 07:37:28 PM PDT 24	Aug 16 07:46:43 PM PDT 24	5987131482 ps
T268	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3697280157			Aug 16 07:08:33 PM PDT 24	Aug 16 07:14:45 PM PDT 24	3321727016 ps
T122	/workspace/coverage/default/2.chip_sw_edn_boot_mode.2278256255			Aug 16 07:26:22 PM PDT 24	Aug 16 07:34:49 PM PDT 24	3501563158 ps
T269	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3888684753			Aug 16 07:26:27 PM PDT 24	Aug 16 07:32:36 PM PDT 24	3918726520 ps
T270	/workspace/coverage/default/1.chip_sw_kmac_idle.1894871284			Aug 16 07:16:05 PM PDT 24	Aug 16 07:21:03 PM PDT 24	2783223176 ps
T271	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3672019812			Aug 16 07:37:17 PM PDT 24	Aug 16 07:44:39 PM PDT 24	3424557128 ps
T63	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1994720637			Aug 16 07:23:35 PM PDT 24	Aug 16 07:26:08 PM PDT 24	3166399799 ps
T125	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2947894672			Aug 16 07:20:42 PM PDT 24	Aug 16 07:29:05 PM PDT 24	5366740968 ps
T68	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1538050385			Aug 16 07:19:28 PM PDT 24	Aug 16 07:30:20 PM PDT 24	4988474496 ps
T272	/workspace/coverage/default/0.chip_sw_aes_idle.180142767			Aug 16 07:07:15 PM PDT 24	Aug 16 07:13:07 PM PDT 24	3193790168 ps
T219	/workspace/coverage/default/97.chip_sw_all_escalation_resets.692387419			Aug 16 07:40:47 PM PDT 24	Aug 16 07:50:09 PM PDT 24	5685787684 ps
T47	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.730590379			Aug 16 07:17:18 PM PDT 24	Aug 16 08:12:44 PM PDT 24	14860163180 ps
T383	/workspace/coverage/default/0.chip_sw_kmac_app_rom.2230790120			Aug 16 07:08:24 PM PDT 24	Aug 16 07:13:33 PM PDT 24	2510955056 ps
T20	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3318510916			Aug 16 07:08:46 PM PDT 24	Aug 16 07:16:12 PM PDT 24	7675233272 ps
T97	/workspace/coverage/default/2.chip_sw_uart_tx_rx.4271373712			Aug 16 07:21:52 PM PDT 24	Aug 16 07:33:04 PM PDT 24	4907313960 ps
T98	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1333650153			Aug 16 07:39:21 PM PDT 24	Aug 16 07:45:01 PM PDT 24	3594239784 ps
T69	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.44072477			Aug 16 07:11:36 PM PDT 24	Aug 16 07:21:47 PM PDT 24	6856800242 ps
T99	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.762084372			Aug 16 07:34:33 PM PDT 24	Aug 16 07:54:42 PM PDT 24	8713624272 ps
T100	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2241663846			Aug 16 07:07:28 PM PDT 24	Aug 16 07:27:40 PM PDT 24	5942692350 ps
T17	/workspace/coverage/default/1.chip_sw_gpio_smoketest.3952308268			Aug 16 07:21:55 PM PDT 24	Aug 16 07:26:18 PM PDT 24	2520306238 ps
T101	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1963811304			Aug 16 07:15:56 PM PDT 24	Aug 16 07:20:12 PM PDT 24	3129499007 ps
T102	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2890808222			Aug 16 07:34:08 PM PDT 24	Aug 16 07:54:17 PM PDT 24	8890579978 ps
T75	/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3562416704			Aug 16 07:12:16 PM PDT 24	Aug 16 07:57:56 PM PDT 24	32280721766 ps
T243	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3206973857			Aug 16 07:10:45 PM PDT 24	Aug 16 07:22:57 PM PDT 24	6597628488 ps
T534	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.4010612514			Aug 16 07:17:24 PM PDT 24	Aug 16 07:26:56 PM PDT 24	6385354990 ps
T176	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.633305521			Aug 16 07:10:34 PM PDT 24	Aug 16 07:16:52 PM PDT 24	3236665032 ps
T306	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.1636886733			Aug 16 07:15:03 PM PDT 24	Aug 16 07:20:46 PM PDT 24	3110290636 ps
T307	/workspace/coverage/default/38.chip_sw_all_escalation_resets.4247401796			Aug 16 07:35:49 PM PDT 24	Aug 16 07:46:25 PM PDT 24	5319714980 ps
T308	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3663343984			Aug 16 07:15:45 PM PDT 24	Aug 16 07:20:38 PM PDT 24	3311325951 ps
T309	/workspace/coverage/default/76.chip_sw_all_escalation_resets.2827939194			Aug 16 07:39:10 PM PDT 24	Aug 16 07:47:49 PM PDT 24	4610940618 ps
T55	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2524058953			Aug 16 07:06:29 PM PDT 24	Aug 16 07:11:32 PM PDT 24	4039102350 ps
T78	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2338211495			Aug 16 07:15:01 PM PDT 24	Aug 16 07:35:57 PM PDT 24	13203379968 ps
T48	/workspace/coverage/default/1.rom_e2e_asm_init_rma.2837738020			Aug 16 07:26:04 PM PDT 24	Aug 16 08:29:21 PM PDT 24	14979650250 ps
T310	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.864141885			Aug 16 07:23:01 PM PDT 24	Aug 16 07:29:11 PM PDT 24	3505197416 ps
T139	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2716063600			Aug 16 07:18:45 PM PDT 24	Aug 16 07:24:38 PM PDT 24	4768984536 ps
T190	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.179760099			Aug 16 07:27:48 PM PDT 24	Aug 16 07:35:37 PM PDT 24	4762513040 ps
T397	/workspace/coverage/default/1.chip_sw_kmac_app_rom.4148953742			Aug 16 07:15:48 PM PDT 24	Aug 16 07:19:35 PM PDT 24	3132493776 ps
T124	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2190773278			Aug 16 07:06:54 PM PDT 24	Aug 16 07:13:25 PM PDT 24	7506047357 ps
T403	/workspace/coverage/default/0.chip_sw_edn_sw_mode.4209517206			Aug 16 07:08:56 PM PDT 24	Aug 16 07:33:44 PM PDT 24	6589424502 ps
T404	/workspace/coverage/default/0.chip_sw_csrng_smoketest.2469934329			Aug 16 07:12:25 PM PDT 24	Aug 16 07:15:51 PM PDT 24	3328944470 ps
T431	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2898799026			Aug 16 07:12:24 PM PDT 24	Aug 16 07:15:57 PM PDT 24	2605137640 ps
T18	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2031330077			Aug 16 07:32:28 PM PDT 24	Aug 16 07:48:08 PM PDT 24	9254152279 ps
T317	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1726271328			Aug 16 07:34:22 PM PDT 24	Aug 16 08:14:17 PM PDT 24	12678018834 ps
T432	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.850271864			Aug 16 07:12:14 PM PDT 24	Aug 16 07:31:22 PM PDT 24	6489229288 ps
T146	/workspace/coverage/default/2.chip_sw_otbn_smoketest.3929785224			Aug 16 07:31:24 PM PDT 24	Aug 16 07:59:14 PM PDT 24	9893773408 ps
T21	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1638203087			Aug 16 07:21:05 PM PDT 24	Aug 16 07:25:39 PM PDT 24	5178860040 ps
T532	/workspace/coverage/default/40.chip_sw_all_escalation_resets.4202026108			Aug 16 07:36:38 PM PDT 24	Aug 16 07:44:18 PM PDT 24	4141940824 ps
T214	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3412495908			Aug 16 07:08:52 PM PDT 24	Aug 16 07:35:41 PM PDT 24	8856227752 ps
T65	/workspace/coverage/default/4.chip_tap_straps_rma.1364502573			Aug 16 07:31:23 PM PDT 24	Aug 16 07:36:25 PM PDT 24	4019550404 ps
T864	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2505245385			Aug 16 07:22:01 PM PDT 24	Aug 16 07:25:22 PM PDT 24	3348008992 ps
T865	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1659324754			Aug 16 07:20:26 PM PDT 24	Aug 16 07:28:15 PM PDT 24	5311056744 ps
T866	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2469169527			Aug 16 07:35:32 PM PDT 24	Aug 16 07:43:49 PM PDT 24	3917972680 ps
T665	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.400363025			Aug 16 07:36:32 PM PDT 24	Aug 16 07:42:21 PM PDT 24	3330723416 ps
T162	/workspace/coverage/default/69.chip_sw_all_escalation_resets.3349354011			Aug 16 07:38:47 PM PDT 24	Aug 16 07:49:41 PM PDT 24	5362329944 ps
T44	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.4066427756			Aug 16 07:14:31 PM PDT 24	Aug 16 08:10:37 PM PDT 24	14161065132 ps
T867	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.4186193857			Aug 16 07:28:56 PM PDT 24	Aug 16 07:32:07 PM PDT 24	2811667271 ps
T260	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2759760645			Aug 16 07:31:01 PM PDT 24	Aug 16 09:04:32 PM PDT 24	25248158624 ps
T154	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.858565931			Aug 16 07:13:11 PM PDT 24	Aug 16 10:45:34 PM PDT 24	254612426008 ps
T113	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.696008421			Aug 16 07:17:26 PM PDT 24	Aug 16 07:28:41 PM PDT 24	4984012243 ps
T114	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3575567310			Aug 16 07:08:40 PM PDT 24	Aug 16 08:45:34 PM PDT 24	48504993958 ps
T257	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1411442630			Aug 16 07:08:05 PM PDT 24	Aug 16 07:45:38 PM PDT 24	14335923053 ps
T380	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.4174650737			Aug 16 07:35:49 PM PDT 24	Aug 16 07:42:48 PM PDT 24	3689155372 ps
T718	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.161213526			Aug 16 07:34:13 PM PDT 24	Aug 16 07:38:58 PM PDT 24	3187162844 ps
T258	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.370988377			Aug 16 07:13:25 PM PDT 24	Aug 16 07:24:01 PM PDT 24	9070467810 ps
T76	/workspace/coverage/default/1.chip_jtag_mem_access.3043620014			Aug 16 07:10:40 PM PDT 24	Aug 16 07:38:22 PM PDT 24	13520926865 ps
T387	/workspace/coverage/default/32.chip_sw_all_escalation_resets.1479030984			Aug 16 07:34:56 PM PDT 24	Aug 16 07:42:55 PM PDT 24	4393186360 ps
T533	/workspace/coverage/default/3.chip_sw_all_escalation_resets.637269806			Aug 16 07:31:46 PM PDT 24	Aug 16 07:41:01 PM PDT 24	5274393288 ps
T241	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.451366170			Aug 16 07:31:26 PM PDT 24	Aug 16 07:44:12 PM PDT 24	6302040260 ps
T465	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2832194749			Aug 16 07:09:48 PM PDT 24	Aug 16 07:29:54 PM PDT 24	6761838120 ps
T868	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1363241314			Aug 16 07:06:22 PM PDT 24	Aug 16 07:17:37 PM PDT 24	4410598664 ps
T222	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3309573567			Aug 16 07:36:34 PM PDT 24	Aug 16 07:44:06 PM PDT 24	3761963458 ps
T172	/workspace/coverage/default/1.chip_sw_flash_init.1273775832			Aug 16 07:11:40 PM PDT 24	Aug 16 07:53:22 PM PDT 24	20220406935 ps
T869	/workspace/coverage/default/1.chip_sw_hmac_multistream.3000011995			Aug 16 07:15:37 PM PDT 24	Aug 16 07:49:41 PM PDT 24	8963844616 ps
T870	/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3172090185			Aug 16 07:09:59 PM PDT 24	Aug 16 07:13:16 PM PDT 24	2869017236 ps
T217	/workspace/coverage/default/3.chip_tap_straps_prod.1022732679			Aug 16 07:31:20 PM PDT 24	Aug 16 07:33:58 PM PDT 24	2302477723 ps
T394	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.4164686150			Aug 16 07:36:49 PM PDT 24	Aug 16 08:45:01 PM PDT 24	22651439352 ps
T871	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3540656255			Aug 16 07:08:51 PM PDT 24	Aug 16 07:20:57 PM PDT 24	4740030568 ps
T108	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.2419556230			Aug 16 07:19:44 PM PDT 24	Aug 16 08:28:34 PM PDT 24	27312227027 ps
T744	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3346795575			Aug 16 07:34:27 PM PDT 24	Aug 16 07:40:48 PM PDT 24	3099271160 ps
T326	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3114509203			Aug 16 07:25:57 PM PDT 24	Aug 16 07:52:15 PM PDT 24	6891743528 ps
T259	/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.259338277			Aug 16 07:10:58 PM PDT 24	Aug 16 07:48:42 PM PDT 24	11192704349 ps
T173	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2242679466			Aug 16 07:12:08 PM PDT 24	Aug 16 07:14:49 PM PDT 24	4076826768 ps
T56	/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.3501779412			Aug 16 07:14:38 PM PDT 24	Aug 16 07:19:47 PM PDT 24	3109782710 ps
T713	/workspace/coverage/default/43.chip_sw_all_escalation_resets.2130817442			Aug 16 07:37:03 PM PDT 24	Aug 16 07:47:39 PM PDT 24	6600084240 ps
T457	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2115605482			Aug 16 07:27:56 PM PDT 24	Aug 16 07:33:09 PM PDT 24	3162201664 ps
T38	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.900580240			Aug 16 07:25:53 PM PDT 24	Aug 16 07:35:00 PM PDT 24	5003441998 ps
T381	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.4220967762			Aug 16 07:14:36 PM PDT 24	Aug 16 08:25:31 PM PDT 24	15377747720 ps
T872	/workspace/coverage/default/0.chip_sw_hmac_smoketest.3867156627			Aug 16 07:16:03 PM PDT 24	Aug 16 07:22:08 PM PDT 24	3216315376 ps
T873	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2840560479			Aug 16 07:08:52 PM PDT 24	Aug 16 07:20:19 PM PDT 24	5306870744 ps
T234	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.937548415			Aug 16 07:26:51 PM PDT 24	Aug 16 07:43:46 PM PDT 24	7724649016 ps
T466	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3236296359			Aug 16 07:15:29 PM PDT 24	Aug 16 07:35:14 PM PDT 24	7030533953 ps
T22	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3764193148			Aug 16 07:28:34 PM PDT 24	Aug 16 07:51:08 PM PDT 24	20393444832 ps
T168	/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2985350904			Aug 16 07:33:33 PM PDT 24	Aug 16 07:52:43 PM PDT 24	9909348731 ps
T79	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.2707803303			Aug 16 07:11:31 PM PDT 24	Aug 16 07:16:33 PM PDT 24	3692801516 ps
T706	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1541823052			Aug 16 07:38:13 PM PDT 24	Aug 16 07:45:59 PM PDT 24	3445097300 ps
T353	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3516546177			Aug 16 07:08:03 PM PDT 24	Aug 16 07:20:52 PM PDT 24	5155029260 ps
T80	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.2076287506			Aug 16 07:17:48 PM PDT 24	Aug 16 07:21:59 PM PDT 24	3095553717 ps
T382	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2649102649			Aug 16 07:16:25 PM PDT 24	Aug 16 08:21:54 PM PDT 24	15811871048 ps
T115	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1464193669			Aug 16 07:16:56 PM PDT 24	Aug 16 07:27:59 PM PDT 24	3614598360 ps
T458	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2811470779			Aug 16 07:26:17 PM PDT 24	Aug 16 07:30:41 PM PDT 24	2888736108 ps
T14	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.369788808			Aug 16 07:24:13 PM PDT 24	Aug 16 07:37:04 PM PDT 24	6056864381 ps
T874	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3524709977			Aug 16 07:14:28 PM PDT 24	Aug 16 07:22:56 PM PDT 24	4657660744 ps
T651	/workspace/coverage/default/39.chip_sw_all_escalation_resets.3845825196			Aug 16 07:36:27 PM PDT 24	Aug 16 07:45:52 PM PDT 24	5027869412 ps
T339	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3100634606			Aug 16 07:23:20 PM PDT 24	Aug 16 07:32:04 PM PDT 24	4198158646 ps
T875	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.10971432			Aug 16 07:27:31 PM PDT 24	Aug 16 07:34:55 PM PDT 24	5515953352 ps
T876	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2512645096			Aug 16 07:13:31 PM PDT 24	Aug 16 07:17:23 PM PDT 24	3425531868 ps
T62	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2885222719			Aug 16 07:09:11 PM PDT 24	Aug 16 07:42:42 PM PDT 24	22986871732 ps
T81	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1526771584			Aug 16 07:26:23 PM PDT 24	Aug 16 07:44:17 PM PDT 24	8996870792 ps
T729	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2327260223			Aug 16 07:39:46 PM PDT 24	Aug 16 07:46:17 PM PDT 24	3405682788 ps
T215	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.4015622407			Aug 16 07:22:09 PM PDT 24	Aug 16 07:44:10 PM PDT 24	8648680116 ps
T877	/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.905513718			Aug 16 07:24:13 PM PDT 24	Aug 16 07:32:56 PM PDT 24	7579996790 ps
T878	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1864078239			Aug 16 07:07:34 PM PDT 24	Aug 16 07:12:22 PM PDT 24	2731522687 ps
T879	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.879590096			Aug 16 07:34:02 PM PDT 24	Aug 16 07:37:50 PM PDT 24	3428146829 ps
T686	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3505770584			Aug 16 07:25:28 PM PDT 24	Aug 16 07:31:46 PM PDT 24	3664294528 ps
T66	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2877954672			Aug 16 07:30:24 PM PDT 24	Aug 16 07:41:51 PM PDT 24	6823594963 ps
T200	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1479441807			Aug 16 07:14:44 PM PDT 24	Aug 16 10:48:10 PM PDT 24	78566004320 ps
T674	/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1853111215			Aug 16 07:13:57 PM PDT 24	Aug 16 07:35:31 PM PDT 24	7789086960 ps
T23	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1836490982			Aug 16 07:25:33 PM PDT 24	Aug 16 08:11:08 PM PDT 24	20078170459 ps
T698	/workspace/coverage/default/18.chip_sw_all_escalation_resets.903402536			Aug 16 07:36:29 PM PDT 24	Aug 16 07:47:33 PM PDT 24	6008661164 ps
T880	/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3502763394			Aug 16 07:30:14 PM PDT 24	Aug 16 07:37:12 PM PDT 24	3650439208 ps
T881	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3568878335			Aug 16 07:17:06 PM PDT 24	Aug 16 08:22:05 PM PDT 24	14878551962 ps
T313	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.829441414			Aug 16 07:32:29 PM PDT 24	Aug 16 07:47:10 PM PDT 24	12441177457 ps
T675	/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.1916343762			Aug 16 07:30:58 PM PDT 24	Aug 16 07:53:33 PM PDT 24	7747832092 ps
T882	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3320024625			Aug 16 07:26:00 PM PDT 24	Aug 16 07:36:02 PM PDT 24	7314673820 ps
T95	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.494580249			Aug 16 07:12:12 PM PDT 24	Aug 16 07:41:31 PM PDT 24	22403202496 ps
T273	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1316734690			Aug 16 07:07:55 PM PDT 24	Aug 16 07:10:26 PM PDT 24	3108692213 ps
T702	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2406758304			Aug 16 07:26:20 PM PDT 24	Aug 16 10:45:58 PM PDT 24	255558809698 ps
T112	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4221216170			Aug 16 07:29:39 PM PDT 24	Aug 16 07:55:08 PM PDT 24	11202995540 ps
T708	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.3978807075			Aug 16 07:21:32 PM PDT 24	Aug 16 07:33:53 PM PDT 24	4825916260 ps
T883	/workspace/coverage/default/1.rom_e2e_asm_init_dev.4158819862			Aug 16 07:26:58 PM PDT 24	Aug 16 08:27:15 PM PDT 24	15289386047 ps
T28	/workspace/coverage/default/1.chip_sw_gpio.448326316			Aug 16 07:20:54 PM PDT 24	Aug 16 07:28:57 PM PDT 24	3427862475 ps
T884	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1404199142			Aug 16 07:16:37 PM PDT 24	Aug 16 07:47:24 PM PDT 24	21571728125 ps
T885	/workspace/coverage/default/1.rom_e2e_smoke.3811526211			Aug 16 07:24:44 PM PDT 24	Aug 16 08:27:59 PM PDT 24	14586329470 ps
T145	/workspace/coverage/default/0.chip_sw_power_sleep_load.940799384			Aug 16 07:10:39 PM PDT 24	Aug 16 07:19:37 PM PDT 24	9929088000 ps
T886	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2120553318			Aug 16 07:27:28 PM PDT 24	Aug 16 07:31:43 PM PDT 24	2994427100 ps
T887	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2945103003			Aug 16 07:19:13 PM PDT 24	Aug 16 07:26:46 PM PDT 24	5046945380 ps
T888	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.2733916447			Aug 16 07:08:11 PM PDT 24	Aug 16 07:17:28 PM PDT 24	6917286150 ps
T116	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4049303415			Aug 16 07:11:44 PM PDT 24	Aug 16 07:39:57 PM PDT 24	13724393727 ps
T147	/workspace/coverage/default/1.chip_sw_otbn_smoketest.2356024211			Aug 16 07:21:21 PM PDT 24	Aug 16 07:44:35 PM PDT 24	6421858348 ps
T634	/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2571387448			Aug 16 07:33:04 PM PDT 24	Aug 16 08:22:07 PM PDT 24	11961811352 ps
T889	/workspace/coverage/default/2.rom_e2e_static_critical.3659474401			Aug 16 07:35:47 PM PDT 24	Aug 16 08:34:41 PM PDT 24	16978287186 ps
T347	/workspace/coverage/default/1.chip_sival_flash_info_access.2617431373			Aug 16 07:12:49 PM PDT 24	Aug 16 07:18:03 PM PDT 24	3124313966 ps
T140	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.839004521			Aug 16 07:27:43 PM PDT 24	Aug 16 07:33:01 PM PDT 24	2831026056 ps
T890	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1471097685			Aug 16 07:28:57 PM PDT 24	Aug 16 07:38:29 PM PDT 24	5848836408 ps
T29	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.4062339408			Aug 16 07:06:27 PM PDT 24	Aug 16 07:11:45 PM PDT 24	3527793328 ps
T230	/workspace/coverage/default/2.rom_keymgr_functest.3629346318			Aug 16 07:30:35 PM PDT 24	Aug 16 07:40:56 PM PDT 24	4520300680 ps
T218	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.88007947			Aug 16 07:21:02 PM PDT 24	Aug 16 07:52:41 PM PDT 24	9575205885 ps
T244	/workspace/coverage/default/20.chip_sw_all_escalation_resets.1246304092			Aug 16 07:34:33 PM PDT 24	Aug 16 07:45:37 PM PDT 24	5798543506 ps
T335	/workspace/coverage/default/2.chip_sw_otbn_randomness.1561547079			Aug 16 07:25:03 PM PDT 24	Aug 16 07:41:50 PM PDT 24	5805407272 ps
T149	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1866308393			Aug 16 07:22:43 PM PDT 24	Aug 16 10:21:48 PM PDT 24	60255594468 ps
T45	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.509551656			Aug 16 07:14:30 PM PDT 24	Aug 16 08:16:24 PM PDT 24	15490839350 ps
T891	/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2031292954			Aug 16 07:07:27 PM PDT 24	Aug 16 07:12:07 PM PDT 24	2291376337 ps
T117	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3201267039			Aug 16 07:17:06 PM PDT 24	Aug 16 07:27:55 PM PDT 24	4975659386 ps
T160	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3541855713			Aug 16 07:06:17 PM PDT 24	Aug 16 08:34:15 PM PDT 24	50779073444 ps
T212	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3748456107			Aug 16 07:13:13 PM PDT 24	Aug 16 07:25:10 PM PDT 24	4336797280 ps
T177	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2595582834			Aug 16 07:20:21 PM PDT 24	Aug 16 07:24:27 PM PDT 24	2851805192 ps
T46	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2252780853			Aug 16 07:17:24 PM PDT 24	Aug 16 08:47:22 PM PDT 24	23151699013 ps
T892	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1871846096			Aug 16 07:16:47 PM PDT 24	Aug 16 08:23:43 PM PDT 24	14439516055 ps
T363	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.82218798			Aug 16 07:08:49 PM PDT 24	Aug 16 07:32:11 PM PDT 24	13429434870 ps
T329	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.454409183			Aug 16 07:33:31 PM PDT 24	Aug 16 08:25:23 PM PDT 24	13450807904 ps
T688	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1030841000			Aug 16 07:40:17 PM PDT 24	Aug 16 07:45:30 PM PDT 24	3554275152 ps
T893	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.4248705293			Aug 16 07:07:32 PM PDT 24	Aug 16 07:18:02 PM PDT 24	7508969204 ps
T894	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1461239042			Aug 16 07:15:33 PM PDT 24	Aug 16 07:18:27 PM PDT 24	2110996916 ps
T70	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2911617094			Aug 16 07:06:37 PM PDT 24	Aug 16 07:14:19 PM PDT 24	3480043400 ps
T895	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2125770951			Aug 16 07:15:07 PM PDT 24	Aug 16 07:23:38 PM PDT 24	7279010175 ps
T724	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2450887815			Aug 16 07:40:47 PM PDT 24	Aug 16 07:46:55 PM PDT 24	3778571158 ps
T336	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1204583172			Aug 16 07:22:11 PM PDT 24	Aug 16 07:25:57 PM PDT 24	2270462456 ps
T24	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3413859638			Aug 16 07:08:09 PM PDT 24	Aug 16 08:02:56 PM PDT 24	20634037289 ps
T351	/workspace/coverage/default/0.chip_sw_pattgen_ios.3681739911			Aug 16 07:05:24 PM PDT 24	Aug 16 07:08:51 PM PDT 24	2344904122 ps
T896	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3757140094			Aug 16 07:34:51 PM PDT 24	Aug 16 07:56:50 PM PDT 24	8514607380 ps
T167	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.961306181			Aug 16 07:18:10 PM PDT 24	Aug 16 08:03:04 PM PDT 24	11786260988 ps
T321	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1337074163			Aug 16 07:21:35 PM PDT 24	Aug 16 07:32:10 PM PDT 24	4657537052 ps
T285	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.4033808952			Aug 16 07:33:04 PM PDT 24	Aug 16 07:44:36 PM PDT 24	5926729064 ps
T26	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1161849209			Aug 16 07:06:56 PM PDT 24	Aug 16 08:54:47 PM PDT 24	32551596624 ps
T726	/workspace/coverage/default/79.chip_sw_all_escalation_resets.808920567			Aug 16 07:39:54 PM PDT 24	Aug 16 07:46:28 PM PDT 24	5848897562 ps
T897	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3133608606			Aug 16 07:09:51 PM PDT 24	Aug 16 07:21:32 PM PDT 24	5213975496 ps
T898	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.4280302088			Aug 16 07:35:30 PM PDT 24	Aug 16 08:33:45 PM PDT 24	15310169356 ps
T899	/workspace/coverage/default/4.chip_tap_straps_prod.4285876308			Aug 16 07:32:12 PM PDT 24	Aug 16 07:35:10 PM PDT 24	2756904304 ps
T201	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.1013461044			Aug 16 07:12:32 PM PDT 24	Aug 16 10:11:04 PM PDT 24	64637589781 ps
T109	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1819900216			Aug 16 07:11:09 PM PDT 24	Aug 16 08:13:02 PM PDT 24	20611810688 ps
T148	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.788677990			Aug 16 07:25:13 PM PDT 24	Aug 16 08:26:30 PM PDT 24	18739046997 ps
T900	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.292678643			Aug 16 07:16:13 PM PDT 24	Aug 16 08:23:51 PM PDT 24	14804130928 ps
T699	/workspace/coverage/default/29.chip_sw_all_escalation_resets.3022977293			Aug 16 07:35:50 PM PDT 24	Aug 16 07:47:29 PM PDT 24	5815188496 ps
T286	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3195229288			Aug 16 07:07:43 PM PDT 24	Aug 16 07:16:22 PM PDT 24	3103296976 ps
T705	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1622302048			Aug 16 07:41:47 PM PDT 24	Aug 16 07:48:31 PM PDT 24	4366342540 ps
T274	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3591517791			Aug 16 07:16:30 PM PDT 24	Aug 16 08:20:46 PM PDT 24	14993214872 ps
T337	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.272061773			Aug 16 07:31:20 PM PDT 24	Aug 16 07:41:12 PM PDT 24	4292078158 ps
T901	/workspace/coverage/default/2.chip_sw_example_concurrency.3383502163			Aug 16 07:22:05 PM PDT 24	Aug 16 07:25:40 PM PDT 24	2864335590 ps
T902	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2979596884			Aug 16 07:27:35 PM PDT 24	Aug 16 07:35:16 PM PDT 24	4143265000 ps
T712	/workspace/coverage/default/22.chip_sw_all_escalation_resets.2128664377			Aug 16 07:36:04 PM PDT 24	Aug 16 07:47:48 PM PDT 24	5344821350 ps
T181	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3882767564			Aug 16 07:11:18 PM PDT 24	Aug 16 08:40:03 PM PDT 24	44228187930 ps
T697	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3357385207			Aug 16 07:35:52 PM PDT 24	Aug 16 07:42:39 PM PDT 24	3312542748 ps
T287	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1054629599			Aug 16 07:30:32 PM PDT 24	Aug 16 07:41:55 PM PDT 24	5032879472 ps
T130	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.4138736273			Aug 16 07:31:17 PM PDT 24	Aug 16 07:43:17 PM PDT 24	6751461336 ps
T680	/workspace/coverage/default/64.chip_sw_all_escalation_resets.4216759023			Aug 16 07:38:55 PM PDT 24	Aug 16 07:47:59 PM PDT 24	5497716024 ps
T903	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.131600175			Aug 16 07:29:05 PM PDT 24	Aug 16 07:38:27 PM PDT 24	6702915320 ps
T459	/workspace/coverage/default/2.chip_sw_kmac_entropy.1444875557			Aug 16 07:23:36 PM PDT 24	Aug 16 07:27:52 PM PDT 24	3306074642 ps
T330	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1828249139			Aug 16 07:22:07 PM PDT 24	Aug 16 07:34:02 PM PDT 24	4112092264 ps