Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	140319	1			T72	98		T73	52		T74	30
values[2]	6823	1			T251	1		T536	1		T467	89
values[3]	2917	1			T467	24		T441	19		T420	19
values[4]	1965	1			T441	1		T420	10		T535	9
values[5]	1401	1			T420	11		T535	8		T782	2
values[6]	1200	1			T420	10		T535	8		T782	2
values[7]	924	1			T420	10		T535	4		T782	2
values[8]	911	1			T420	8		T535	12		T782	2
values[9]	803	1			T420	12		T535	6		T782	2
values[10]	795	1			T420	11		T535	10		T782	2
values[11]	765	1			T420	12		T535	11		T782	2
values[12]	663	1			T420	6		T535	12		T782	2
values[13]	646	1			T420	6		T535	9		T782	2
values[14]	669	1			T420	15		T535	11		T782	2
values[15]	622	1			T420	8		T535	6		T782	2
values[16]	591	1			T420	8		T535	5		T782	2
values[17]	645	1			T420	22		T535	14		T782	2
values[18]	603	1			T420	4		T535	7		T782	2
values[19]	612	1			T535	15		T782	2		T824	20
values[20]	629	1			T535	6		T782	2		T824	14
values[21]	561	1			T535	17		T782	2		T824	26
values[22]	539	1			T535	22		T782	2		T824	24
values[23]	591	1			T535	7		T782	2		T824	17
values[24]	497	1			T535	10		T782	2		T824	14
values[25]	551	1			T535	6		T782	2		T824	15
values[26]	545	1			T535	8		T782	2		T824	14
values[27]	561	1			T535	13		T782	2		T824	19
values[28]	431	1			T535	19		T782	2		T824	19
values[29]	417	1			T535	6		T782	2		T824	18
values[30]	491	1			T535	8		T782	2		T824	12
values[31]	452	1			T535	3		T782	2		T824	10
values[32]	496	1			T535	3		T782	2		T824	13
values[33]	535	1			T535	7		T782	2		T824	67
values[34]	485	1			T535	8		T782	2		T824	24
values[35]	395	1			T535	8		T782	2		T824	15
values[36]	335	1			T535	3		T782	2		T824	9
values[37]	400	1			T535	11		T782	2		T824	11
values[38]	407	1			T535	8		T782	2		T824	9
values[39]	370	1			T535	11		T782	2		T824	8
values[40]	313	1			T535	7		T782	2		T824	5
values[41]	348	1			T535	15		T782	2		T824	13
values[42]	361	1			T535	14		T782	2		T824	7
values[43]	319	1			T535	8		T782	2		T824	10
values[44]	309	1			T535	2		T782	2		T824	26
values[45]	257	1			T782	2		T824	8		T790	1
values[46]	210	1			T782	3		T824	10		T790	1
values[47]	220	1			T782	2		T824	9		T790	1
values[48]	193	1			T782	3		T824	7		T790	1
values[49]	169	1			T782	2		T824	3		T790	1
values[50]	146	1			T782	2		T824	24		T790	1
values[51]	130	1			T782	2		T824	10		T790	1
values[52]	146	1			T782	2		T824	9		T790	1
values[53]	135	1			T782	2		T824	4		T790	1
values[54]	118	1			T782	2		T824	9		T790	1
values[55]	106	1			T782	2		T824	12		T790	1
values[56]	77	1			T782	2		T824	6		T790	1
values[57]	82	1			T782	2		T824	6		T790	1
values[58]	99	1			T782	2		T824	26		T790	1
values[59]	79	1			T782	2		T824	2		T790	1
values[60]	54	1			T782	2		T790	1		T794	1
values[61]	56	1			T782	2		T790	1		T794	1
values[62]	67	1			T782	2		T790	1		T794	1
values[63]	68	1			T782	2		T790	1		T794	1
values[64]	49	1			T782	2		T790	1		T794	1
values[65]	40	1			T782	2		T790	1		T794	1
values[66]	46	1			T782	2		T790	1		T794	1
values[67]	67	1			T782	3		T790	1		T794	1
values[68]	81	1			T782	2		T790	1		T794	1
values[69]	72	1			T782	2		T790	1		T794	1
values[70]	75	1			T782	2		T790	1		T794	1
values[71]	59	1			T782	2		T790	1		T794	1
values[72]	76	1			T782	2		T790	1		T794	1
values[73]	90	1			T782	2		T790	1		T794	1
values[74]	87	1			T782	2		T790	1		T794	1
values[75]	73	1			T782	2		T790	1		T794	1
values[76]	60	1			T782	2		T790	1		T794	1
values[77]	82	1			T782	2		T790	1		T794	1
values[78]	84	1			T782	2		T790	1		T794	1
values[79]	97	1			T782	2		T790	1		T794	1
values[80]	109	1			T782	2		T790	1		T794	1
values[81]	102	1			T782	2		T790	1		T794	1
values[82]	81	1			T782	2		T790	1		T794	1
values[83]	74	1			T782	2		T790	1		T794	1
values[84]	92	1			T782	2		T790	1		T794	1
values[85]	119	1			T782	2		T790	1		T794	1
values[86]	74	1			T782	2		T790	1		T794	1
values[87]	74	1			T782	2		T790	1		T794	1
values[88]	75	1			T782	2		T790	1		T794	2
values[89]	91	1			T782	2		T790	1		T794	1
values[90]	94	1			T782	2		T790	1		T794	2
values[91]	79	1			T782	2		T790	1		T794	2
values[92]	56	1			T782	2		T790	1		T794	1
values[93]	63	1			T782	2		T790	1		T794	2
values[94]	62	1			T782	2		T790	1		T794	6
values[95]	75	1			T782	2		T790	1		T794	1
values[96]	65	1			T782	2		T790	1		T794	3
values[97]	55	1			T782	2		T790	1		T794	1
values[98]	57	1			T782	2		T790	1		T794	4
values[99]	48	1			T782	2		T790	1		T794	4
values[100]	50	1			T782	2		T790	1		T794	3
values[101]	54	1			T782	2		T790	1		T794	1
values[102]	63	1			T782	2		T790	1		T794	7
values[103]	62	1			T782	2		T790	1		T794	2
values[104]	55	1			T782	2		T790	1		T794	2
values[105]	60	1			T782	2		T790	1		T794	5
values[106]	47	1			T782	2		T790	1		T794	1
values[107]	51	1			T782	2		T790	1		T794	2
values[108]	54	1			T782	2		T790	1		T794	1
values[109]	54	1			T782	2		T790	1		T794	1
values[110]	44	1			T782	2		T790	1		T794	3
values[111]	57	1			T782	2		T790	1		T794	2
values[112]	57	1			T782	2		T790	1		T794	2
values[113]	52	1			T782	2		T790	1		T794	3
values[114]	68	1			T782	5		T790	6		T794	1
values[115]	60	1			T782	2		T790	2		T794	1
values[116]	54	1			T782	2		T790	5		T794	1
values[117]	58	1			T782	2		T790	1		T794	2
values[118]	49	1			T782	5		T790	2		T794	1
values[119]	54	1			T782	3		T790	1		T794	1
values[120]	56	1			T782	2		T790	2		T794	2
values[121]	50	1			T782	3		T790	4		T794	3
values[122]	47	1			T782	3		T790	3		T794	3
values[123]	40	1			T782	6		T790	2		T794	1
values[124]	47	1			T782	7		T790	1		T794	1
values[125]	47	1			T782	5		T790	1		T794	1
values[126]	105	1			T782	8		T790	5		T794	5
values[127]	1470	1			T782	110		T790	53		T794	73
values[128]	6871	1			T782	552		T790	265		T794	314