Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	478	1			T536	1		T441	2		T538	3
all_values[1]	517	1			T536	2		T467	1		T441	1
all_values[2]	490	1			T536	1		T441	1		T538	2
all_values[3]	495	1			T536	1		T538	3		T542	2
all_values[4]	469	1			T536	1		T441	1		T538	4
all_values[5]	533	1			T536	7		T441	2		T538	3
all_values[6]	503	1			T536	2		T467	1		T441	1
all_values[7]	479	1			T536	2		T538	1		T542	1
all_values[8]	490	1			T536	3		T714	1		T441	3
all_values[9]	485	1			T441	1		T538	1		T420	1
all_values[10]	503	1			T536	2		T441	1		T538	3
all_values[11]	485	1			T536	3		T538	1		T654	1
all_values[12]	473	1			T536	4		T538	2		T420	1
all_values[13]	482	1			T441	1		T538	3		T654	1
all_values[14]	490	1			T441	1		T538	5		T542	2
all_values[15]	496	1			T536	3		T441	2		T538	1
all_values[16]	485	1			T536	1		T441	1		T538	1
all_values[17]	459	1			T536	2		T441	1		T538	1
all_values[18]	465	1			T538	1		T654	1		T535	1
all_values[19]	473	1			T538	2		T542	1		T535	1
all_values[20]	507	1			T536	6		T467	1		T441	2
all_values[21]	465	1			T536	3		T441	2		T538	2
all_values[22]	493	1			T536	4		T714	1		T441	2
all_values[23]	508	1			T536	3		T467	1		T538	2
all_values[24]	518	1			T536	2		T467	1		T441	3
all_values[25]	497	1			T536	3		T441	1		T538	3
all_values[26]	468	1			T536	3		T467	2		T538	1
all_values[27]	456	1			T536	2		T538	3		T654	1
all_values[28]	524	1			T536	2		T467	1		T441	1
all_values[29]	468	1			T536	1		T538	2		T516	5
all_values[30]	503	1			T536	3		T715	1		T538	3
all_values[31]	474	1			T536	4		T538	2		T420	1
all_values[32]	487	1			T714	1		T441	2		T538	3
all_values[33]	460	1			T536	1		T538	3		T542	1
all_values[34]	466	1			T536	1		T538	2		T542	1
all_values[35]	488	1			T536	1		T538	5		T542	1
all_values[36]	482	1			T536	3		T441	2		T538	2
all_values[37]	475	1			T536	1		T467	1		T538	1
all_values[38]	466	1			T536	2		T538	1		T542	1
all_values[39]	459	1			T536	3		T538	2		T535	1
all_values[40]	473	1			T536	4		T441	1		T538	3
all_values[41]	493	1			T536	1		T441	2		T538	1
all_values[42]	509	1			T536	6		T538	2		T542	1
all_values[43]	435	1			T536	1		T542	1		T420	1
all_values[44]	444	1			T441	2		T538	2		T542	1
all_values[45]	446	1			T536	3		T441	1		T538	2
all_values[46]	503	1			T536	3		T538	1		T844	1
all_values[47]	499	1			T536	1		T538	4		T542	1
all_values[48]	442	1			T536	2		T538	1		T844	1
all_values[49]	483	1			T536	1		T441	1		T542	1