Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3679	1			T72	2		T536	15		T467	1
all_values[1]	3645	1			T72	5		T536	23		T467	5
all_values[2]	3663	1			T72	5		T536	22		T467	1
all_values[3]	3586	1			T72	4		T536	22		T467	2
all_values[4]	3639	1			T72	6		T536	22		T467	2
all_values[5]	3600	1			T72	1		T536	16		T467	4
all_values[6]	3714	1			T72	3		T536	19		T441	1
all_values[7]	3635	1			T72	2		T536	12		T467	4
all_values[8]	3651	1			T72	4		T536	21		T467	2
all_values[9]	3556	1			T72	2		T536	16		T441	1
all_values[10]	3624	1			T72	2		T536	8		T467	3
all_values[11]	3561	1			T72	6		T536	11		T467	1
all_values[12]	3638	1			T72	3		T536	23		T441	3
all_values[13]	3606	1			T72	4		T536	12		T467	2
all_values[14]	3698	1			T72	2		T536	13		T467	1
all_values[15]	3682	1			T72	3		T536	21		T467	1
all_values[16]	3629	1			T72	8		T536	24		T467	6
all_values[17]	3619	1			T72	3		T536	23		T467	1
all_values[18]	3652	1			T72	5		T536	20		T441	4
all_values[19]	3645	1			T72	4		T536	21		T467	3
all_values[20]	3729	1			T72	3		T536	21		T467	2
all_values[21]	3671	1			T72	1		T536	24		T467	2
all_values[22]	3668	1			T72	6		T536	20		T467	5
all_values[23]	3695	1			T72	5		T536	23		T467	1
all_values[24]	3559	1			T72	3		T536	20		T467	4
all_values[25]	3629	1			T72	3		T536	23		T467	2
all_values[26]	3633	1			T72	1		T536	23		T467	3
all_values[27]	3641	1			T72	4		T536	19		T467	2
all_values[28]	3600	1			T536	18		T467	2		T538	13
all_values[29]	3725	1			T72	4		T536	18		T467	3
all_values[30]	3660	1			T72	1		T536	14		T467	1
all_values[31]	3720	1			T72	1		T536	15		T467	1
all_values[32]	3636	1			T72	4		T536	20		T467	2
all_values[33]	3677	1			T72	3		T536	20		T441	3
all_values[34]	3695	1			T72	5		T536	25		T441	2
all_values[35]	3574	1			T72	3		T536	21		T467	3
all_values[36]	3660	1			T72	3		T536	13		T467	3
all_values[37]	3621	1			T72	1		T536	19		T467	5
all_values[38]	3614	1			T72	4		T536	23		T467	5
all_values[39]	3659	1			T72	4		T536	14		T467	4
all_values[40]	3735	1			T72	1		T536	22		T441	2
all_values[41]	3617	1			T72	1		T536	17		T467	3
all_values[42]	3679	1			T72	4		T536	17		T467	2
all_values[43]	3748	1			T72	3		T536	20		T467	2
all_values[44]	3665	1			T72	1		T536	22		T467	5
all_values[45]	3682	1			T72	2		T536	21		T467	3
all_values[46]	3720	1			T72	3		T536	20		T467	1
all_values[47]	3643	1			T72	4		T536	13		T441	4
all_values[48]	3621	1			T72	6		T536	26		T467	3
all_values[49]	3706	1			T72	3		T536	20		T467	1
all_values[50]	3775	1			T72	1		T536	19		T467	3
all_values[51]	3644	1			T72	3		T536	21		T467	2
all_values[52]	3596	1			T72	3		T536	14		T467	4
all_values[53]	3666	1			T72	1		T536	26		T467	1
all_values[54]	3620	1			T72	2		T536	19		T467	3
all_values[55]	3743	1			T72	4		T536	25		T467	1
all_values[56]	3640	1			T72	4		T536	18		T467	5
all_values[57]	3728	1			T72	3		T536	15		T467	5
all_values[58]	3724	1			T72	4		T536	18		T467	5
all_values[59]	3620	1			T72	1		T536	20		T467	7
all_values[60]	3662	1			T72	5		T536	17		T467	2
all_values[61]	3698	1			T72	1		T536	20		T467	4
all_values[62]	3615	1			T72	2		T536	27		T467	4
all_values[63]	3667	1			T72	2		T536	16		T467	2