Unified Coverage Report :: Cond split page

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 LINE       32668
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32669
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32670
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32671
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32672
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T64,T362

 LINE       32673
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       32674
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       32675
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32676
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32677
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       32678
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32679
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32680
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32681
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32682
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32683
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T156

 LINE       32684
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32685
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32686
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32687
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32688
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32689
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32690
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32691
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32692
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32693
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32694
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32695
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_0_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32696
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_1_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32697
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_2_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32698
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_3_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32699
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_4_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32700
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_5_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T144

 LINE       32701
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_6_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32702
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_7_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32703
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_8_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32704
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_9_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T362

 LINE       32705
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_10_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T362

 LINE       32706
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_11_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32707
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_12_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T362

 LINE       32708
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_13_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       32709
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_14_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       32710
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_15_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T362

 LINE       32711
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_16_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32712
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_17_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32713
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_18_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32714
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_19_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32715
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_20_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32716
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_21_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32717
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_22_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32718
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_23_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32719
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_24_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32720
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_25_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       32721
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_26_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       32722
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_27_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32723
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_28_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32724
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_29_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       32725
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_30_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32726
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_31_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32727
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_32_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32728
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_33_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32729
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_34_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32730
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_35_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32731
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_36_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T49

 LINE       32732
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_37_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32733
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_38_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32734
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_39_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32735
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_40_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32736
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_41_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32737
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_42_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T64,T362

 LINE       32738
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_43_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32739
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_44_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32740
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_45_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32741
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_OUTSEL_46_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32742
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32743
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32744
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T362

 LINE       32745
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32746
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32747
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32748
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T156

 LINE       32749
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32750
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32751
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T362

 LINE       32752
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T362

 LINE       32753
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32754
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T362

 LINE       32755
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T362

 LINE       32756
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T362

 LINE       32757
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T362

 LINE       32758
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32759
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32760
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32761
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32762
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32763
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32764
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32765
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32766
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32767
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       32768
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32769
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32770
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32771
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32772
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32773
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32774
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32775
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32776
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32777
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32778
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32779
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32780
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32781
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32782
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32783
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32784
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32785
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32786
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T362

 LINE       32787
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32788
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32789
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_0_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32790
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_1_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32791
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_2_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T362

 LINE       32792
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_3_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32793
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_4_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32794
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_5_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32795
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_6_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32796
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_7_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32797
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_8_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32798
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_9_OFFSET)
            -----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T362

 LINE       32799
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_10_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T111

 LINE       32800
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_11_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32801
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_12_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T362

 LINE       32802
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_13_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T362

 LINE       32803
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_14_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T362

 LINE       32804
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_15_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T13,T362

 LINE       32805
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_16_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32806
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_17_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T111,T362

 LINE       32807
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_18_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32808
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_19_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32809
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_20_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32810
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_21_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32811
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_22_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T362

 LINE       32812
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_23_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T362

 LINE       32813
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_24_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T5,T111

 LINE       32814
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_25_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       32815
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_26_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32816
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_27_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32817
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_28_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32818
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_29_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32819
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_30_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32820
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_31_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32821
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_32_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32822
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_33_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32823
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_34_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32824
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_35_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32825
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_36_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32826
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_37_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T362,T400

 LINE       32827
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_38_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T111,T362

 LINE       32828
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_39_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T111,T362

 LINE       32829
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_40_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T77,T438,T530

 LINE       32830
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_41_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T257,T77,T438

 LINE       32831
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_42_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T77,T441,T531

 LINE       32832
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_43_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T111,T362

 LINE       32833
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_44_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T111,T362

 LINE       32834
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_45_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T111,T362

 LINE       32835
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_ATTR_46_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T111,T362

 LINE       32836
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       32837
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       32838
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T156,T155

 LINE       32839
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T14,T51

 LINE       32840
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T156,T155

 LINE       32841
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T64,T13

 LINE       32842
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T64,T111

 LINE       32843
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T51,T77,T72

 LINE       32844
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T51,T77,T440

 LINE       32845
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T51,T77,T73

 LINE       32846
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T64,T111