Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
3978 | 
1 | 
 | 
 | 
T415 | 
1097 | 
 | 
T84 | 
79 | 
 | 
T370 | 
1080 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
3980 | 
1 | 
 | 
 | 
T415 | 
1098 | 
 | 
T84 | 
79 | 
 | 
T370 | 
1081 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
3978 | 
1 | 
 | 
 | 
T415 | 
1097 | 
 | 
T84 | 
79 | 
 | 
T370 | 
1080 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
5445 | 
1 | 
 | 
 | 
T84 | 
66 | 
 | 
T52 | 
1 | 
 | 
T249 | 
1722 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
5445 | 
1 | 
 | 
 | 
T84 | 
66 | 
 | 
T52 | 
1 | 
 | 
T249 | 
1722 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
5445 | 
1 | 
 | 
 | 
T84 | 
66 | 
 | 
T52 | 
1 | 
 | 
T249 | 
1722 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
97 | 
1 | 
 | 
 | 
T52 | 
1 | 
 | 
T53 | 
1 | 
 | 
T54 | 
1 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
98 | 
1 | 
 | 
 | 
T52 | 
1 | 
 | 
T53 | 
1 | 
 | 
T54 | 
1 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
97 | 
1 | 
 | 
 | 
T52 | 
1 | 
 | 
T53 | 
1 | 
 | 
T54 | 
1 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
1977 | 
1 | 
 | 
 | 
T52 | 
1 | 
 | 
T748 | 
814 | 
 | 
T53 | 
1 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
1980 | 
1 | 
 | 
 | 
T52 | 
1 | 
 | 
T269 | 
1 | 
 | 
T748 | 
815 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
1977 | 
1 | 
 | 
 | 
T52 | 
1 | 
 | 
T748 | 
814 | 
 | 
T53 | 
1 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
1990 | 
1 | 
 | 
 | 
T84 | 
84 | 
 | 
T74 | 
2 | 
 | 
T52 | 
1 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
1991 | 
1 | 
 | 
 | 
T84 | 
84 | 
 | 
T74 | 
2 | 
 | 
T52 | 
1 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
1990 | 
1 | 
 | 
 | 
T84 | 
84 | 
 | 
T74 | 
2 | 
 | 
T52 | 
1 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
3591 | 
1 | 
 | 
 | 
T68 | 
2 | 
 | 
T52 | 
1 | 
 | 
T749 | 
504 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
3594 | 
1 | 
 | 
 | 
T68 | 
2 | 
 | 
T52 | 
1 | 
 | 
T749 | 
504 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
3591 | 
1 | 
 | 
 | 
T68 | 
2 | 
 | 
T52 | 
1 | 
 | 
T749 | 
504 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
4396 | 
1 | 
 | 
 | 
T68 | 
1 | 
 | 
T368 | 
814 | 
 | 
T312 | 
815 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
4399 | 
1 | 
 | 
 | 
T68 | 
1 | 
 | 
T368 | 
815 | 
 | 
T312 | 
816 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
4396 | 
1 | 
 | 
 | 
T68 | 
1 | 
 | 
T368 | 
814 | 
 | 
T312 | 
815 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
1426 | 
1 | 
 | 
 | 
T68 | 
1 | 
 | 
T221 | 
513 | 
 | 
T52 | 
1 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
1427 | 
1 | 
 | 
 | 
T68 | 
1 | 
 | 
T221 | 
513 | 
 | 
T52 | 
1 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
1426 | 
1 | 
 | 
 | 
T68 | 
1 | 
 | 
T221 | 
513 | 
 | 
T52 | 
1 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
2735 | 
1 | 
 | 
 | 
T68 | 
1 | 
 | 
T52 | 
1 | 
 | 
T750 | 
809 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
2736 | 
1 | 
 | 
 | 
T68 | 
1 | 
 | 
T52 | 
1 | 
 | 
T750 | 
809 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
2735 | 
1 | 
 | 
 | 
T68 | 
1 | 
 | 
T52 | 
1 | 
 | 
T750 | 
809 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
3463 | 
1 | 
 | 
 | 
T84 | 
64 | 
 | 
T302 | 
694 | 
 | 
T276 | 
670 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
3463 | 
1 | 
 | 
 | 
T84 | 
64 | 
 | 
T302 | 
694 | 
 | 
T276 | 
670 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
3463 | 
1 | 
 | 
 | 
T84 | 
64 | 
 | 
T302 | 
694 | 
 | 
T276 | 
670 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
258 | 
1 | 
 | 
 | 
T84 | 
71 | 
 | 
T680 | 
1 | 
 | 
T74 | 
2 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
258 | 
1 | 
 | 
 | 
T84 | 
71 | 
 | 
T680 | 
1 | 
 | 
T74 | 
2 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
258 | 
1 | 
 | 
 | 
T84 | 
71 | 
 | 
T680 | 
1 | 
 | 
T74 | 
2 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
8753 | 
1 | 
 | 
 | 
T84 | 
85 | 
 | 
T683 | 
1095 | 
 | 
T52 | 
1 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
8753 | 
1 | 
 | 
 | 
T84 | 
85 | 
 | 
T683 | 
1095 | 
 | 
T52 | 
1 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
8753 | 
1 | 
 | 
 | 
T84 | 
85 | 
 | 
T683 | 
1095 | 
 | 
T52 | 
1 | 
 
Summary for Variable cp_handshake_complete
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_handshake_complete
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
283 | 
1 | 
 | 
 | 
T84 | 
71 | 
 | 
T680 | 
1 | 
 | 
T52 | 
1 | 
Summary for Variable cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_trans_type
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| alert_triggered | 
283 | 
1 | 
 | 
 | 
T84 | 
71 | 
 | 
T680 | 
1 | 
 | 
T52 | 
1 | 
Summary for Cross alert_handshake_complete
Samples crossed: cp_handshake_complete cp_trans_type
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
1 | 
0 | 
1 | 
100.00 | 
 | 
Automatically Generated Cross Bins for alert_handshake_complete
Bins
| cp_handshake_complete | cp_trans_type | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| complete | 
alert_triggered | 
283 | 
1 | 
 | 
 | 
T84 | 
71 | 
 | 
T680 | 
1 | 
 | 
T52 | 
1 |