Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.17	95.54	94.10	95.34		94.92	97.53	99.58

Total tests in report: 2934

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.17	39.17	44.12	44.12	42.75	42.75	31.41	31.41			57.48	57.48	59.09	59.09	0.19	0.19	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.95633133
49.17	10.00	50.08	5.96	60.95	18.19	31.86	0.46			68.32	10.85	82.17	23.08	1.64	1.46	/workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.3611390640
56.03	6.86	59.16	9.08	62.22	1.27	34.53	2.67			68.99	0.67	82.17	0.00	29.14	27.49	/workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.371922307
61.43	5.39	70.85	11.69	69.73	7.51	37.37	2.83			79.30	10.31	82.17	0.00	29.14	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.4240699983
64.53	3.11	76.12	5.27	73.60	3.87	40.90	3.53			81.07	1.77	86.36	4.20	29.14	0.00	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1441850676
67.39	2.85	76.12	0.00	73.60	0.00	40.90	0.00			81.07	0.00	86.36	0.00	46.26	17.12	/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1249605560
69.92	2.53	78.72	2.59	76.52	2.92	47.86	6.97			83.27	2.20	86.89	0.52	46.26	0.00	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.961331937
72.23	2.31	78.72	0.00	76.95	0.42	47.86	0.00			83.38	0.11	86.89	0.00	59.58	13.32	/workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.2972892857
74.41	2.18	82.39	3.67	78.87	1.92	50.27	2.40			85.11	1.73	90.03	3.15	59.78	0.20	/workspace/coverage/default/2.chip_jtag_csr_rw.1407131888
76.43	2.02	82.39	0.00	78.87	0.00	62.41	12.14			85.11	0.00	90.03	0.00	59.78	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3869155650
78.18	1.75	82.68	0.29	79.02	0.15	71.70	9.30			85.29	0.18	90.56	0.52	59.83	0.05	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1949801273
79.84	1.66	83.42	0.74	79.21	0.19	74.91	3.21			85.40	0.11	90.56	0.00	65.57	5.75	/workspace/coverage/cover_reg_top/60.xbar_stress_all.1054889579
81.45	1.61	83.42	0.00	79.21	0.00	74.91	0.00			85.40	0.00	90.56	0.00	75.23	9.66	/workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.324194690
82.91	1.46	85.59	2.17	81.25	2.05	77.07	2.16			87.78	2.39	90.56	0.00	75.23	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2149295502
84.19	1.27	85.59	0.00	81.25	0.00	77.07	0.00			87.78	0.00	90.56	0.00	82.87	7.64	/workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.3356933536
85.43	1.24	87.96	2.37	83.38	2.13	77.42	0.35			90.04	2.26	90.91	0.35	82.87	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.307752088
86.29	0.86	89.04	1.08	84.15	0.77	79.08	1.65			91.12	1.08	90.91	0.00	83.44	0.58	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.205656009
87.07	0.79	89.04	0.00	84.15	0.00	79.08	0.00			91.12	0.00	90.91	0.00	88.16	4.71	/workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.1726416283
87.83	0.75	89.82	0.78	84.95	0.80	80.23	1.15			91.68	0.57	90.91	0.00	89.38	1.22	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2866862781
88.58	0.75	90.21	0.40	85.07	0.12	80.24	0.01			91.80	0.11	94.76	3.85	89.38	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.873691563
89.32	0.74	91.66	1.44	85.73	0.66	81.72	1.47			92.31	0.51	95.10	0.35	89.38	0.00	/workspace/coverage/default/0.chip_sw_power_virus.3076089196
90.01	0.69	91.67	0.01	85.74	0.01	85.83	4.12			92.31	0.00	95.10	0.00	89.38	0.00	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1732825754
90.56	0.55	91.67	0.01	85.92	0.18	86.53	0.70			92.34	0.03	95.10	0.00	91.79	2.41	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.2680577284
91.05	0.49	91.67	0.00	85.92	0.00	86.53	0.00			92.34	0.00	95.10	0.00	94.75	2.96	/workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.1288069036
91.50	0.45	92.60	0.92	86.67	0.75	86.99	0.46			92.92	0.58	95.10	0.00	94.75	0.00	/workspace/coverage/default/1.chip_sw_gpio.81852934
91.95	0.45	93.13	0.53	87.12	0.46	88.22	1.23			93.39	0.46	95.10	0.00	94.75	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.1793198642
92.30	0.34	93.13	0.00	87.22	0.10	88.22	0.00			93.39	0.00	95.10	0.00	96.72	1.97	/workspace/coverage/cover_reg_top/53.xbar_stress_all.3733080960
92.56	0.27	93.13	0.01	88.77	1.55	88.22	0.00			93.39	0.00	95.10	0.00	96.77	0.05	/workspace/coverage/cover_reg_top/20.chip_tl_errors.2432601232
92.80	0.23	93.37	0.24	88.82	0.05	89.20	0.98			93.43	0.04	95.10	0.00	96.86	0.09	/workspace/coverage/default/1.chip_jtag_csr_rw.2638124778
93.01	0.21	93.59	0.22	89.01	0.19	89.39	0.19			93.57	0.15	95.63	0.52	96.86	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2594477668
93.22	0.21	93.80	0.20	90.03	1.02	89.40	0.01			93.59	0.02	95.63	0.00	96.86	0.00	/workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.3160266465
93.41	0.20	93.80	0.00	90.03	0.00	90.58	1.18			93.59	0.00	95.63	0.00	96.86	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.4069436260
93.56	0.15	93.91	0.11	90.07	0.04	90.80	0.22			93.59	0.00	96.15	0.52	96.86	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3561363122
93.71	0.15	94.11	0.21	90.39	0.32	91.15	0.35			93.59	0.00	96.15	0.00	96.86	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3092432744
93.85	0.13	94.14	0.02	90.45	0.06	91.68	0.52			93.61	0.02	96.33	0.17	96.86	0.00	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2436348781
93.96	0.12	94.14	0.00	90.47	0.01	91.68	0.00			93.61	0.00	96.33	0.00	97.56	0.69	/workspace/coverage/cover_reg_top/24.xbar_random_large_delays.1840530715
94.07	0.10	94.14	0.00	91.08	0.61	91.68	0.00			93.61	0.00	96.33	0.00	97.57	0.01	/workspace/coverage/cover_reg_top/5.chip_tl_errors.339858567
94.17	0.10	94.14	0.00	91.37	0.28	91.69	0.02			93.94	0.32	96.33	0.00	97.57	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3065995426
94.26	0.09	94.33	0.19	91.48	0.11	91.82	0.13			94.06	0.12	96.33	0.00	97.57	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.350957014
94.35	0.08	94.33	0.01	91.52	0.04	92.09	0.28			94.07	0.01	96.50	0.17	97.57	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1058737941
94.43	0.08	94.33	0.00	91.52	0.00	92.59	0.49			94.07	0.00	96.50	0.00	97.57	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1694168477
94.51	0.08	94.33	0.00	91.60	0.08	92.59	0.00			94.07	0.00	96.50	0.00	97.97	0.40	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1705639353
94.58	0.07	94.33	0.00	91.60	0.00	93.03	0.44			94.07	0.00	96.50	0.00	97.97	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2923761642
94.65	0.07	94.33	0.00	91.60	0.00	93.44	0.41			94.07	0.00	96.50	0.00	97.97	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.829323211
94.72	0.07	94.35	0.02	91.76	0.16	93.45	0.01			94.11	0.04	96.68	0.17	97.97	0.00	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2243561014
94.78	0.06	94.35	0.00	91.93	0.17	93.45	0.00			94.30	0.19	96.68	0.00	97.97	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3957682584
94.83	0.05	94.38	0.03	91.96	0.03	93.46	0.01			94.35	0.05	96.85	0.17	98.00	0.04	/workspace/coverage/default/18.chip_sw_all_escalation_resets.2082078186
94.88	0.05	94.42	0.05	91.97	0.01	93.66	0.20			94.39	0.03	96.85	0.00	98.00	0.00	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2910514539
94.93	0.05	94.46	0.03	92.11	0.14	93.66	0.00			94.49	0.11	96.85	0.00	98.00	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.234024200
94.97	0.04	94.46	0.00	92.11	0.00	93.92	0.26			94.49	0.00	96.85	0.00	98.00	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2190583520
95.02	0.04	94.48	0.02	92.14	0.03	93.95	0.03			94.49	0.00	96.85	0.00	98.18	0.18	/workspace/coverage/default/2.chip_sw_alert_test.2278577513
95.06	0.04	94.50	0.03	92.17	0.02	93.95	0.01			94.52	0.02	97.03	0.17	98.18	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1213350917
95.10	0.04	94.50	0.00	92.40	0.23	93.95	0.00			94.52	0.00	97.03	0.00	98.18	0.00	/workspace/coverage/cover_reg_top/7.chip_tl_errors.1584600842
95.13	0.04	94.58	0.07	92.40	0.00	94.09	0.14			94.52	0.01	97.03	0.00	98.18	0.00	/workspace/coverage/default/1.chip_tap_straps_rma.2970239498
95.17	0.04	94.58	0.01	92.41	0.01	94.10	0.01			94.53	0.01	97.20	0.17	98.19	0.01	/workspace/coverage/default/59.chip_sw_all_escalation_resets.1639749272
95.21	0.04	94.58	0.01	92.42	0.01	94.11	0.01			94.54	0.01	97.38	0.17	98.20	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.2910032663
95.24	0.04	94.59	0.01	92.44	0.01	94.11	0.00			94.55	0.01	97.55	0.17	98.21	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.1080995086
95.28	0.04	94.62	0.03	92.48	0.04	94.23	0.12			94.57	0.02	97.55	0.00	98.21	0.00	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.284759949
95.31	0.03	94.62	0.00	92.56	0.08	94.23	0.00			94.60	0.03	97.55	0.00	98.28	0.07	/workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.2098571436
95.34	0.03	94.62	0.00	92.56	0.00	94.39	0.16			94.60	0.00	97.55	0.00	98.28	0.00	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3611727483
95.36	0.03	94.65	0.03	92.60	0.04	94.44	0.05			94.65	0.04	97.55	0.00	98.28	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.4228843246
95.39	0.03	94.72	0.07	92.65	0.05	94.44	0.00			94.68	0.03	97.55	0.00	98.28	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2858371925
95.41	0.02	94.72	0.00	92.80	0.14	94.44	0.00			94.68	0.00	97.55	0.00	98.28	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1519043065
95.43	0.02	94.72	0.00	92.86	0.06	94.44	0.00			94.69	0.02	97.55	0.00	98.34	0.06	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.147765680
95.46	0.02	94.78	0.07	92.90	0.05	94.44	0.00			94.71	0.02	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3202066706
95.48	0.02	94.78	0.00	92.94	0.04	94.44	0.00			94.71	0.00	97.55	0.00	98.43	0.08	/workspace/coverage/cover_reg_top/0.xbar_stress_all.3562569821
95.50	0.02	94.79	0.01	92.98	0.04	94.48	0.04			94.73	0.02	97.55	0.00	98.44	0.01	/workspace/coverage/default/42.chip_sw_all_escalation_resets.3625839843
95.52	0.02	94.79	0.00	93.09	0.11	94.48	0.00			94.73	0.00	97.55	0.00	98.44	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.278649944
95.53	0.02	94.84	0.05	93.11	0.02	94.49	0.01			94.77	0.03	97.55	0.00	98.44	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3622960406
95.55	0.02	94.85	0.01	93.17	0.05	94.49	0.00			94.82	0.05	97.55	0.00	98.44	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.389258292
95.57	0.02	94.86	0.01	93.19	0.02	94.54	0.05			94.84	0.02	97.55	0.00	98.44	0.00	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.255104166
95.59	0.02	94.86	0.00	93.19	0.00	94.64	0.10			94.84	0.00	97.55	0.00	98.44	0.00	/workspace/coverage/cover_reg_top/38.xbar_same_source.3530883050
95.60	0.02	94.87	0.01	93.20	0.01	94.71	0.07			94.85	0.01	97.55	0.00	98.44	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.726792679
95.62	0.01	94.87	0.00	93.29	0.09	94.71	0.00			94.85	0.00	97.55	0.00	98.44	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.3101105639
95.63	0.01	94.87	0.00	93.29	0.00	94.71	0.00			94.85	0.00	97.55	0.00	98.52	0.08	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.1429652479
95.65	0.01	94.87	0.00	93.29	0.00	94.79	0.08			94.85	0.00	97.55	0.00	98.52	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3288488730
95.66	0.01	94.87	0.00	93.36	0.07	94.79	0.00			94.85	0.00	97.55	0.00	98.52	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.501868947
95.67	0.01	94.87	0.00	93.42	0.06	94.79	0.00			94.86	0.02	97.55	0.00	98.52	0.00	/workspace/coverage/cover_reg_top/2.xbar_stress_all.1207300412
95.68	0.01	94.87	0.00	93.43	0.01	94.79	0.00			94.86	0.00	97.55	0.00	98.58	0.06	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1199504224
95.69	0.01	94.87	0.00	93.43	0.01	94.85	0.05			94.86	0.00	97.55	0.00	98.59	0.01	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.552582406
95.70	0.01	94.87	0.00	93.50	0.06	94.85	0.00			94.86	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/cover_reg_top/39.xbar_stress_all.1891508055
95.71	0.01	94.87	0.01	93.52	0.02	94.89	0.04			94.86	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1160578859
95.72	0.01	94.87	0.00	93.52	0.00	94.95	0.06			94.86	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2221416950
95.73	0.01	94.87	0.00	93.54	0.02	94.95	0.00			94.86	0.00	97.55	0.00	98.63	0.04	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.1942742671
95.74	0.01	94.90	0.02	93.55	0.01	94.95	0.01			94.88	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3641199375
95.75	0.01	94.92	0.02	93.55	0.01	94.96	0.01			94.90	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3928204155
95.76	0.01	94.92	0.00	93.60	0.05	94.96	0.00			94.90	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/cover_reg_top/18.chip_tl_errors.1174877742
95.77	0.01	94.92	0.00	93.61	0.01	95.01	0.05			94.90	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.1281537909
95.78	0.01	94.92	0.00	93.61	0.00	95.06	0.05			94.90	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3568941839
95.78	0.01	94.92	0.00	93.61	0.00	95.06	0.00			94.90	0.00	97.55	0.00	98.67	0.05	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.2264294694
95.79	0.01	94.92	0.00	93.65	0.04	95.06	0.00			94.90	0.00	97.55	0.00	98.67	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.375225383
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96.02	0.01	94.95	0.00	93.93	0.00	95.25	0.00			94.90	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2933402669
96.02	0.01	94.95	0.00	93.93	0.00	95.25	0.00			94.90	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/83.chip_sw_all_escalation_resets.3902552192
96.02	0.01	94.95	0.00	93.93	0.00	95.25	0.00			94.90	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/86.chip_sw_all_escalation_resets.3922280969
96.02	0.01	94.95	0.00	93.93	0.00	95.25	0.00			94.90	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/87.chip_sw_all_escalation_resets.4043703707
96.02	0.01	94.95	0.00	93.93	0.00	95.25	0.00			94.90	0.00	97.55	0.00	99.57	0.01	/workspace/coverage/default/91.chip_sw_all_escalation_resets.4105834123
96.03	0.01	94.95	0.00	93.93	0.00	95.25	0.00			94.90	0.00	97.55	0.00	99.58	0.01	/workspace/coverage/default/92.chip_sw_all_escalation_resets.4235993104
96.03	0.01	94.95	0.00	93.94	0.01	95.26	0.01			94.90	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1108558550
96.03	0.01	94.95	0.00	93.94	0.01	95.26	0.00			94.90	0.01	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1967627271
96.03	0.01	94.95	0.00	93.95	0.01	95.26	0.00			94.90	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.733220889
96.03	0.01	94.95	0.00	93.96	0.01	95.26	0.00			94.90	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/24.chip_tl_errors.932056072
96.04	0.01	94.95	0.00	93.97	0.01	95.26	0.00			94.90	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3300415488
96.04	0.01	94.95	0.00	93.98	0.01	95.26	0.00			94.90	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3165155279
96.04	0.01	94.95	0.00	93.99	0.01	95.26	0.00			94.90	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.215729650
96.04	0.01	94.95	0.00	94.00	0.01	95.26	0.00			94.90	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1297856719
96.04	0.01	94.95	0.00	94.01	0.01	95.26	0.00			94.90	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2148554755
96.04	0.01	94.96	0.01	94.01	0.00	95.26	0.01			94.90	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1750230310
96.05	0.01	94.96	0.00	94.01	0.00	95.27	0.01			94.90	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3856679625
96.05	0.01	94.96	0.00	94.01	0.00	95.28	0.01			94.90	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3160357248
96.05	0.01	94.96	0.00	94.01	0.00	95.29	0.01			94.90	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3185214598
96.05	0.01	94.96	0.00	94.01	0.00	95.29	0.01			94.91	0.01	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3365427406
96.05	0.01	94.96	0.00	94.01	0.00	95.29	0.00			94.92	0.01	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_tap_straps_dev.2622316766
96.05	0.01	94.96	0.00	94.02	0.01	95.29	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/20.xbar_stress_all.97526343
96.05	0.01	94.96	0.00	94.03	0.01	95.29	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_gpio.3609987889
96.06	0.01	94.96	0.00	94.04	0.01	95.29	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.2938735875
96.06	0.01	94.96	0.00	94.04	0.01	95.29	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1692213073
96.06	0.01	94.96	0.00	94.04	0.00	95.30	0.01			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4041695288
96.06	0.01	94.96	0.01	94.04	0.00	95.30	0.01			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2246384855
96.06	0.01	94.96	0.00	94.04	0.00	95.31	0.01			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2550094994
96.06	0.01	94.96	0.00	94.04	0.00	95.31	0.01			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_aes_idle.2504163785
96.06	0.01	94.96	0.00	94.04	0.00	95.32	0.01			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2012344504
96.06	0.01	94.96	0.00	94.04	0.00	95.32	0.01			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1326877401
96.06	0.01	94.96	0.00	94.04	0.00	95.33	0.01			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1926964043
96.06	0.01	94.96	0.00	94.05	0.01	95.33	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.557966410
96.06	0.01	94.96	0.00	94.05	0.01	95.33	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/11.chip_tl_errors.3726574487
96.06	0.01	94.96	0.00	94.05	0.01	95.33	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3491508063
96.07	0.01	94.96	0.00	94.06	0.01	95.33	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2047546683
96.07	0.01	94.96	0.00	94.06	0.01	95.33	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.36547505
96.07	0.01	94.96	0.00	94.06	0.01	95.33	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1327634155
96.07	0.01	94.96	0.00	94.07	0.01	95.33	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1417031250
96.07	0.01	94.96	0.00	94.07	0.01	95.33	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3215379775
96.07	0.01	94.96	0.00	94.07	0.01	95.33	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.4208180135
96.07	0.01	94.96	0.00	94.08	0.01	95.33	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.432933377
96.07	0.01	94.96	0.00	94.08	0.01	95.33	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.320870623
96.07	0.01	94.96	0.00	94.08	0.01	95.33	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.1440805093
96.07	0.01	94.96	0.00	94.09	0.01	95.33	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.4238777454
96.07	0.01	94.96	0.00	94.09	0.01	95.33	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.154794132
96.07	0.01	94.96	0.00	94.10	0.01	95.33	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2028827956
96.07	0.01	94.96	0.00	94.10	0.01	95.33	0.00			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/2.chip_sw_gpio.3879338536
96.07	0.01	94.96	0.00	94.10	0.00	95.33	0.01			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1844799440
96.07	0.01	94.96	0.00	94.10	0.00	95.33	0.01			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.681725664
96.07	0.01	94.96	0.00	94.10	0.00	95.33	0.01			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1570048418
96.07	0.01	94.96	0.00	94.10	0.00	95.33	0.01			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.577702098
96.07	0.01	94.96	0.00	94.10	0.00	95.34	0.01			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3197342109
96.07	0.01	94.96	0.00	94.10	0.00	95.34	0.01			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1129391316
96.08	0.01	94.96	0.00	94.10	0.00	95.34	0.01			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.4001518071
96.08	0.01	94.96	0.00	94.10	0.00	95.34	0.01			94.92	0.00	97.55	0.00	99.58	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3231097471

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.358112859
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.324317881
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1617163717
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1338978730
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1045868306
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.834537545
/workspace/coverage/cover_reg_top/0.chip_tl_errors.1605334733
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1913740353
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1879648806
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.749647411
/workspace/coverage/cover_reg_top/0.xbar_error_random.1117643379
/workspace/coverage/cover_reg_top/0.xbar_random.158885699
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2470918724
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3445346413
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1404491058
/workspace/coverage/cover_reg_top/0.xbar_same_source.3373377986
/workspace/coverage/cover_reg_top/0.xbar_smoke.1252070929
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2403679371
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.103132607
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2860185372
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.22161687
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.80985545
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2839172965
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2726961759
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.3022774447
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3016721141
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3859628425
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2346320480
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.440887686
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.4006750998
/workspace/coverage/cover_reg_top/1.chip_tl_errors.2968258724
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.822834349
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.490460090
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3155182109
/workspace/coverage/cover_reg_top/1.xbar_error_random.248480992
/workspace/coverage/cover_reg_top/1.xbar_random.4078454710
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1842739706
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1166299931
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1045921285
/workspace/coverage/cover_reg_top/1.xbar_same_source.990226325
/workspace/coverage/cover_reg_top/1.xbar_smoke.3900457832
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1338581292
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1174353465
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2252554279
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1108049022
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2479400480
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1836379628
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2494479723
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.2347108542
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2297205091
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.57195206
/workspace/coverage/cover_reg_top/10.chip_tl_errors.36428445
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.4034446570
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3657648197
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1185414432
/workspace/coverage/cover_reg_top/10.xbar_error_random.2134671160
/workspace/coverage/cover_reg_top/10.xbar_random.2846583318
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1056570652
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.902858412
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.2986818988
/workspace/coverage/cover_reg_top/10.xbar_same_source.303360229
/workspace/coverage/cover_reg_top/10.xbar_smoke.69862997
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.799889452
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2191469820
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.907572044
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1454854733
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2909630442
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.71338320
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.4047049037
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.232868337
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.982913492
/workspace/coverage/cover_reg_top/11.chip_csr_rw.1376728891
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.349043100
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.754307499
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.970249899
/workspace/coverage/cover_reg_top/11.xbar_error_random.1307635465
/workspace/coverage/cover_reg_top/11.xbar_random.2934287515
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.848662190
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.893326641
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.672508471
/workspace/coverage/cover_reg_top/11.xbar_same_source.348395668
/workspace/coverage/cover_reg_top/11.xbar_smoke.3438664456
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1953539888
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.642136654
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3503668526
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1859722964
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1629101786
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.82830730
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.135791754
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.167291748
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.337434591
/workspace/coverage/cover_reg_top/12.chip_csr_rw.2945954421
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.889546843
/workspace/coverage/cover_reg_top/12.chip_tl_errors.3434919882
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3544645571
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.4263757731
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.714239969
/workspace/coverage/cover_reg_top/12.xbar_error_random.109460674
/workspace/coverage/cover_reg_top/12.xbar_random.3997503976
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3865994645
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.4287980741
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.453149327
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/workspace/coverage/default/97.chip_sw_all_escalation_resets.750378913
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/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4235979012
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.130494728

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Total test records in report: 2934

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---

TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/2.chip_sival_flash_info_access.2205916178			Aug 18 06:59:23 PM PDT 24	Aug 18 07:06:04 PM PDT 24	3386351188 ps
T2	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.749570162			Aug 18 06:58:19 PM PDT 24	Aug 18 07:06:39 PM PDT 24	4408454688 ps
T3	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.95633133			Aug 18 06:54:05 PM PDT 24	Aug 18 07:02:12 PM PDT 24	6922340490 ps
T46	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.961331937			Aug 18 07:05:35 PM PDT 24	Aug 18 08:22:58 PM PDT 24	15776590020 ps
T47	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1061245199			Aug 18 07:01:41 PM PDT 24	Aug 18 08:06:20 PM PDT 24	15420098960 ps
T88	/workspace/coverage/default/0.chip_sw_aes_idle.2504163785			Aug 18 06:56:28 PM PDT 24	Aug 18 06:59:40 PM PDT 24	2745241000 ps
T66	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3240122163			Aug 18 07:20:29 PM PDT 24	Aug 18 07:27:33 PM PDT 24	4225420110 ps
T51	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3448995426			Aug 18 06:52:52 PM PDT 24	Aug 18 06:54:40 PM PDT 24	1774040433 ps
T30	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2910514539			Aug 18 07:14:10 PM PDT 24	Aug 18 07:27:46 PM PDT 24	6609172730 ps
T89	/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.117708380			Aug 18 07:11:13 PM PDT 24	Aug 18 07:13:43 PM PDT 24	3150778660 ps
T163	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.595194893			Aug 18 07:17:33 PM PDT 24	Aug 18 07:24:41 PM PDT 24	3763984510 ps
T31	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2436348781			Aug 18 06:54:53 PM PDT 24	Aug 18 07:04:46 PM PDT 24	5853465160 ps
T118	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.255104166			Aug 18 06:58:29 PM PDT 24	Aug 18 08:08:48 PM PDT 24	18990048122 ps
T202	/workspace/coverage/default/0.chip_sw_pattgen_ios.284701068			Aug 18 06:55:41 PM PDT 24	Aug 18 07:01:00 PM PDT 24	2802605520 ps
T13	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.284759949			Aug 18 07:12:41 PM PDT 24	Aug 18 07:21:09 PM PDT 24	3977982800 ps
T135	/workspace/coverage/default/0.chip_sw_otbn_smoketest.563963083			Aug 18 06:59:06 PM PDT 24	Aug 18 07:18:12 PM PDT 24	5831146340 ps
T130	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2589654016			Aug 18 06:55:00 PM PDT 24	Aug 18 07:01:16 PM PDT 24	6649832198 ps
T132	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1570048418			Aug 18 06:55:08 PM PDT 24	Aug 18 07:06:43 PM PDT 24	3288898552 ps
T263	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3952489197			Aug 18 06:57:45 PM PDT 24	Aug 18 07:02:15 PM PDT 24	3374557550 ps
T32	/workspace/coverage/default/49.chip_sw_all_escalation_resets.2750550414			Aug 18 07:18:22 PM PDT 24	Aug 18 07:27:41 PM PDT 24	5267621660 ps
T68	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.205656009			Aug 18 07:05:55 PM PDT 24	Aug 18 07:40:08 PM PDT 24	11842224188 ps
T131	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3229408881			Aug 18 06:54:46 PM PDT 24	Aug 18 07:07:39 PM PDT 24	8626383750 ps
T126	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1689271324			Aug 18 06:58:24 PM PDT 24	Aug 18 07:06:20 PM PDT 24	5061934143 ps
T4	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3477105224			Aug 18 07:05:09 PM PDT 24	Aug 18 07:18:50 PM PDT 24	10110410600 ps
T267	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1732825754			Aug 18 07:14:18 PM PDT 24	Aug 18 08:52:19 PM PDT 24	27259728332 ps
T264	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.480347040			Aug 18 07:12:48 PM PDT 24	Aug 18 07:18:59 PM PDT 24	2907859006 ps
T199	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1829264180			Aug 18 07:06:45 PM PDT 24	Aug 18 07:16:45 PM PDT 24	7836421832 ps
T5	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1949801273			Aug 18 07:03:27 PM PDT 24	Aug 18 08:46:07 PM PDT 24	48213264520 ps
T189	/workspace/coverage/default/42.chip_sw_all_escalation_resets.3625839843			Aug 18 07:17:58 PM PDT 24	Aug 18 07:27:09 PM PDT 24	4983251060 ps
T200	/workspace/coverage/default/62.chip_sw_all_escalation_resets.1723910103			Aug 18 07:20:20 PM PDT 24	Aug 18 07:29:42 PM PDT 24	4692659440 ps
T6	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.4243031623			Aug 18 07:01:18 PM PDT 24	Aug 18 07:12:30 PM PDT 24	9596985032 ps
T121	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1720094410			Aug 18 06:59:47 PM PDT 24	Aug 18 07:04:33 PM PDT 24	3381607545 ps
T127	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1160578859			Aug 18 07:14:04 PM PDT 24	Aug 18 07:47:13 PM PDT 24	12890568147 ps
T716	/workspace/coverage/default/2.chip_sw_aes_entropy.1786439760			Aug 18 07:07:01 PM PDT 24	Aug 18 07:12:04 PM PDT 24	3377617228 ps
T14	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.967817741			Aug 18 07:01:48 PM PDT 24	Aug 18 07:36:23 PM PDT 24	8286720114 ps
T184	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.426600493			Aug 18 06:59:56 PM PDT 24	Aug 18 07:07:21 PM PDT 24	3352943537 ps
T332	/workspace/coverage/default/38.chip_sw_all_escalation_resets.232854418			Aug 18 07:19:42 PM PDT 24	Aug 18 07:31:58 PM PDT 24	6136680900 ps
T368	/workspace/coverage/default/81.chip_sw_all_escalation_resets.2780096149			Aug 18 07:21:20 PM PDT 24	Aug 18 07:30:23 PM PDT 24	3983837168 ps
T15	/workspace/coverage/default/2.chip_sw_gpio_smoketest.4242233847			Aug 18 07:12:53 PM PDT 24	Aug 18 07:18:07 PM PDT 24	3318735061 ps
T227	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1163681502			Aug 18 07:05:14 PM PDT 24	Aug 18 07:18:29 PM PDT 24	4018579688 ps
T251	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.854281869			Aug 18 06:51:46 PM PDT 24	Aug 18 06:58:39 PM PDT 24	4547166840 ps
T48	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.418553367			Aug 18 07:03:18 PM PDT 24	Aug 18 08:10:00 PM PDT 24	15134669594 ps
T252	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1567713985			Aug 18 06:55:40 PM PDT 24	Aug 18 07:03:33 PM PDT 24	5150800168 ps
T415	/workspace/coverage/default/39.chip_sw_all_escalation_resets.1666832360			Aug 18 07:16:51 PM PDT 24	Aug 18 07:26:31 PM PDT 24	6487100340 ps
T49	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.326756222			Aug 18 06:54:51 PM PDT 24	Aug 18 07:05:12 PM PDT 24	5123546056 ps
T158	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3611727483			Aug 18 06:56:17 PM PDT 24	Aug 18 07:05:32 PM PDT 24	5063573638 ps
T386	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3231097471			Aug 18 06:58:42 PM PDT 24	Aug 18 08:31:58 PM PDT 24	23846549900 ps
T226	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.154794132			Aug 18 06:52:08 PM PDT 24	Aug 18 06:59:55 PM PDT 24	3703182544 ps
T268	/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3644831063			Aug 18 07:16:25 PM PDT 24	Aug 18 08:13:41 PM PDT 24	16112553960 ps
T50	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2965543150			Aug 18 06:53:59 PM PDT 24	Aug 18 09:46:59 PM PDT 24	59608497320 ps
T19	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1004307564			Aug 18 07:07:35 PM PDT 24	Aug 18 07:13:53 PM PDT 24	3221300533 ps
T224	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3179586095			Aug 18 06:56:59 PM PDT 24	Aug 18 07:08:08 PM PDT 24	4647024008 ps
T319	/workspace/coverage/default/23.chip_sw_all_escalation_resets.470160699			Aug 18 07:18:00 PM PDT 24	Aug 18 07:30:01 PM PDT 24	5443644796 ps
T900	/workspace/coverage/default/2.chip_sw_csrng_smoketest.2299578283			Aug 18 07:11:55 PM PDT 24	Aug 18 07:16:34 PM PDT 24	3348088566 ps
T729	/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.867777109			Aug 18 07:07:37 PM PDT 24	Aug 18 07:35:53 PM PDT 24	8171515736 ps
T433	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2119266436			Aug 18 06:59:04 PM PDT 24	Aug 18 07:03:45 PM PDT 24	3421703530 ps
T409	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.332430002			Aug 18 06:54:56 PM PDT 24	Aug 18 07:14:56 PM PDT 24	5511333540 ps
T901	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3229374824			Aug 18 07:03:41 PM PDT 24	Aug 18 07:13:23 PM PDT 24	4937144696 ps
T320	/workspace/coverage/default/2.chip_plic_all_irqs_20.4240699983			Aug 18 07:09:33 PM PDT 24	Aug 18 07:19:55 PM PDT 24	4103756956 ps
T171	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.4069436260			Aug 18 06:53:57 PM PDT 24	Aug 18 07:02:15 PM PDT 24	4791563173 ps
T67	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.92120732			Aug 18 07:02:59 PM PDT 24	Aug 18 07:16:38 PM PDT 24	11723227537 ps
T154	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.179065279			Aug 18 07:06:25 PM PDT 24	Aug 18 08:05:11 PM PDT 24	17047533304 ps
T84	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2866862781			Aug 18 07:07:32 PM PDT 24	Aug 18 07:33:39 PM PDT 24	12994050096 ps
T902	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.2120518731			Aug 18 07:02:11 PM PDT 24	Aug 18 07:06:19 PM PDT 24	3003716024 ps
T125	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2190583520			Aug 18 06:54:14 PM PDT 24	Aug 18 06:56:29 PM PDT 24	2598958429 ps
T122	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3943576307			Aug 18 06:55:35 PM PDT 24	Aug 18 07:01:43 PM PDT 24	3724924960 ps
T43	/workspace/coverage/default/1.rom_e2e_shutdown_output.1425687638			Aug 18 07:04:50 PM PDT 24	Aug 18 08:04:14 PM PDT 24	24154296143 ps
T44	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.552582406			Aug 18 07:05:15 PM PDT 24	Aug 18 07:59:45 PM PDT 24	14905892658 ps
T365	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3010976303			Aug 18 07:16:10 PM PDT 24	Aug 18 07:26:02 PM PDT 24	4405603872 ps
T148	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.284550416			Aug 18 06:52:58 PM PDT 24	Aug 18 06:57:22 PM PDT 24	2596283188 ps
T181	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1580012472			Aug 18 07:11:28 PM PDT 24	Aug 18 07:15:42 PM PDT 24	2167217794 ps
T176	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2221416950			Aug 18 07:14:56 PM PDT 24	Aug 18 07:30:04 PM PDT 24	11950902713 ps
T309	/workspace/coverage/default/2.chip_sw_kmac_smoketest.1977961028			Aug 18 07:12:59 PM PDT 24	Aug 18 07:18:15 PM PDT 24	2902592920 ps
T310	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2851085661			Aug 18 06:53:23 PM PDT 24	Aug 18 07:00:10 PM PDT 24	2712218136 ps
T311	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1760640697			Aug 18 07:00:31 PM PDT 24	Aug 18 08:09:03 PM PDT 24	16087790080 ps
T312	/workspace/coverage/default/58.chip_sw_all_escalation_resets.336927321			Aug 18 07:18:36 PM PDT 24	Aug 18 07:28:56 PM PDT 24	4543971140 ps
T313	/workspace/coverage/default/1.chip_sw_hmac_oneshot.802529223			Aug 18 06:56:01 PM PDT 24	Aug 18 07:02:16 PM PDT 24	3218096448 ps
T153	/workspace/coverage/default/0.chip_sw_power_idle_load.4001518071			Aug 18 06:54:46 PM PDT 24	Aug 18 07:06:01 PM PDT 24	4451158992 ps
T314	/workspace/coverage/default/2.chip_sw_otbn_smoketest.222826507			Aug 18 07:13:15 PM PDT 24	Aug 18 07:30:24 PM PDT 24	6062557350 ps
T315	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3560255220			Aug 18 07:05:48 PM PDT 24	Aug 18 07:16:01 PM PDT 24	5084817948 ps
T903	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2000625649			Aug 18 07:06:26 PM PDT 24	Aug 18 07:20:03 PM PDT 24	7111589120 ps
T167	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1171421544			Aug 18 06:56:49 PM PDT 24	Aug 18 06:58:43 PM PDT 24	2617749626 ps
T45	/workspace/coverage/default/2.rom_e2e_shutdown_output.975828342			Aug 18 07:16:25 PM PDT 24	Aug 18 08:14:43 PM PDT 24	27389627730 ps
T681	/workspace/coverage/default/1.chip_sw_edn_sw_mode.3135788237			Aug 18 06:56:32 PM PDT 24	Aug 18 07:26:55 PM PDT 24	8457787544 ps
T904	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.867356104			Aug 18 06:56:59 PM PDT 24	Aug 18 07:01:40 PM PDT 24	3065468504 ps
T133	/workspace/coverage/default/2.chip_sw_edn_boot_mode.1915526196			Aug 18 07:08:03 PM PDT 24	Aug 18 07:17:18 PM PDT 24	3108039140 ps
T356	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1482989445			Aug 18 06:57:55 PM PDT 24	Aug 18 07:10:10 PM PDT 24	5137350121 ps
T16	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3129791704			Aug 18 06:57:05 PM PDT 24	Aug 18 07:32:25 PM PDT 24	24928680184 ps
T105	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3744058297			Aug 18 07:04:54 PM PDT 24	Aug 18 08:24:30 PM PDT 24	45583263707 ps
T106	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.4159551445			Aug 18 07:10:40 PM PDT 24	Aug 18 07:15:23 PM PDT 24	3053294652 ps
T107	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3779804275			Aug 18 07:00:26 PM PDT 24	Aug 18 08:07:01 PM PDT 24	14121863765 ps
T108	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1574245263			Aug 18 06:56:09 PM PDT 24	Aug 18 07:06:35 PM PDT 24	4666540700 ps
T109	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2300181162			Aug 18 07:05:49 PM PDT 24	Aug 18 07:11:14 PM PDT 24	2562865199 ps
T110	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.85487946			Aug 18 06:54:19 PM PDT 24	Aug 18 07:00:12 PM PDT 24	3891865542 ps
T111	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2043036614			Aug 18 06:52:51 PM PDT 24	Aug 18 07:04:25 PM PDT 24	5090778536 ps
T112	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.4058562381			Aug 18 07:06:29 PM PDT 24	Aug 18 07:10:37 PM PDT 24	3061226345 ps
T113	/workspace/coverage/default/99.chip_sw_all_escalation_resets.2748006468			Aug 18 07:21:31 PM PDT 24	Aug 18 07:30:31 PM PDT 24	5281356160 ps
T391	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.4110791426			Aug 18 07:10:11 PM PDT 24	Aug 18 07:18:46 PM PDT 24	5185861464 ps
T407	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.959208219			Aug 18 06:53:29 PM PDT 24	Aug 18 06:59:40 PM PDT 24	2988281260 ps
T134	/workspace/coverage/default/1.chip_sw_edn_boot_mode.237401395			Aug 18 06:59:01 PM PDT 24	Aug 18 07:08:22 PM PDT 24	3100518984 ps
T192	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1326877401			Aug 18 06:56:24 PM PDT 24	Aug 18 07:07:52 PM PDT 24	6121907359 ps
T527	/workspace/coverage/default/63.chip_sw_all_escalation_resets.611943440			Aug 18 07:19:24 PM PDT 24	Aug 18 07:30:33 PM PDT 24	5378629008 ps
T182	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.792466026			Aug 18 06:52:05 PM PDT 24	Aug 18 07:05:44 PM PDT 24	6945159678 ps
T905	/workspace/coverage/default/1.chip_sw_csrng_smoketest.3023603891			Aug 18 06:57:08 PM PDT 24	Aug 18 06:59:52 PM PDT 24	2641724440 ps
T906	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.4045451413			Aug 18 07:04:49 PM PDT 24	Aug 18 08:00:39 PM PDT 24	11008368981 ps
T193	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.319662482			Aug 18 07:14:27 PM PDT 24	Aug 18 07:29:49 PM PDT 24	12000804280 ps
T241	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1834272049			Aug 18 07:10:29 PM PDT 24	Aug 18 07:42:33 PM PDT 24	22504865552 ps
T175	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1694168477			Aug 18 06:55:34 PM PDT 24	Aug 18 08:21:13 PM PDT 24	47590015816 ps
T72	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2408928492			Aug 18 07:09:56 PM PDT 24	Aug 18 07:16:25 PM PDT 24	4359991224 ps
T429	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2664172636			Aug 18 06:57:04 PM PDT 24	Aug 18 07:08:42 PM PDT 24	6876471287 ps
T24	/workspace/coverage/default/1.chip_sw_gpio.81852934			Aug 18 06:59:42 PM PDT 24	Aug 18 07:08:04 PM PDT 24	4786419742 ps
T430	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2418807820			Aug 18 06:55:17 PM PDT 24	Aug 18 06:58:55 PM PDT 24	3069342620 ps
T397	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3666481932			Aug 18 06:57:52 PM PDT 24	Aug 18 07:07:20 PM PDT 24	6369092220 ps
T383	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.175982295			Aug 18 07:16:18 PM PDT 24	Aug 18 07:24:15 PM PDT 24	3340247788 ps
T346	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2000144617			Aug 18 07:14:01 PM PDT 24	Aug 18 07:20:00 PM PDT 24	2482810596 ps
T253	/workspace/coverage/default/12.chip_sw_all_escalation_resets.1080995086			Aug 18 07:15:50 PM PDT 24	Aug 18 07:26:36 PM PDT 24	5545734392 ps
T302	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4019991959			Aug 18 07:19:34 PM PDT 24	Aug 18 07:27:08 PM PDT 24	4445064720 ps
T221	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1917247171			Aug 18 07:17:02 PM PDT 24	Aug 18 07:22:24 PM PDT 24	3393500974 ps
T7	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.307752088			Aug 18 06:51:57 PM PDT 24	Aug 18 06:55:57 PM PDT 24	3051279046 ps
T303	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2750683560			Aug 18 06:53:10 PM PDT 24	Aug 18 07:00:04 PM PDT 24	4880699800 ps
T304	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.1411667854			Aug 18 07:01:53 PM PDT 24	Aug 18 07:58:02 PM PDT 24	11110133550 ps
T136	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3294906370			Aug 18 07:09:24 PM PDT 24	Aug 18 07:17:10 PM PDT 24	5336422810 ps
T17	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1262241871			Aug 18 06:58:17 PM PDT 24	Aug 18 07:08:05 PM PDT 24	7100505162 ps
T305	/workspace/coverage/default/0.chip_sw_example_rom.739684935			Aug 18 06:52:45 PM PDT 24	Aug 18 06:54:34 PM PDT 24	2715814840 ps
T73	/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2844544924			Aug 18 06:56:57 PM PDT 24	Aug 18 07:43:39 PM PDT 24	32140593645 ps
T907	/workspace/coverage/default/0.chip_sw_csrng_kat_test.963254621			Aug 18 06:56:48 PM PDT 24	Aug 18 07:00:48 PM PDT 24	2540857880 ps
T359	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1108558550			Aug 18 06:55:17 PM PDT 24	Aug 18 06:59:07 PM PDT 24	2954964444 ps
T680	/workspace/coverage/default/2.chip_sw_aes_masking_off.1848958321			Aug 18 07:07:07 PM PDT 24	Aug 18 07:12:49 PM PDT 24	3073403540 ps
T162	/workspace/coverage/default/77.chip_sw_all_escalation_resets.3730119659			Aug 18 07:22:40 PM PDT 24	Aug 18 07:30:27 PM PDT 24	4552468904 ps
T74	/workspace/coverage/default/1.chip_jtag_csr_rw.2638124778			Aug 18 06:44:50 PM PDT 24	Aug 18 07:21:23 PM PDT 24	18738054202 ps
T438	/workspace/coverage/default/0.chip_sw_kmac_entropy.2380007042			Aug 18 06:54:46 PM PDT 24	Aug 18 06:58:54 PM PDT 24	2404860088 ps
T908	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.890819938			Aug 18 07:09:03 PM PDT 24	Aug 18 07:16:47 PM PDT 24	5295187134 ps
T248	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1213350917			Aug 18 06:53:28 PM PDT 24	Aug 18 07:04:09 PM PDT 24	5041104106 ps
T275	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.508088901			Aug 18 06:58:36 PM PDT 24	Aug 18 07:17:26 PM PDT 24	7028661292 ps
T123	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3068774727			Aug 18 07:10:57 PM PDT 24	Aug 18 07:28:18 PM PDT 24	7187387827 ps
T276	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.185017617			Aug 18 07:18:42 PM PDT 24	Aug 18 07:26:42 PM PDT 24	4093538912 ps
T277	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1542522028			Aug 18 07:19:55 PM PDT 24	Aug 18 07:27:54 PM PDT 24	3692488728 ps
T278	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2595246283			Aug 18 06:54:12 PM PDT 24	Aug 18 07:06:10 PM PDT 24	5189271151 ps
T279	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3826140138			Aug 18 07:02:51 PM PDT 24	Aug 18 07:12:22 PM PDT 24	3734028746 ps
T128	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1942819170			Aug 18 06:59:08 PM PDT 24	Aug 18 07:12:14 PM PDT 24	4271817840 ps
T280	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3138892254			Aug 18 07:17:38 PM PDT 24	Aug 18 07:23:06 PM PDT 24	3993912818 ps
T281	/workspace/coverage/default/97.chip_sw_all_escalation_resets.750378913			Aug 18 07:21:12 PM PDT 24	Aug 18 07:30:18 PM PDT 24	3915579850 ps
T683	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2581923465			Aug 18 07:18:29 PM PDT 24	Aug 18 07:25:19 PM PDT 24	3483013284 ps
T435	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.833338824			Aug 18 07:11:52 PM PDT 24	Aug 18 07:17:31 PM PDT 24	3402418470 ps
T739	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3449955894			Aug 18 07:19:00 PM PDT 24	Aug 18 07:25:58 PM PDT 24	3742211808 ps
T370	/workspace/coverage/default/28.chip_sw_all_escalation_resets.1931423064			Aug 18 07:15:03 PM PDT 24	Aug 18 07:24:44 PM PDT 24	4852085520 ps
T69	/workspace/coverage/default/4.chip_tap_straps_rma.4186953589			Aug 18 07:13:04 PM PDT 24	Aug 18 07:15:40 PM PDT 24	2551473050 ps
T412	/workspace/coverage/default/2.chip_sw_kmac_app_rom.7125648			Aug 18 07:07:58 PM PDT 24	Aug 18 07:12:45 PM PDT 24	3088505852 ps
T909	/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3009388566			Aug 18 06:57:42 PM PDT 24	Aug 18 07:01:29 PM PDT 24	2058283368 ps
T228	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1297856719			Aug 18 06:55:37 PM PDT 24	Aug 18 07:26:47 PM PDT 24	7743362210 ps
T910	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1610686198			Aug 18 07:13:01 PM PDT 24	Aug 18 07:32:37 PM PDT 24	6142582070 ps
T223	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.190293388			Aug 18 07:00:53 PM PDT 24	Aug 18 07:16:48 PM PDT 24	5487449250 ps
T911	/workspace/coverage/default/2.chip_sw_edn_sw_mode.3832917090			Aug 18 07:07:37 PM PDT 24	Aug 18 07:42:22 PM PDT 24	10189112180 ps
T345	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3048117792			Aug 18 06:54:11 PM PDT 24	Aug 18 07:10:06 PM PDT 24	5246115890 ps
T52	/workspace/coverage/default/2.chip_sw_alert_test.2278577513			Aug 18 07:07:03 PM PDT 24	Aug 18 07:12:04 PM PDT 24	3480903384 ps
T912	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2214216182			Aug 18 06:56:47 PM PDT 24	Aug 18 07:09:38 PM PDT 24	5564116216 ps
T129	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1240494388			Aug 18 06:51:01 PM PDT 24	Aug 18 06:59:58 PM PDT 24	4260739192 ps
T913	/workspace/coverage/default/2.chip_sw_edn_kat.1418899638			Aug 18 07:07:53 PM PDT 24	Aug 18 07:17:41 PM PDT 24	3724422916 ps
T321	/workspace/coverage/default/3.chip_sw_uart_tx_rx.3636285488			Aug 18 07:13:20 PM PDT 24	Aug 18 07:25:00 PM PDT 24	4349075944 ps
T749	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1379160579			Aug 18 07:21:08 PM PDT 24	Aug 18 07:30:03 PM PDT 24	3637192792 ps
T914	/workspace/coverage/default/2.chip_sw_csrng_kat_test.4276675726			Aug 18 07:07:20 PM PDT 24	Aug 18 07:11:38 PM PDT 24	2537644830 ps
T915	/workspace/coverage/default/1.chip_sw_otbn_smoketest.1230805605			Aug 18 06:59:19 PM PDT 24	Aug 18 07:44:20 PM PDT 24	9539852072 ps
T796	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3912082766			Aug 18 07:16:18 PM PDT 24	Aug 18 07:26:41 PM PDT 24	4136351488 ps
T794	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.968337988			Aug 18 07:24:16 PM PDT 24	Aug 18 07:30:17 PM PDT 24	3828178630 ps
T801	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.935614491			Aug 18 07:20:18 PM PDT 24	Aug 18 07:27:01 PM PDT 24	3397964428 ps
T825	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.969070224			Aug 18 07:21:27 PM PDT 24	Aug 18 07:27:32 PM PDT 24	3649953150 ps
T916	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3083541633			Aug 18 07:10:21 PM PDT 24	Aug 18 07:16:45 PM PDT 24	6612204134 ps
T371	/workspace/coverage/default/4.chip_sw_all_escalation_resets.2974657732			Aug 18 07:13:29 PM PDT 24	Aug 18 07:24:12 PM PDT 24	4550877740 ps
T246	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.4070960737			Aug 18 07:11:39 PM PDT 24	Aug 18 07:21:52 PM PDT 24	5133581112 ps
T294	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.848910206			Aug 18 07:20:47 PM PDT 24	Aug 18 07:28:09 PM PDT 24	3773439040 ps
T295	/workspace/coverage/default/2.chip_sw_uart_tx_rx.1026803370			Aug 18 07:02:53 PM PDT 24	Aug 18 07:13:46 PM PDT 24	4239086860 ps
T296	/workspace/coverage/default/1.chip_sw_example_concurrency.821042855			Aug 18 06:57:00 PM PDT 24	Aug 18 07:02:41 PM PDT 24	2512147560 ps
T297	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1405920315			Aug 18 07:00:56 PM PDT 24	Aug 18 07:29:27 PM PDT 24	7649000874 ps
T260	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.566893662			Aug 18 07:11:15 PM PDT 24	Aug 18 07:15:19 PM PDT 24	3326357000 ps
T298	/workspace/coverage/default/1.chip_sw_aes_masking_off.1275702751			Aug 18 06:59:03 PM PDT 24	Aug 18 07:04:42 PM PDT 24	2736411100 ps
T299	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1490370220			Aug 18 07:15:54 PM PDT 24	Aug 18 07:21:40 PM PDT 24	3904529000 ps
T300	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.671605800			Aug 18 07:15:20 PM PDT 24	Aug 18 07:21:58 PM PDT 24	5247475679 ps
T301	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3304822072			Aug 18 06:57:26 PM PDT 24	Aug 18 07:18:34 PM PDT 24	5389413294 ps
T721	/workspace/coverage/default/0.chip_sw_hmac_multistream.991613620			Aug 18 06:57:59 PM PDT 24	Aug 18 07:33:54 PM PDT 24	7861965128 ps
T361	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2338254619			Aug 18 07:11:08 PM PDT 24	Aug 18 07:14:49 PM PDT 24	3611131170 ps
T834	/workspace/coverage/default/2.chip_sw_all_escalation_resets.2124102573			Aug 18 07:01:22 PM PDT 24	Aug 18 07:11:57 PM PDT 24	5558874800 ps
T119	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3338279353			Aug 18 06:57:48 PM PDT 24	Aug 18 08:13:12 PM PDT 24	24812755658 ps
T720	/workspace/coverage/default/89.chip_sw_all_escalation_resets.1983974349			Aug 18 07:21:14 PM PDT 24	Aug 18 07:30:12 PM PDT 24	5760913992 ps
T396	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3692043106			Aug 18 07:16:23 PM PDT 24	Aug 18 07:23:49 PM PDT 24	3752980976 ps
T261	/workspace/coverage/default/2.chip_sw_rv_timer_irq.2218361280			Aug 18 07:04:56 PM PDT 24	Aug 18 07:09:28 PM PDT 24	2593445164 ps
T917	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2459254348			Aug 18 06:59:51 PM PDT 24	Aug 18 07:04:47 PM PDT 24	3264263699 ps
T918	/workspace/coverage/default/2.chip_sw_hmac_multistream.5501042			Aug 18 07:07:36 PM PDT 24	Aug 18 07:39:12 PM PDT 24	7646607416 ps
T744	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.617951775			Aug 18 07:00:50 PM PDT 24	Aug 18 07:08:44 PM PDT 24	5960792264 ps
T372	/workspace/coverage/default/64.chip_sw_all_escalation_resets.4108045658			Aug 18 07:20:29 PM PDT 24	Aug 18 07:30:07 PM PDT 24	5324420870 ps
T249	/workspace/coverage/default/76.chip_sw_all_escalation_resets.4059455968			Aug 18 07:20:50 PM PDT 24	Aug 18 07:32:59 PM PDT 24	5467337750 ps
T229	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3169640416			Aug 18 07:03:18 PM PDT 24	Aug 18 07:31:07 PM PDT 24	8644668428 ps
T120	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.4094013390			Aug 18 06:56:54 PM PDT 24	Aug 18 07:30:37 PM PDT 24	9309146389 ps
T764	/workspace/coverage/default/96.chip_sw_all_escalation_resets.3722430246			Aug 18 07:21:06 PM PDT 24	Aug 18 07:30:55 PM PDT 24	5208611912 ps
T220	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2566558406			Aug 18 07:03:28 PM PDT 24	Aug 18 07:06:24 PM PDT 24	2186915672 ps
T369	/workspace/coverage/default/87.chip_sw_all_escalation_resets.4043703707			Aug 18 07:20:46 PM PDT 24	Aug 18 07:30:00 PM PDT 24	4322280410 ps
T124	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2954795524			Aug 18 07:08:59 PM PDT 24	Aug 18 07:29:25 PM PDT 24	6240122487 ps
T919	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2647509437			Aug 18 07:12:21 PM PDT 24	Aug 18 07:21:44 PM PDT 24	4139374706 ps
T366	/workspace/coverage/default/2.chip_sw_pattgen_ios.2513120976			Aug 18 06:58:54 PM PDT 24	Aug 18 07:03:29 PM PDT 24	3411446744 ps
T116	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.681725664			Aug 18 06:53:53 PM PDT 24	Aug 18 10:19:31 PM PDT 24	84268891919 ps
T262	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2394051046			Aug 18 06:52:11 PM PDT 24	Aug 18 06:54:57 PM PDT 24	2267137544 ps
T920	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3671089490			Aug 18 07:01:32 PM PDT 24	Aug 18 07:08:40 PM PDT 24	3733132744 ps
T921	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2910384413			Aug 18 06:54:15 PM PDT 24	Aug 18 07:55:58 PM PDT 24	16698791512 ps
T718	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3088392335			Aug 18 07:00:26 PM PDT 24	Aug 18 07:24:34 PM PDT 24	9419307256 ps
T792	/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.628900302			Aug 18 07:17:05 PM PDT 24	Aug 18 07:23:29 PM PDT 24	3816938652 ps
T922	/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2482500107			Aug 18 07:14:49 PM PDT 24	Aug 18 07:30:21 PM PDT 24	12456128150 ps
T10	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3561363122			Aug 18 06:53:48 PM PDT 24	Aug 18 07:03:28 PM PDT 24	4653993265 ps
T923	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4280200601			Aug 18 06:57:28 PM PDT 24	Aug 18 07:08:25 PM PDT 24	4155517200 ps
T362	/workspace/coverage/default/1.chip_sw_hmac_enc.285856953			Aug 18 06:58:16 PM PDT 24	Aug 18 07:02:59 PM PDT 24	3144811080 ps
T63	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1967627271			Aug 18 07:01:18 PM PDT 24	Aug 18 07:11:04 PM PDT 24	6676624224 ps
T924	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2003403417			Aug 18 07:07:37 PM PDT 24	Aug 18 07:12:24 PM PDT 24	2981698379 ps
T742	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3761213681			Aug 18 07:20:05 PM PDT 24	Aug 18 07:25:20 PM PDT 24	3452050650 ps
T230	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3856679625			Aug 18 06:59:01 PM PDT 24	Aug 18 07:20:34 PM PDT 24	6903896258 ps
T925	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.355944111			Aug 18 06:59:03 PM PDT 24	Aug 18 07:02:20 PM PDT 24	2349517196 ps
T225	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3237929182			Aug 18 07:12:33 PM PDT 24	Aug 18 07:23:14 PM PDT 24	4506807170 ps
T352	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1151924235			Aug 18 06:55:51 PM PDT 24	Aug 18 07:21:56 PM PDT 24	9995523756 ps
T140	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3622960406			Aug 18 07:09:41 PM PDT 24	Aug 18 07:29:33 PM PDT 24	9359638456 ps
T722	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3387892066			Aug 18 07:18:41 PM PDT 24	Aug 18 07:24:54 PM PDT 24	3190852428 ps
T824	/workspace/coverage/default/70.chip_sw_all_escalation_resets.3156847713			Aug 18 07:20:04 PM PDT 24	Aug 18 07:29:47 PM PDT 24	4881980134 ps
T926	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.3522170550			Aug 18 06:56:11 PM PDT 24	Aug 18 07:01:15 PM PDT 24	2537580658 ps
T364	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3430973033			Aug 18 07:15:51 PM PDT 24	Aug 18 07:41:46 PM PDT 24	8553494750 ps
T738	/workspace/coverage/default/6.chip_sw_all_escalation_resets.3584687589			Aug 18 07:14:22 PM PDT 24	Aug 18 07:25:29 PM PDT 24	5100473320 ps
T247	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3300192810			Aug 18 06:57:05 PM PDT 24	Aug 18 07:04:36 PM PDT 24	2951908170 ps
T384	/workspace/coverage/default/18.chip_sw_all_escalation_resets.2082078186			Aug 18 07:15:36 PM PDT 24	Aug 18 07:28:09 PM PDT 24	5502456104 ps
T20	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.350957014			Aug 18 06:52:58 PM PDT 24	Aug 18 07:20:33 PM PDT 24	21575533028 ps
T927	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1151173682			Aug 18 07:01:17 PM PDT 24	Aug 18 07:12:55 PM PDT 24	4734585150 ps
T244	/workspace/coverage/default/2.chip_sw_flash_init.3489214463			Aug 18 07:01:54 PM PDT 24	Aug 18 07:32:40 PM PDT 24	17732452248 ps
T347	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2803604333			Aug 18 07:14:28 PM PDT 24	Aug 18 07:40:02 PM PDT 24	8990649400 ps
T928	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3520818975			Aug 18 07:07:47 PM PDT 24	Aug 18 08:15:13 PM PDT 24	15770001834 ps
T11	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.641991041			Aug 18 07:04:02 PM PDT 24	Aug 18 07:15:21 PM PDT 24	4251584454 ps
T70	/workspace/coverage/default/1.chip_tap_straps_rma.2970239498			Aug 18 06:54:44 PM PDT 24	Aug 18 07:04:54 PM PDT 24	7209099265 ps
T756	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2205356946			Aug 18 07:18:53 PM PDT 24	Aug 18 07:26:19 PM PDT 24	3776432392 ps
T782	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1757942876			Aug 18 07:23:48 PM PDT 24	Aug 18 07:29:32 PM PDT 24	3651506862 ps
T179	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1615641641			Aug 18 06:57:02 PM PDT 24	Aug 18 07:07:09 PM PDT 24	5510369803 ps
T284	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1384316493			Aug 18 07:00:15 PM PDT 24	Aug 18 07:07:36 PM PDT 24	8766691215 ps
T929	/workspace/coverage/default/1.chip_sw_edn_kat.1449268354			Aug 18 06:54:56 PM PDT 24	Aug 18 07:05:26 PM PDT 24	3113149800 ps
T930	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3791008751			Aug 18 07:11:02 PM PDT 24	Aug 18 07:16:50 PM PDT 24	2901491490 ps
T931	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2861473719			Aug 18 07:12:45 PM PDT 24	Aug 18 07:18:48 PM PDT 24	2999518600 ps
T682	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3811150326			Aug 18 07:17:50 PM PDT 24	Aug 18 07:25:30 PM PDT 24	3758773824 ps
T743	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2019008087			Aug 18 07:18:16 PM PDT 24	Aug 18 07:25:13 PM PDT 24	3036587720 ps
T338	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1692213073			Aug 18 07:00:37 PM PDT 24	Aug 18 07:12:48 PM PDT 24	4782505576 ps
T932	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1038360943			Aug 18 06:57:03 PM PDT 24	Aug 18 07:15:25 PM PDT 24	5023452718 ps
T933	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.736746217			Aug 18 07:13:58 PM PDT 24	Aug 18 07:25:00 PM PDT 24	7306302173 ps
T231	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.4106823247			Aug 18 06:52:50 PM PDT 24	Aug 18 07:01:03 PM PDT 24	3774251076 ps
T934	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.843654944			Aug 18 06:55:59 PM PDT 24	Aug 18 07:59:54 PM PDT 24	14727010807 ps
T935	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1293049386			Aug 18 06:57:51 PM PDT 24	Aug 18 07:06:51 PM PDT 24	3961989368 ps
T740	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4111820465			Aug 18 07:19:33 PM PDT 24	Aug 18 07:26:44 PM PDT 24	4365482276 ps
T374	/workspace/coverage/default/24.chip_sw_all_escalation_resets.2259016532			Aug 18 07:18:31 PM PDT 24	Aug 18 07:31:09 PM PDT 24	5044289872 ps
T936	/workspace/coverage/default/0.rom_e2e_asm_init_rma.1459680882			Aug 18 07:03:34 PM PDT 24	Aug 18 08:02:33 PM PDT 24	15491060988 ps
T937	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1234248814			Aug 18 07:13:44 PM PDT 24	Aug 18 07:26:02 PM PDT 24	5571781816 ps
T215	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3159334210			Aug 18 06:58:52 PM PDT 24	Aug 18 07:05:20 PM PDT 24	3623553320 ps