Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	148209	1			T80	94		T81	92		T82	3
values[2]	9597	1			T80	1		T155	1		T256	2
values[3]	3608	1			T529	1		T448	1		T565	33
values[4]	2091	1			T529	1		T565	15		T543	1
values[5]	1449	1			T529	1		T565	8		T451	12
values[6]	927	1			T529	1		T451	3		T840	1
values[7]	671	1			T529	1		T451	2		T840	1
values[8]	546	1			T529	1		T840	1		T866	1
values[9]	548	1			T529	1		T840	1		T547	2
values[10]	400	1			T529	1		T840	1		T547	13
values[11]	348	1			T529	1		T840	1		T547	9
values[12]	372	1			T529	1		T840	1		T547	15
values[13]	360	1			T529	1		T840	1		T547	7
values[14]	367	1			T529	1		T840	1		T547	6
values[15]	336	1			T529	1		T840	1		T547	8
values[16]	324	1			T529	1		T840	1		T547	7
values[17]	357	1			T529	1		T840	1		T547	9
values[18]	331	1			T529	1		T840	1		T547	6
values[19]	319	1			T529	1		T840	1		T547	4
values[20]	353	1			T529	1		T840	1		T547	4
values[21]	299	1			T529	2		T840	1		T547	4
values[22]	322	1			T529	1		T840	1		T547	5
values[23]	337	1			T529	1		T840	1		T547	7
values[24]	366	1			T529	1		T840	1		T547	11
values[25]	357	1			T529	1		T840	1		T547	6
values[26]	320	1			T529	1		T840	1		T547	5
values[27]	316	1			T529	1		T840	1		T547	4
values[28]	297	1			T529	2		T840	1		T547	6
values[29]	306	1			T529	1		T840	1		T547	15
values[30]	301	1			T529	1		T840	1		T547	3
values[31]	326	1			T529	1		T840	1		T547	6
values[32]	320	1			T529	1		T840	1		T547	12
values[33]	303	1			T529	1		T840	1		T547	3
values[34]	305	1			T529	1		T840	1		T547	4
values[35]	281	1			T529	1		T840	1		T547	3
values[36]	295	1			T529	1		T840	1		T547	6
values[37]	311	1			T529	1		T840	1		T547	14
values[38]	312	1			T529	1		T840	1		T547	16
values[39]	350	1			T529	1		T840	1		T547	3
values[40]	372	1			T529	1		T840	1		T547	9
values[41]	247	1			T529	1		T840	1		T547	2
values[42]	276	1			T529	2		T840	1		T547	10
values[43]	265	1			T529	1		T840	1		T547	4
values[44]	279	1			T529	1		T840	1		T547	6
values[45]	249	1			T529	1		T840	1		T547	5
values[46]	256	1			T529	1		T840	1		T547	7
values[47]	285	1			T529	2		T840	1		T547	9
values[48]	300	1			T529	1		T840	1		T547	12
values[49]	262	1			T529	1		T840	1		T547	5
values[50]	274	1			T529	1		T840	1		T547	14
values[51]	233	1			T529	1		T840	1		T547	8
values[52]	261	1			T529	1		T840	1		T547	5
values[53]	234	1			T529	1		T840	1		T547	6
values[54]	207	1			T529	1		T840	1		T547	5
values[55]	193	1			T529	1		T840	1		T547	7
values[56]	220	1			T529	1		T840	1		T547	3
values[57]	244	1			T529	1		T840	1		T547	13
values[58]	246	1			T529	1		T840	1		T547	4
values[59]	207	1			T529	1		T840	1		T547	3
values[60]	200	1			T529	1		T840	1		T547	3
values[61]	195	1			T529	1		T840	1		T547	5
values[62]	184	1			T529	1		T840	1		T547	5
values[63]	228	1			T529	1		T840	1		T547	13
values[64]	233	1			T529	1		T840	1		T547	13
values[65]	255	1			T529	1		T840	1		T547	24
values[66]	220	1			T529	1		T840	1		T547	13
values[67]	235	1			T529	1		T840	1		T547	9
values[68]	216	1			T529	1		T840	1		T547	12
values[69]	172	1			T529	1		T840	2		T547	5
values[70]	163	1			T529	1		T840	1		T547	1
values[71]	130	1			T529	1		T840	1		T649	5
values[72]	166	1			T529	1		T840	1		T649	8
values[73]	151	1			T529	1		T840	1		T649	7
values[74]	123	1			T529	1		T840	1		T649	11
values[75]	123	1			T529	1		T840	1		T649	9
values[76]	118	1			T529	1		T840	1		T649	5
values[77]	134	1			T529	1		T840	1		T649	9
values[78]	136	1			T529	1		T840	1		T649	7
values[79]	137	1			T529	1		T840	1		T649	12
values[80]	90	1			T529	1		T840	1		T649	13
values[81]	120	1			T529	1		T840	1		T649	5
values[82]	112	1			T529	1		T840	1		T649	5
values[83]	94	1			T529	1		T840	1		T649	10
values[84]	110	1			T529	1		T840	1		T649	17
values[85]	105	1			T529	1		T840	1		T649	9
values[86]	103	1			T529	1		T840	1		T649	10
values[87]	112	1			T529	1		T840	1		T649	13
values[88]	137	1			T529	1		T840	1		T649	13
values[89]	91	1			T529	1		T840	1		T649	11
values[90]	102	1			T529	1		T840	1		T649	7
values[91]	83	1			T529	1		T840	1		T649	4
values[92]	101	1			T529	1		T840	1		T649	7
values[93]	95	1			T529	1		T840	1		T649	7
values[94]	78	1			T529	1		T840	1		T649	5
values[95]	85	1			T529	1		T840	1		T649	6
values[96]	101	1			T529	1		T840	1		T649	8
values[97]	70	1			T529	1		T840	1		T649	7
values[98]	78	1			T529	1		T840	1		T649	12
values[99]	101	1			T529	1		T840	1		T649	12
values[100]	87	1			T529	1		T840	1		T649	13
values[101]	102	1			T529	1		T840	1		T649	20
values[102]	96	1			T529	1		T840	1		T649	13
values[103]	89	1			T529	1		T840	1		T649	7
values[104]	77	1			T529	1		T840	1		T649	8
values[105]	60	1			T529	1		T840	1		T649	11
values[106]	61	1			T529	1		T840	2		T649	7
values[107]	59	1			T529	1		T840	1		T649	11
values[108]	52	1			T529	1		T840	1		T649	4
values[109]	66	1			T529	1		T840	1		T649	7
values[110]	70	1			T529	1		T840	1		T649	6
values[111]	61	1			T529	1		T840	1		T649	9
values[112]	64	1			T529	1		T840	1		T649	4
values[113]	68	1			T529	1		T840	1		T649	6
values[114]	77	1			T529	1		T840	1		T649	6
values[115]	54	1			T529	1		T840	1		T649	4
values[116]	55	1			T529	1		T840	1		T649	6
values[117]	56	1			T529	1		T840	1		T649	5
values[118]	52	1			T529	1		T840	1		T649	3
values[119]	68	1			T529	1		T840	3		T649	9
values[120]	74	1			T529	1		T840	4		T649	9
values[121]	60	1			T529	1		T840	3		T649	4
values[122]	48	1			T529	1		T840	1		T649	5
values[123]	66	1			T529	1		T840	2		T649	11
values[124]	57	1			T529	1		T840	1		T649	11
values[125]	88	1			T529	1		T840	1		T649	29
values[126]	166	1			T529	2		T840	4		T649	61
values[127]	783	1			T529	25		T840	31		T649	71
values[128]	6215	1			T529	313		T840	301		T649	28