Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	560	1			T752	1		T427	1		T456	1
all_values[1]	515	1			T427	3		T456	3		T504	4
all_values[2]	490	1			T529	2		T427	2		T456	2
all_values[3]	515	1			T529	1		T427	2		T456	2
all_values[4]	516	1			T427	3		T456	2		T504	9
all_values[5]	522	1			T427	3		T504	3		T450	3
all_values[6]	484	1			T427	1		T456	1		T450	1
all_values[7]	501	1			T427	1		T504	2		T450	6
all_values[8]	504	1			T529	1		T427	3		T456	1
all_values[9]	506	1			T427	1		T456	2		T504	6
all_values[10]	518	1			T427	2		T456	1		T504	3
all_values[11]	536	1			T427	4		T456	4		T504	3
all_values[12]	490	1			T529	1		T427	2		T442	1
all_values[13]	497	1			T427	2		T456	1		T448	2
all_values[14]	516	1			T427	1		T456	1		T504	2
all_values[15]	487	1			T427	2		T504	5		T450	2
all_values[16]	518	1			T427	1		T456	2		T504	5
all_values[17]	526	1			T427	2		T456	1		T504	2
all_values[18]	482	1			T427	4		T456	1		T448	1
all_values[19]	422	1			T427	2		T456	1		T442	1
all_values[20]	458	1			T529	2		T456	1		T504	6
all_values[21]	503	1			T427	1		T456	1		T448	1
all_values[22]	483	1			T427	1		T456	2		T504	2
all_values[23]	504	1			T504	6		T450	2		T565	7
all_values[24]	501	1			T427	3		T456	2		T504	4
all_values[25]	491	1			T529	1		T427	2		T456	5
all_values[26]	496	1			T427	2		T504	3		T565	5
all_values[27]	508	1			T427	2		T456	1		T442	1
all_values[28]	504	1			T427	1		T442	1		T448	1
all_values[29]	522	1			T427	2		T456	2		T504	7
all_values[30]	499	1			T529	1		T427	3		T456	3
all_values[31]	498	1			T427	3		T456	1		T442	1
all_values[32]	497	1			T529	1		T427	3		T504	2
all_values[33]	460	1			T427	1		T504	2		T565	3
all_values[34]	512	1			T529	2		T427	3		T456	2
all_values[35]	498	1			T456	2		T504	7		T450	5
all_values[36]	476	1			T456	2		T442	1		T504	2
all_values[37]	488	1			T427	3		T456	1		T504	5
all_values[38]	521	1			T427	1		T456	3		T504	6
all_values[39]	485	1			T529	1		T427	2		T456	3
all_values[40]	527	1			T427	2		T456	4		T504	7
all_values[41]	502	1			T427	3		T456	2		T504	4
all_values[42]	514	1			T529	1		T752	1		T427	2
all_values[43]	490	1			T427	1		T456	1		T504	6
all_values[44]	528	1			T427	2		T456	5		T448	1
all_values[45]	544	1			T529	1		T504	5		T450	3
all_values[46]	480	1			T752	1		T427	2		T456	1
all_values[47]	499	1			T529	1		T427	1		T456	2
all_values[48]	495	1			T427	1		T456	1		T504	3
all_values[49]	538	1			T427	1		T456	2		T442	1