Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3771	1			T80	3		T155	3		T256	2
all_values[1]	3883	1			T80	5		T155	3		T256	2
all_values[2]	3873	1			T80	4		T256	2		T427	20
all_values[3]	3794	1			T80	1		T155	2		T532	2
all_values[4]	3837	1			T80	2		T155	1		T256	3
all_values[5]	3876	1			T80	1		T155	4		T256	2
all_values[6]	3738	1			T80	1		T155	2		T256	3
all_values[7]	3808	1			T80	2		T155	1		T256	1
all_values[8]	3792	1			T80	2		T155	5		T256	3
all_values[9]	3743	1			T80	2		T155	2		T256	4
all_values[10]	3795	1			T80	3		T155	1		T256	1
all_values[11]	3808	1			T80	3		T155	3		T532	1
all_values[12]	3803	1			T80	1		T155	2		T256	1
all_values[13]	3838	1			T80	2		T155	1		T256	5
all_values[14]	3803	1			T80	2		T155	1		T256	4
all_values[15]	3731	1			T155	1		T256	7		T427	19
all_values[16]	3868	1			T80	6		T155	2		T256	2
all_values[17]	3876	1			T80	6		T155	1		T256	2
all_values[18]	3836	1			T80	4		T155	4		T256	2
all_values[19]	3867	1			T80	2		T532	1		T256	6
all_values[20]	3812	1			T80	3		T256	3		T427	14
all_values[21]	3808	1			T155	1		T256	2		T427	19
all_values[22]	3730	1			T80	4		T155	2		T256	4
all_values[23]	3901	1			T80	2		T155	4		T256	3
all_values[24]	3793	1			T80	3		T155	2		T532	1
all_values[25]	3715	1			T80	2		T155	3		T532	2
all_values[26]	3839	1			T80	2		T155	2		T256	7
all_values[27]	3772	1			T80	3		T155	1		T256	2
all_values[28]	3892	1			T80	2		T155	4		T256	2
all_values[29]	3781	1			T80	3		T155	2		T256	4
all_values[30]	3726	1			T80	3		T155	1		T256	3
all_values[31]	3705	1			T80	4		T155	1		T532	1
all_values[32]	3815	1			T80	2		T532	1		T256	3
all_values[33]	3826	1			T80	3		T155	3		T256	1
all_values[34]	3979	1			T80	6		T155	2		T256	3
all_values[35]	3788	1			T80	2		T155	2		T532	1
all_values[36]	3831	1			T80	2		T155	2		T532	1
all_values[37]	3722	1			T80	3		T155	2		T532	1
all_values[38]	3766	1			T80	4		T155	2		T256	5
all_values[39]	3764	1			T80	2		T155	1		T256	5
all_values[40]	3843	1			T80	1		T155	2		T256	7
all_values[41]	3880	1			T80	4		T155	2		T256	2
all_values[42]	3762	1			T80	3		T155	1		T256	4
all_values[43]	3846	1			T80	2		T155	1		T256	4
all_values[44]	3804	1			T80	2		T155	1		T256	4
all_values[45]	3810	1			T80	5		T155	3		T427	20
all_values[46]	3767	1			T80	3		T256	4		T427	16
all_values[47]	3957	1			T80	4		T155	4		T256	1
all_values[48]	3880	1			T80	5		T155	3		T532	1
all_values[49]	3742	1			T80	3		T155	4		T427	17
all_values[50]	3827	1			T80	2		T155	2		T532	1
all_values[51]	3780	1			T80	8		T155	3		T256	4
all_values[52]	3837	1			T80	6		T155	1		T256	2
all_values[53]	3760	1			T80	1		T155	3		T256	3
all_values[54]	3859	1			T155	1		T256	3		T427	17
all_values[55]	3859	1			T80	5		T155	3		T256	2
all_values[56]	3774	1			T80	4		T155	2		T532	2
all_values[57]	3725	1			T80	1		T155	3		T256	2
all_values[58]	3885	1			T80	7		T155	2		T256	2
all_values[59]	3865	1			T80	3		T155	1		T256	5
all_values[60]	3786	1			T80	3		T427	13		T456	17
all_values[61]	3802	1			T80	3		T155	3		T256	4
all_values[62]	3793	1			T80	2		T256	1		T427	13
all_values[63]	3687	1			T80	2		T155	1		T532	1