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 LINE       17880
 EXPRESSION (addr_hit[196] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T66
1	1	0	Covered	T541,T611,T710
1	1	1	Covered	T2,T3,T66

 LINE       17945
 EXPRESSION (addr_hit[197] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T118,T320
1	1	0	Covered	T538,T537,T535
1	1	1	Covered	T1,T118,T320

 LINE       17998
 EXPRESSION (addr_hit[198] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T151,T392,T401
1	1	0	Covered	T541,T539,T669
1	1	1	Covered	T1,T2,T3

 LINE       18001
 EXPRESSION (addr_hit[199] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       18002
 EXPRESSION (addr_hit[199] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T534,T535,T711
1	1	1	Covered	T1,T2,T3

 LINE       18005
 EXPRESSION (addr_hit[200] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T258,T259,T715
1	1	0	Covered	T536,T537,T611
1	1	1	Covered	T257,T258,T259

 LINE       18008
 EXPRESSION (addr_hit[201] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T151,T392,T401
1	1	0	Covered	T535,T541,T539
1	1	1	Covered	T52,T53,T54