Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	157835	1			T85	3		T87	9		T90	2
values[2]	3801	1			T413	1		T501	1		T503	2
values[3]	1635	1			T527	1		T738	6		T739	1
values[4]	1098	1			T738	2		T445	21		T478	31
values[5]	886	1			T738	4		T445	14		T478	24
values[6]	698	1			T738	2		T445	2		T478	12
values[7]	542	1			T738	5		T478	4		T730	37
values[8]	482	1			T738	2		T478	3		T730	26
values[9]	510	1			T738	7		T478	2		T730	30
values[10]	416	1			T738	6		T478	9		T730	11
values[11]	377	1			T738	9		T478	9		T730	20
values[12]	389	1			T738	10		T478	13		T730	22
values[13]	319	1			T738	8		T478	6		T730	12
values[14]	284	1			T738	20		T478	3		T730	7
values[15]	296	1			T738	41		T478	1		T730	13
values[16]	266	1			T738	22		T730	11		T722	5
values[17]	247	1			T738	25		T730	17		T722	7
values[18]	244	1			T738	44		T730	6		T722	7
values[19]	257	1			T738	60		T730	1		T722	3
values[20]	277	1			T738	56		T722	3		T480	3
values[21]	251	1			T738	34		T722	6		T480	1
values[22]	185	1			T738	9		T722	3		T480	1
values[23]	199	1			T738	7		T722	7		T480	2
values[24]	235	1			T738	16		T722	5		T480	3
values[25]	218	1			T738	11		T722	7		T480	3
values[26]	232	1			T738	14		T722	4		T480	1
values[27]	218	1			T738	26		T722	5		T480	2
values[28]	190	1			T738	18		T722	5		T480	3
values[29]	228	1			T738	11		T722	5		T480	4
values[30]	210	1			T738	10		T722	5		T480	2
values[31]	197	1			T722	5		T480	3		T740	1
values[32]	195	1			T722	3		T480	3		T740	1
values[33]	192	1			T722	5		T480	3		T740	1
values[34]	163	1			T722	3		T480	2		T740	1
values[35]	121	1			T722	8		T480	1		T740	1
values[36]	104	1			T722	2		T480	1		T740	1
values[37]	81	1			T722	3		T480	2		T740	1
values[38]	84	1			T722	7		T480	2		T740	1
values[39]	60	1			T722	5		T480	1		T740	1
values[40]	50	1			T722	5		T480	1		T740	1
values[41]	52	1			T722	7		T480	2		T740	1
values[42]	54	1			T722	5		T480	3		T740	1
values[43]	55	1			T722	6		T480	3		T740	1
values[44]	56	1			T722	8		T480	4		T740	1
values[45]	49	1			T722	6		T480	1		T740	1
values[46]	45	1			T722	2		T480	3		T740	1
values[47]	46	1			T722	4		T480	2		T740	1
values[48]	57	1			T722	8		T480	2		T740	1
values[49]	54	1			T722	7		T480	2		T740	1
values[50]	38	1			T722	4		T480	2		T740	1
values[51]	43	1			T722	3		T480	4		T740	1
values[52]	51	1			T722	8		T480	1		T740	1
values[53]	64	1			T722	7		T480	3		T740	1
values[54]	64	1			T722	7		T480	1		T740	1
values[55]	74	1			T722	3		T480	2		T740	1
values[56]	73	1			T722	4		T480	3		T740	1
values[57]	52	1			T722	3		T480	1		T740	1
values[58]	44	1			T722	6		T480	2		T740	1
values[59]	44	1			T722	7		T480	2		T740	1
values[60]	46	1			T722	9		T480	2		T740	1
values[61]	52	1			T722	14		T480	3		T740	1
values[62]	44	1			T722	5		T480	5		T740	1
values[63]	47	1			T722	5		T480	2		T740	1
values[64]	35	1			T722	3		T480	1		T740	1
values[65]	32	1			T722	3		T480	1		T740	1
values[66]	48	1			T722	3		T480	2		T740	1
values[67]	41	1			T722	3		T480	1		T740	1
values[68]	37	1			T722	4		T480	2		T740	1
values[69]	43	1			T722	3		T480	4		T740	1
values[70]	45	1			T722	4		T480	6		T740	1
values[71]	46	1			T722	5		T480	8		T740	1
values[72]	38	1			T722	3		T480	4		T740	1
values[73]	45	1			T722	5		T480	5		T740	1
values[74]	46	1			T722	3		T480	4		T740	1
values[75]	41	1			T722	4		T480	1		T740	1
values[76]	43	1			T722	11		T480	2		T740	1
values[77]	51	1			T722	3		T480	1		T740	1
values[78]	49	1			T722	4		T480	2		T740	1
values[79]	47	1			T722	7		T480	3		T740	1
values[80]	42	1			T722	7		T480	4		T740	1
values[81]	42	1			T722	4		T480	3		T740	1
values[82]	41	1			T722	3		T480	1		T740	1
values[83]	47	1			T722	10		T480	1		T740	1
values[84]	56	1			T722	11		T480	3		T740	1
values[85]	42	1			T722	3		T480	1		T740	1
values[86]	40	1			T722	3		T480	3		T740	1
values[87]	48	1			T722	2		T480	4		T740	1
values[88]	48	1			T722	4		T480	1		T740	1
values[89]	48	1			T722	4		T480	1		T740	1
values[90]	52	1			T722	2		T480	1		T740	1
values[91]	58	1			T722	4		T480	1		T740	1
values[92]	88	1			T722	12		T480	7		T740	1
values[93]	52	1			T722	3		T480	1		T740	1
values[94]	46	1			T722	3		T480	3		T740	1
values[95]	64	1			T722	12		T480	2		T740	1
values[96]	56	1			T722	9		T480	2		T740	1
values[97]	61	1			T722	12		T480	1		T740	1
values[98]	51	1			T722	2		T480	4		T740	1
values[99]	70	1			T722	7		T480	9		T740	1
values[100]	61	1			T722	13		T480	6		T740	1
values[101]	64	1			T722	6		T480	4		T740	1
values[102]	56	1			T722	6		T480	6		T740	1
values[103]	72	1			T722	8		T480	8		T740	2
values[104]	69	1			T722	6		T480	4		T740	1
values[105]	70	1			T722	10		T480	5		T740	1
values[106]	58	1			T722	6		T480	3		T740	2
values[107]	70	1			T722	10		T480	6		T740	2
values[108]	74	1			T722	9		T480	7		T740	1
values[109]	63	1			T722	4		T480	4		T740	1
values[110]	66	1			T722	8		T480	6		T740	1
values[111]	59	1			T722	9		T480	2		T740	1
values[112]	72	1			T722	9		T480	1		T740	1
values[113]	66	1			T722	8		T480	5		T740	2
values[114]	93	1			T722	15		T480	8		T740	2
values[115]	89	1			T722	9		T480	8		T740	3
values[116]	87	1			T722	9		T480	10		T740	1
values[117]	68	1			T722	7		T480	2		T740	2
values[118]	75	1			T722	7		T480	5		T740	4
values[119]	85	1			T722	12		T480	6		T740	3
values[120]	64	1			T722	6		T480	4		T740	1
values[121]	68	1			T722	9		T480	2		T740	1
values[122]	74	1			T722	14		T480	10		T740	1
values[123]	93	1			T722	24		T480	9		T740	3
values[124]	168	1			T722	36		T480	20		T740	1
values[125]	329	1			T722	84		T480	30		T740	3
values[126]	655	1			T722	108		T480	47		T740	23
values[127]	2543	1			T722	36		T480	12		T740	101
values[128]	4733	1			T722	1		T480	4		T740	178