Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.10 95.49 93.88 95.41 94.76 97.53 99.53


Total tests in report: 2688
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
40.63 40.63 50.74 50.74 46.80 46.80 25.28 25.28 61.76 61.76 59.09 59.09 0.13 0.13 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.1623112168
50.34 9.71 59.04 8.30 56.68 9.87 29.73 4.45 70.56 8.80 85.49 26.40 0.55 0.42 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.1905464472
54.67 4.33 59.04 0.00 56.68 0.00 29.73 0.00 70.56 0.00 85.49 0.00 26.51 25.95 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.2881382872
58.97 4.30 67.88 8.84 62.83 6.15 32.42 2.69 78.69 8.13 85.49 0.00 26.51 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.2331755415
62.91 3.94 75.77 7.89 63.95 1.12 38.43 6.01 78.86 0.18 85.49 0.00 34.97 8.46 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.367894270
66.00 3.09 80.73 4.97 67.91 3.96 41.80 3.37 80.55 1.69 90.03 4.55 34.97 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.59829593
68.95 2.95 80.73 0.00 67.92 0.01 59.05 17.25 80.56 0.01 90.38 0.35 35.07 0.11 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.676142797
71.51 2.56 83.02 2.29 75.54 7.62 59.50 0.45 84.64 4.08 90.38 0.00 35.98 0.90 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_hw_reset.3328376781
73.96 2.45 83.02 0.00 75.54 0.01 59.50 0.00 84.64 0.00 90.38 0.00 50.69 14.71 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.859259527
76.04 2.08 85.28 2.26 77.94 2.40 64.02 4.52 87.17 2.53 90.56 0.17 51.27 0.59 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.2631136847
77.96 1.92 85.28 0.00 78.00 0.06 64.02 0.00 87.17 0.00 90.56 0.00 62.74 11.47 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1727785836
79.47 1.51 85.28 0.00 78.00 0.00 64.02 0.00 87.17 0.00 90.56 0.00 71.78 9.04 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.3341736857
80.74 1.27 85.39 0.10 78.08 0.08 71.28 7.27 87.34 0.17 90.56 0.00 71.78 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.3558760020
81.93 1.19 87.46 2.07 78.80 0.73 74.16 2.88 87.77 0.43 91.61 1.05 71.78 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.3591133795
83.07 1.14 87.46 0.00 78.80 0.00 74.16 0.00 87.77 0.00 91.61 0.00 78.64 6.86 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1086977510
84.04 0.96 88.10 0.64 79.57 0.77 76.50 2.34 88.23 0.45 91.78 0.17 80.04 1.40 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.1756423647
84.99 0.96 88.18 0.08 80.68 1.10 76.50 0.00 88.29 0.06 91.78 0.00 84.54 4.50 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device.867834312
85.87 0.88 89.13 0.95 82.46 1.79 76.77 0.27 90.56 2.27 91.78 0.00 84.54 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2345724640
86.71 0.83 89.13 0.00 82.46 0.00 81.76 4.99 90.56 0.00 91.78 0.00 84.54 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.2517926413
87.44 0.74 89.46 0.33 82.58 0.12 81.77 0.01 90.69 0.12 95.63 3.85 84.54 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3344740543
88.13 0.69 89.46 0.00 82.58 0.00 85.91 4.14 90.69 0.00 95.63 0.00 84.54 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.2142401769
88.79 0.66 90.64 1.18 83.67 1.09 86.34 0.43 91.95 1.27 95.63 0.00 84.54 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_20.1850967374
89.32 0.53 91.44 0.80 84.43 0.76 86.55 0.21 92.84 0.88 96.15 0.52 84.54 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2496429166
89.83 0.51 91.45 0.01 87.00 2.57 86.55 0.00 92.84 0.00 96.15 0.00 85.00 0.46 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_tl_errors.2567329497
90.33 0.50 91.45 0.00 87.00 0.00 86.55 0.00 92.84 0.00 96.15 0.00 87.98 2.98 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2811807403
90.79 0.46 91.46 0.01 87.01 0.01 89.13 2.58 92.84 0.00 96.33 0.17 87.98 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.2350291033
91.21 0.42 91.46 0.00 87.01 0.01 89.13 0.00 92.84 0.00 96.33 0.00 90.49 2.51 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.3529591818
91.58 0.37 91.46 0.00 87.80 0.79 89.13 0.00 92.87 0.03 96.33 0.00 91.89 1.40 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all.792417779
91.90 0.32 92.15 0.69 88.10 0.30 89.86 0.73 93.04 0.17 96.33 0.00 91.93 0.04 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2404639938
92.21 0.31 92.56 0.41 89.37 1.27 89.89 0.03 93.17 0.13 96.33 0.00 91.93 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_rw.3694214509
92.48 0.28 93.01 0.45 89.81 0.44 90.19 0.30 93.63 0.46 96.33 0.00 91.93 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_plic_all_irqs_10.1376970046
92.74 0.26 93.01 0.00 89.87 0.06 90.20 0.01 93.63 0.00 96.33 0.00 93.41 1.48 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_large_delays.1476273256
92.99 0.25 93.01 0.00 89.87 0.00 90.20 0.00 93.63 0.00 96.33 0.00 94.91 1.50 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/8.xbar_access_same_device.3150070740
93.24 0.25 93.67 0.66 90.09 0.23 90.49 0.29 93.94 0.31 96.33 0.00 94.91 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.1337775088
93.47 0.23 93.67 0.00 90.09 0.00 90.49 0.00 93.94 0.00 96.33 0.00 96.31 1.40 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.304180631
93.67 0.19 93.68 0.01 90.11 0.01 91.64 1.15 93.94 0.00 96.33 0.00 96.31 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.587573509
93.81 0.14 93.68 0.00 90.11 0.00 92.49 0.85 93.94 0.00 96.33 0.00 96.31 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.2947440077
93.94 0.14 93.68 0.00 90.12 0.01 92.49 0.00 93.94 0.00 96.33 0.00 97.11 0.80 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_stress_all_with_error.1490560610
94.07 0.12 93.89 0.21 90.44 0.32 92.69 0.20 93.94 0.00 96.33 0.00 97.11 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4224104936
94.16 0.10 93.92 0.03 90.69 0.25 92.71 0.02 94.22 0.28 96.33 0.00 97.11 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.631190864
94.26 0.09 93.95 0.03 90.82 0.12 92.71 0.00 94.22 0.01 96.33 0.00 97.51 0.40 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.xbar_access_same_device.2888506801
94.34 0.09 93.95 0.00 90.82 0.00 93.23 0.52 94.22 0.00 96.33 0.00 97.51 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2815072525
94.43 0.09 93.95 0.00 91.33 0.52 93.23 0.00 94.22 0.00 96.33 0.00 97.51 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/7.chip_tl_errors.2388465847
94.51 0.08 94.08 0.13 91.40 0.07 93.45 0.22 94.30 0.07 96.33 0.00 97.51 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.4117819554
94.59 0.08 94.18 0.10 91.76 0.36 93.46 0.01 94.30 0.00 96.33 0.00 97.51 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_rw.3965363047
94.67 0.08 94.35 0.16 91.77 0.01 93.61 0.15 94.30 0.00 96.33 0.00 97.64 0.13 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke.2130416716
94.74 0.07 94.49 0.14 91.88 0.11 93.73 0.12 94.36 0.06 96.33 0.00 97.64 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.3382209195
94.79 0.05 94.49 0.00 92.03 0.14 93.73 0.00 94.41 0.05 96.33 0.00 97.77 0.13 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3027987808
94.84 0.05 94.49 0.01 92.05 0.02 93.84 0.11 94.41 0.00 96.50 0.17 97.77 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1849759400
94.89 0.04 94.49 0.00 92.05 0.00 94.10 0.26 94.41 0.00 96.50 0.00 97.77 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1872221636
94.93 0.04 94.49 0.00 92.08 0.03 94.10 0.00 94.41 0.00 96.50 0.00 97.99 0.22 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.4014801249
94.97 0.04 94.50 0.01 92.09 0.01 94.10 0.00 94.43 0.02 96.68 0.17 98.00 0.01 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.194864842
95.01 0.04 94.53 0.03 92.10 0.01 94.10 0.01 94.44 0.01 96.85 0.17 98.01 0.01 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/60.chip_sw_all_escalation_resets.777251747
95.04 0.04 94.53 0.01 92.11 0.01 94.12 0.02 94.45 0.01 97.03 0.17 98.03 0.01 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/18.chip_sw_all_escalation_resets.1692490521
95.08 0.04 94.54 0.01 92.12 0.01 94.13 0.01 94.46 0.01 97.20 0.17 98.04 0.01 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/77.chip_sw_all_escalation_resets.2169840622
95.12 0.04 94.55 0.01 92.14 0.01 94.13 0.00 94.47 0.01 97.38 0.17 98.05 0.01 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2992848219
95.15 0.04 94.55 0.00 92.14 0.00 94.34 0.21 94.47 0.00 97.38 0.00 98.05 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.146362254
95.19 0.03 94.55 0.00 92.34 0.21 94.34 0.00 94.47 0.00 97.38 0.00 98.05 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_tl_errors.556022313
95.22 0.03 94.55 0.00 92.34 0.00 94.37 0.03 94.47 0.00 97.55 0.17 98.05 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_data_integrity_escalation.1283683758
95.25 0.03 94.57 0.02 92.39 0.05 94.47 0.10 94.47 0.00 97.55 0.00 98.05 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/6.chip_csr_rw.3054275574
95.28 0.03 94.57 0.00 92.56 0.16 94.47 0.00 94.47 0.00 97.55 0.00 98.05 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_plic_all_irqs_0.491915805
95.30 0.03 94.64 0.07 92.58 0.03 94.48 0.01 94.52 0.05 97.55 0.00 98.05 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_sensor_ctrl_alert.2640375944
95.33 0.03 94.64 0.01 92.65 0.07 94.50 0.02 94.58 0.06 97.55 0.00 98.05 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.1068191274
95.36 0.03 94.64 0.00 92.66 0.01 94.50 0.00 94.58 0.00 97.55 0.00 98.19 0.14 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.1592162544
95.38 0.03 94.66 0.01 92.69 0.03 94.61 0.11 94.58 0.00 97.55 0.00 98.19 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1176380251
95.40 0.02 94.73 0.07 92.69 0.00 94.68 0.07 94.59 0.01 97.55 0.00 98.19 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2592656582
95.43 0.02 94.73 0.01 92.72 0.02 94.79 0.12 94.59 0.00 97.55 0.00 98.19 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3213383
95.45 0.02 94.73 0.00 92.75 0.03 94.79 0.00 94.59 0.00 97.55 0.00 98.30 0.11 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_unmapped_addr.1386770131
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95.99 0.01 94.92 0.01 93.83 0.00 95.37 0.01 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.452398808
95.99 0.01 94.92 0.00 93.83 0.00 95.37 0.01 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/2.chip_csr_hw_reset.680670679
95.99 0.01 94.92 0.00 93.83 0.00 95.38 0.01 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1491328804
96.00 0.01 94.92 0.00 93.83 0.00 95.38 0.01 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.1288883888
96.00 0.01 94.92 0.00 93.83 0.00 95.39 0.01 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.2303182181
96.00 0.01 94.92 0.00 93.84 0.01 95.39 0.00 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/24.xbar_stress_all_with_error.1464521365
96.00 0.01 94.92 0.00 93.84 0.01 95.39 0.00 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/4.chip_tl_errors.1456955136
96.00 0.01 94.92 0.00 93.84 0.01 95.39 0.00 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/47.xbar_stress_all_with_error.1641251954
96.00 0.01 94.92 0.00 93.85 0.01 95.39 0.00 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_error_random.4098022939
96.00 0.01 94.92 0.00 93.85 0.01 95.39 0.00 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.4051378571
96.00 0.01 94.92 0.00 93.86 0.01 95.39 0.00 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/60.xbar_stress_all_with_error.1002436105
96.00 0.01 94.92 0.00 93.86 0.01 95.39 0.00 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.1550952610
96.00 0.01 94.92 0.00 93.86 0.01 95.39 0.00 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.46426337
96.00 0.01 94.92 0.00 93.87 0.01 95.39 0.00 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.2565207081
96.00 0.01 94.92 0.00 93.87 0.01 95.39 0.00 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1910598505
96.00 0.01 94.92 0.00 93.87 0.01 95.39 0.00 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.1590970532
96.00 0.01 94.92 0.00 93.88 0.01 95.39 0.00 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.1304556962
96.00 0.01 94.92 0.00 93.88 0.01 95.39 0.00 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_jtag_csr_rw.1375411622
96.00 0.01 94.92 0.00 93.88 0.01 95.39 0.00 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/2.chip_sw_aon_timer_irq.1483325076
96.01 0.01 94.92 0.00 93.88 0.00 95.39 0.01 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.3213625310
96.01 0.01 94.92 0.00 93.88 0.00 95.39 0.01 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/3.chip_csr_hw_reset.1434159003
96.01 0.01 94.92 0.00 93.88 0.00 95.39 0.01 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.3665770356
96.01 0.01 94.92 0.00 93.88 0.00 95.40 0.01 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.1565650250
96.01 0.01 94.92 0.00 93.88 0.00 95.40 0.01 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.547074269
96.01 0.01 94.92 0.00 93.88 0.00 95.40 0.01 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.3261112768
96.01 0.01 94.92 0.00 93.88 0.00 95.40 0.01 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.1408484827
96.01 0.01 94.92 0.00 93.88 0.00 95.41 0.01 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.1087567499
96.01 0.01 94.92 0.00 93.88 0.00 95.41 0.01 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1686284347
96.01 0.01 94.92 0.00 93.88 0.00 95.41 0.01 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1621963042
96.01 0.01 94.92 0.00 93.88 0.00 95.41 0.01 94.76 0.00 97.55 0.00 99.53 0.00 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1527982132

Tests that do not contribute to grading

Name
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_aliasing.2572272141
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_bit_bash.1686632564
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2312401759
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_csr_rw.1407535712
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_prim_tl_access.227296180
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2233364227
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2073894530
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_error_random.2904752570
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random.2972113652
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_slow_rsp.3700297477
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_random_zero_delays.1194290155
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_same_source.3514692535
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2049723067
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_smoke_zero_delays.516818834
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/0.xbar_stress_all_with_error.2119815980
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_aliasing.2786066129
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_bit_bash.2033178924
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_csr_hw_reset.3660571131
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_prim_tl_access.2939533030
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1172516435
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.chip_same_csr_outstanding.514406623
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device.2453554546
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2140133638
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1125855231
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_error_random.1836546269
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random.3896319165
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_large_delays.868675544
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_slow_rsp.2606261425
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_random_zero_delays.3127630732
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_same_source.4173675946
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke.2194940895
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_large_delays.1826488322
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.4360625
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_smoke_zero_delays.814472792
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_stress_all.3118383550
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/1.xbar_unmapped_addr.1731922489
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3053498502
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_csr_rw.4270524960
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_same_csr_outstanding.678211871
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.chip_tl_errors.3071884594
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device.4203780465
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1918682006
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.456300215
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_error_random.4245407076
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random.2438844909
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_large_delays.3866308471
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_slow_rsp.967835290
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_random_zero_delays.1708601975
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_same_source.1416257244
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke.75398117
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_large_delays.167136004
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2409819008
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1939967953
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all.4054363393
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_error.1590185168
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3038031236
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1890008632
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/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2732207118
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.62824089
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/76.chip_sw_all_escalation_resets.1965792096
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3675480172
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2741523418
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2978216743
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_all_escalation_resets.2430781611
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_csrng_edn_concurrency.1346814771
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_lc_ctrl_transition.1097207681
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/8.chip_sw_uart_rand_baudrate.831352012
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.474522522
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/80.chip_sw_all_escalation_resets.1253063306
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3749016852
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/81.chip_sw_all_escalation_resets.519121817
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3966771744
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/82.chip_sw_all_escalation_resets.110791749
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3553625618
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/83.chip_sw_all_escalation_resets.1177174213
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4153875793
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/84.chip_sw_all_escalation_resets.3388577905
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1424702993
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/85.chip_sw_all_escalation_resets.2744470686
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2245864013
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/86.chip_sw_all_escalation_resets.602259930
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1525997232
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.4000336387
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/88.chip_sw_all_escalation_resets.839769710
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3091025714
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.395450415
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_csrng_edn_concurrency.3268017825
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/9.chip_sw_uart_rand_baudrate.359118186
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/90.chip_sw_all_escalation_resets.2359875566
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/91.chip_sw_all_escalation_resets.3044385759
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/93.chip_sw_all_escalation_resets.960023341
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/94.chip_sw_all_escalation_resets.1605373756
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/95.chip_sw_all_escalation_resets.1101444139
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/96.chip_sw_all_escalation_resets.1169286007
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/97.chip_sw_all_escalation_resets.2673467187
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/98.chip_sw_all_escalation_resets.3873907542
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/99.chip_sw_all_escalation_resets.1934228077
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1576360471
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2263517179
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1874843851
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1833939323
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.165593879
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1875484554
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3463897795
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3341813788



Total test records in report: 2688
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.1068191274 Aug 21 11:48:54 PM UTC 24 Aug 21 11:51:56 PM UTC 24 3387824938 ps
T2 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_concurrency.547074269 Aug 21 11:49:22 PM UTC 24 Aug 21 11:51:59 PM UTC 24 2826437272 ps
T3 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through_collision.1590970532 Aug 21 11:47:58 PM UTC 24 Aug 21 11:52:49 PM UTC 24 4155016560 ps
T4 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio.1623112168 Aug 21 11:52:11 PM UTC 24 Aug 21 11:56:28 PM UTC 24 3779962494 ps
T39 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_escalation.587573509 Aug 21 11:51:40 PM UTC 24 Aug 21 11:56:45 PM UTC 24 4447192710 ps
T11 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_tpm.1033968277 Aug 21 11:56:30 PM UTC 24 Aug 21 11:59:44 PM UTC 24 3460800702 ps
T31 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1872221636 Aug 21 11:58:31 PM UTC 24 Aug 22 12:01:22 AM UTC 24 4306687065 ps
T22 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_retention.3382209195 Aug 22 12:04:17 AM UTC 24 Aug 22 12:07:36 AM UTC 24 4466600712 ps
T24 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx1.1458957773 Aug 22 12:02:13 AM UTC 24 Aug 22 12:08:31 AM UTC 24 4928101832 ps
T97 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_manufacturer.276387715 Aug 22 12:06:47 AM UTC 24 Aug 22 12:09:22 AM UTC 24 2716903558 ps
T178 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sival_flash_info_access.3499471934 Aug 22 12:08:01 AM UTC 24 Aug 22 12:11:06 AM UTC 24 2402844000 ps
T33 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init.2142401769 Aug 21 11:54:30 PM UTC 24 Aug 22 12:13:39 AM UTC 24 23609998666 ps
T29 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_transition.2947440077 Aug 22 12:08:22 AM UTC 24 Aug 22 12:14:17 AM UTC 24 6672264061 ps
T27 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pattgen_ios.1064707802 Aug 22 12:12:09 AM UTC 24 Aug 22 12:14:42 AM UTC 24 2647181568 ps
T28 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pwm_pulses.707117815 Aug 22 12:01:16 AM UTC 24 Aug 22 12:14:55 AM UTC 24 8568977422 ps
T166 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3776842660 Aug 22 12:13:02 AM UTC 24 Aug 22 12:15:32 AM UTC 24 2281767866 ps
T387 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_rom.3608144690 Aug 22 12:14:38 AM UTC 24 Aug 22 12:16:05 AM UTC 24 1745592642 ps
T23 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_idx2.268549002 Aug 22 12:09:37 AM UTC 24 Aug 22 12:16:13 AM UTC 24 3688905144 ps
T75 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.98414750 Aug 22 12:10:45 AM UTC 24 Aug 22 12:16:56 AM UTC 24 4635521470 ps
T58 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.519233487 Aug 22 12:09:58 AM UTC 24 Aug 22 12:16:56 AM UTC 24 4254448442 ps
T814 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_example_flash.1033525589 Aug 22 12:14:09 AM UTC 24 Aug 22 12:17:16 AM UTC 24 2591086520 ps
T76 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_all_escalation_resets.1928096191 Aug 22 12:10:30 AM UTC 24 Aug 22 12:18:02 AM UTC 24 6137985792 ps
T167 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2144568612 Aug 22 12:12:17 AM UTC 24 Aug 22 12:18:34 AM UTC 24 4213618682 ps
T8 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_device_pass_through.1081700364 Aug 22 12:14:58 AM UTC 24 Aug 22 12:22:12 AM UTC 24 6648009450 ps
T120 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx.910932946 Aug 22 12:19:09 AM UTC 24 Aug 22 12:25:23 AM UTC 24 4281008388 ps
T372 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_rst.3301041121 Aug 22 12:22:49 AM UTC 24 Aug 22 12:25:29 AM UTC 24 2288410720 ps
T53 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_device_tx_rx.309042119 Aug 22 12:20:27 AM UTC 24 Aug 22 12:25:31 AM UTC 24 3410593660 ps
T19 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_wake.3774857256 Aug 22 12:23:43 AM UTC 24 Aug 22 12:27:00 AM UTC 24 3244280236 ps
T181 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.676142797 Aug 22 12:23:09 AM UTC 24 Aug 22 12:27:16 AM UTC 24 4428965616 ps
T54 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx.2565207081 Aug 22 12:19:58 AM UTC 24 Aug 22 12:27:59 AM UTC 24 5205940960 ps
T10 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2345724640 Aug 22 12:24:12 AM UTC 24 Aug 22 12:27:59 AM UTC 24 3881798916 ps
T136 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.531913268 Aug 22 12:19:02 AM UTC 24 Aug 22 12:30:14 AM UTC 24 6431750154 ps
T5 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pullup.981211508 Aug 22 12:26:57 AM UTC 24 Aug 22 12:30:51 AM UTC 24 3045094356 ps
T30 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3556254436 Aug 22 12:29:20 AM UTC 24 Aug 22 12:31:09 AM UTC 24 3739245519 ps
T139 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prodend.3558760020 Aug 22 12:23:50 AM UTC 24 Aug 22 12:32:25 AM UTC 24 11449916795 ps
T25 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_spi_host_tx_rx.452398808 Aug 22 12:31:28 AM UTC 24 Aug 22 12:34:13 AM UTC 24 3409252298 ps
T56 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3306140593 Aug 22 12:24:49 AM UTC 24 Aug 22 12:34:44 AM UTC 24 6046941196 ps
T121 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3213383 Aug 22 12:05:40 AM UTC 24 Aug 22 12:35:48 AM UTC 24 14048393422 ps
T186 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1035496941 Aug 22 12:34:33 AM UTC 24 Aug 22 12:38:38 AM UTC 24 3398242025 ps
T172 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_alert_info.2631136847 Aug 22 12:22:29 AM UTC 24 Aug 22 12:38:40 AM UTC 24 10843828400 ps
T64 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1448300345 Aug 22 12:30:02 AM UTC 24 Aug 22 12:38:51 AM UTC 24 8339315206 ps
T26 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_inputs.421353193 Aug 22 12:36:45 AM UTC 24 Aug 22 12:40:22 AM UTC 24 3074244095 ps
T173 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3763415126 Aug 22 12:38:17 AM UTC 24 Aug 22 12:41:03 AM UTC 24 2769285858 ps
T15 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4243288929 Aug 22 12:37:14 AM UTC 24 Aug 22 12:41:43 AM UTC 24 5649176264 ps
T65 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4194005349 Aug 22 12:30:39 AM UTC 24 Aug 22 12:42:08 AM UTC 24 10889158354 ps
T6 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_dpi.1631190082 Aug 22 12:18:28 AM UTC 24 Aug 22 12:49:10 AM UTC 24 12614794854 ps
T115 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_irq.15410205 Aug 22 12:46:39 AM UTC 24 Aug 22 12:50:21 AM UTC 24 3477080768 ps
T815 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rstmgr_sw_req.2565073347 Aug 22 12:47:23 AM UTC 24 Aug 22 12:51:45 AM UTC 24 3567590268 ps
T7 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_stream.2794440772 Aug 22 12:00:27 AM UTC 24 Aug 22 12:52:07 AM UTC 24 19404058250 ps
T128 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.827810243 Aug 22 12:46:47 AM UTC 24 Aug 22 12:53:10 AM UTC 24 8058448400 ps
T148 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.330538919 Aug 22 12:47:53 AM UTC 24 Aug 22 12:54:10 AM UTC 24 9759980626 ps
T63 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3790209469 Aug 22 12:48:07 AM UTC 24 Aug 22 12:54:35 AM UTC 24 4870520430 ps
T322 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1609860211 Aug 22 12:55:10 AM UTC 24 Aug 22 01:01:11 AM UTC 24 7630383946 ps
T92 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_timeout.1020370119 Aug 22 12:56:31 AM UTC 24 Aug 22 01:01:43 AM UTC 24 4685924030 ps
T137 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en.2901215136 Aug 22 12:59:52 AM UTC 24 Aug 22 01:03:20 AM UTC 24 3126252689 ps
T69 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_test.1756423647 Aug 22 01:00:35 AM UTC 24 Aug 22 01:03:49 AM UTC 24 2859078488 ps
T364 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_kat_test.775159267 Aug 22 01:07:01 AM UTC 24 Aug 22 01:10:05 AM UTC 24 3062754336 ps
T235 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1910598505 Aug 22 01:00:50 AM UTC 24 Aug 22 01:10:09 AM UTC 24 5549633040 ps
T176 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4213536896 Aug 22 01:10:31 AM UTC 24 Aug 22 01:12:05 AM UTC 24 2742832815 ps
T193 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_mem_scramble.1087567499 Aug 22 01:06:22 AM UTC 24 Aug 22 01:12:10 AM UTC 24 3691878476 ps
T177 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1347872794 Aug 22 01:11:00 AM UTC 24 Aug 22 01:12:29 AM UTC 24 2402560348 ps
T287 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc.3254126075 Aug 22 01:12:03 AM UTC 24 Aug 22 01:16:04 AM UTC 24 3290119152 ps
T288 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.966636318 Aug 22 01:11:08 AM UTC 24 Aug 22 01:17:14 AM UTC 24 5176494940 ps
T143 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_boot_mode.1565650250 Aug 22 01:13:47 AM UTC 24 Aug 22 01:19:58 AM UTC 24 3124610952 ps
T146 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_kat_test.3917036688 Aug 22 01:16:42 AM UTC 24 Aug 22 01:20:15 AM UTC 24 2909044468 ps
T289 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1701739109 Aug 22 01:16:59 AM UTC 24 Aug 22 01:22:48 AM UTC 24 4079145232 ps
T147 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_randomness.1008983010 Aug 22 01:11:48 AM UTC 24 Aug 22 01:22:59 AM UTC 24 5844518522 ps
T12 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3626610056 Aug 22 01:19:21 AM UTC 24 Aug 22 01:23:21 AM UTC 24 3116121406 ps
T133 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1976100032 Aug 22 01:10:38 AM UTC 24 Aug 22 01:23:55 AM UTC 24 7393831267 ps
T244 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3366697814 Aug 22 01:17:44 AM UTC 24 Aug 22 01:24:12 AM UTC 24 5106665380 ps
T245 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2379400209 Aug 22 12:55:24 AM UTC 24 Aug 22 01:24:15 AM UTC 24 27832226606 ps
T816 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1245172452 Aug 22 01:18:26 AM UTC 24 Aug 22 01:25:06 AM UTC 24 4080180040 ps
T215 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.680955069 Aug 22 01:10:17 AM UTC 24 Aug 22 01:25:15 AM UTC 24 6526641972 ps
T593 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_oneshot.1055137784 Aug 22 01:21:41 AM UTC 24 Aug 22 01:25:44 AM UTC 24 3181899000 ps
T587 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_ping_ok.3665770356 Aug 22 01:09:03 AM UTC 24 Aug 22 01:25:45 AM UTC 24 7851482600 ps
T204 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_escalation.1375401636 Aug 22 01:19:14 AM UTC 24 Aug 22 01:26:47 AM UTC 24 6531088936 ps
T243 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_rnd.845318457 Aug 22 01:15:15 AM UTC 24 Aug 22 01:26:48 AM UTC 24 5580798412 ps
T93 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2404639938 Aug 22 01:12:27 AM UTC 24 Aug 22 01:27:06 AM UTC 24 10618314744 ps
T144 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2815072525 Aug 22 01:19:55 AM UTC 24 Aug 22 01:27:33 AM UTC 24 6160239680 ps
T817 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_ast_rng_req.4107957984 Aug 22 01:25:27 AM UTC 24 Aug 22 01:27:55 AM UTC 24 2183016990 ps
T218 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3637058615 Aug 22 01:07:30 AM UTC 24 Aug 22 01:28:01 AM UTC 24 18957173545 ps
T145 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_kat.3198445809 Aug 22 01:22:33 AM UTC 24 Aug 22 01:29:52 AM UTC 24 2946187496 ps
T316 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_entropy_src_csrng.664683970 Aug 22 01:18:33 AM UTC 24 Aug 22 01:30:26 AM UTC 24 5612092376 ps
T94 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_entropy.3054085993 Aug 22 01:30:35 AM UTC 24 Aug 22 01:34:50 AM UTC 24 3358091095 ps
T818 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2929145053 Aug 22 12:28:40 AM UTC 24 Aug 22 01:37:15 AM UTC 24 27651760102 ps
T406 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1134596149 Aug 22 01:18:10 AM UTC 24 Aug 22 01:40:02 AM UTC 24 8143282800 ps
T194 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.539011393 Aug 22 01:34:59 AM UTC 24 Aug 22 01:41:31 AM UTC 24 4879805878 ps
T404 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac.1353540064 Aug 22 01:38:26 AM UTC 24 Aug 22 01:41:44 AM UTC 24 2499581440 ps
T161 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sensor_ctrl_status.194754666 Aug 22 01:40:18 AM UTC 24 Aug 22 01:44:00 AM UTC 24 3629572575 ps
T819 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_frequency.164250152 Aug 22 01:41:45 AM UTC 24 Aug 22 01:46:25 AM UTC 24 2822283160 ps
T405 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1725525368 Aug 22 01:44:08 AM UTC 24 Aug 22 01:47:48 AM UTC 24 2609768814 ps
T255 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_edn_auto_mode.2350291033 Aug 22 01:36:31 AM UTC 24 Aug 22 01:48:30 AM UTC 24 4517960380 ps
T163 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.269447392 Aug 22 12:58:53 AM UTC 24 Aug 22 01:51:04 AM UTC 24 16893597500 ps
T314 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_enc_jitter_en.46426337 Aug 22 01:49:22 AM UTC 24 Aug 22 01:53:23 AM UTC 24 3097283688 ps
T188 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1122275622 Aug 22 01:42:49 AM UTC 24 Aug 22 01:53:25 AM UTC 24 7379489194 ps
T140 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3952770849 Aug 22 01:45:57 AM UTC 24 Aug 22 01:53:35 AM UTC 24 3986061796 ps
T388 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_app_rom.4152852342 Aug 22 01:51:36 AM UTC 24 Aug 22 01:54:42 AM UTC 24 2624863114 ps
T141 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3697359010 Aug 22 01:47:17 AM UTC 24 Aug 22 01:54:48 AM UTC 24 3678280288 ps
T134 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1491328804 Aug 22 01:33:26 AM UTC 24 Aug 22 01:55:17 AM UTC 24 10343580292 ps
T187 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.198708500 Aug 22 01:48:02 AM UTC 24 Aug 22 01:56:07 AM UTC 24 4039864396 ps
T185 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.384657939 Aug 22 01:44:00 AM UTC 24 Aug 22 01:56:13 AM UTC 24 14345472423 ps
T595 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2983140806 Aug 22 01:51:58 AM UTC 24 Aug 22 01:57:46 AM UTC 24 4476184400 ps
T594 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_multistream.188710037 Aug 22 01:37:29 AM UTC 24 Aug 22 01:57:56 AM UTC 24 8033521728 ps
T13 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.4117819554 Aug 22 01:13:55 AM UTC 24 Aug 22 01:58:06 AM UTC 24 20820179334 ps
T32 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_csr_rw.1905464472 Aug 22 01:42:53 AM UTC 24 Aug 22 01:58:39 AM UTC 24 12986841575 ps
T80 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_jtag_mem_access.1903634053 Aug 22 01:44:16 AM UTC 24 Aug 22 02:00:18 AM UTC 24 13466938600 ps
T179 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_prod.1098908528 Aug 22 12:49:11 AM UTC 24 Aug 22 02:02:41 AM UTC 24 50569470528 ps
T219 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_kmac.2517926413 Aug 22 01:34:41 AM UTC 24 Aug 22 02:02:47 AM UTC 24 11962999074 ps
T220 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_aes.3261112768 Aug 22 01:29:46 AM UTC 24 Aug 22 02:03:02 AM UTC 24 13642938580 ps
T182 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_ctrl_program_error.1288883888 Aug 22 01:57:46 AM UTC 24 Aug 22 02:03:28 AM UTC 24 5528249000 ps
T311 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_plic_all_irqs_0.2331755415 Aug 22 01:50:47 AM UTC 24 Aug 22 02:03:38 AM UTC 24 6181690042 ps
T395 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2073801125 Aug 22 01:59:50 AM UTC 24 Aug 22 02:04:22 AM UTC 24 4245431284 ps
T396 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_reset_frequency.2945068483 Aug 22 01:59:35 AM UTC 24 Aug 22 02:04:30 AM UTC 24 3303923336 ps
T397 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_cshake.3031768551 Aug 22 02:01:22 AM UTC 24 Aug 22 02:04:36 AM UTC 24 2587686092 ps
T217 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_prod.4007045062 Aug 22 02:03:17 AM UTC 24 Aug 22 02:05:12 AM UTC 24 2513410213 ps
T184 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_rma.2303182181 Aug 22 12:57:51 AM UTC 24 Aug 22 02:06:16 AM UTC 24 47394038290 ps
T35 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usbdev_pincfg.764001280 Aug 22 12:31:49 AM UTC 24 Aug 22 02:06:18 AM UTC 24 31707205214 ps
T617 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_ast_clk_outputs.1675589591 Aug 22 01:54:46 AM UTC 24 Aug 22 02:06:25 AM UTC 24 8321019040 ps
T142 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4048391866 Aug 22 01:59:42 AM UTC 24 Aug 22 02:06:55 AM UTC 24 4476953448 ps
T410 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.1686284347 Aug 22 01:46:29 AM UTC 24 Aug 22 02:07:35 AM UTC 24 13006215534 ps
T135 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2762172465 Aug 22 01:22:42 AM UTC 24 Aug 22 02:12:44 AM UTC 24 19184859312 ps
T820 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.659452430 Aug 22 02:09:19 AM UTC 24 Aug 22 02:13:11 AM UTC 24 3563330550 ps
T821 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2152753706 Aug 22 02:09:27 AM UTC 24 Aug 22 02:15:35 AM UTC 24 5706276234 ps
T160 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3396639343 Aug 22 02:10:55 AM UTC 24 Aug 22 02:15:46 AM UTC 24 6548657692 ps
T81 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_testunlock0.2592656582 Aug 22 02:10:33 AM UTC 24 Aug 22 02:16:36 AM UTC 24 6587486872 ps
T138 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1849759400 Aug 22 02:10:18 AM UTC 24 Aug 22 02:17:48 AM UTC 24 5497448196 ps
T822 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2443711647 Aug 22 02:13:57 AM UTC 24 Aug 22 02:17:56 AM UTC 24 3252927177 ps
T221 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_sideload_otbn.1408484827 Aug 22 01:33:32 AM UTC 24 Aug 22 02:18:38 AM UTC 24 12430607310 ps
T823 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_write_clear.2988444810 Aug 22 02:14:38 AM UTC 24 Aug 22 02:18:54 AM UTC 24 3022894612 ps
T824 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_sleep_frequency.545490329 Aug 22 02:13:04 AM UTC 24 Aug 22 02:19:35 AM UTC 24 4630729156 ps
T84 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_dev.921723410 Aug 22 02:15:22 AM UTC 24 Aug 22 02:20:08 AM UTC 24 5373158905 ps
T229 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_lc_walkthrough_dev.3762993553 Aug 22 01:04:52 AM UTC 24 Aug 22 02:21:13 AM UTC 24 49111638872 ps
T189 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_execution_main.2417066600 Aug 22 02:10:48 AM UTC 24 Aug 22 02:21:14 AM UTC 24 9191640572 ps
T305 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1956310224 Aug 22 02:17:24 AM UTC 24 Aug 22 02:24:04 AM UTC 24 4327099800 ps
T306 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter.2952190275 Aug 22 02:22:00 AM UTC 24 Aug 22 02:24:06 AM UTC 24 2864243896 ps
T224 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2689772281 Aug 22 02:13:41 AM UTC 24 Aug 22 02:24:13 AM UTC 24 7950037889 ps
T67 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2496429166 Aug 22 02:20:42 AM UTC 24 Aug 22 02:24:50 AM UTC 24 7619999192 ps
T256 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency.556146311 Aug 22 02:00:57 AM UTC 24 Aug 22 02:26:44 AM UTC 24 9190316820 ps
T307 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1517966496 Aug 22 02:24:19 AM UTC 24 Aug 22 02:30:12 AM UTC 24 6059694904 ps
T77 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_tap_straps_rma.3213625310 Aug 22 02:29:22 AM UTC 24 Aug 22 02:34:01 AM UTC 24 5630247262 ps
T308 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2644902468 Aug 22 02:33:01 AM UTC 24 Aug 22 02:35:04 AM UTC 24 3103630573 ps
T309 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2106661509 Aug 22 02:04:56 AM UTC 24 Aug 22 02:36:31 AM UTC 24 31899794328 ps
T190 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3344740543 Aug 22 02:37:17 AM UTC 24 Aug 22 02:40:49 AM UTC 24 3118456800 ps
T118 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_idle_load.3888383561 Aug 22 02:34:12 AM UTC 24 Aug 22 02:41:54 AM UTC 24 4608473738 ps
T149 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3508877491 Aug 22 02:36:03 AM UTC 24 Aug 22 02:42:16 AM UTC 24 6223877736 ps
T300 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2369496227 Aug 22 02:32:27 AM UTC 24 Aug 22 02:43:00 AM UTC 24 7245869293 ps
T301 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2129421756 Aug 22 02:38:19 AM UTC 24 Aug 22 02:44:16 AM UTC 24 5475041506 ps
T68 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.314549976 Aug 22 02:29:51 AM UTC 24 Aug 22 02:45:39 AM UTC 24 21568198132 ps
T302 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_rom.4186538539 Aug 22 02:45:06 AM UTC 24 Aug 22 02:46:49 AM UTC 24 2545551072 ps
T127 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_sleep_load.67167545 Aug 22 02:40:53 AM UTC 24 Aug 22 02:49:01 AM UTC 24 10207027998 ps
T230 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_flash_init_reduced_freq.3446472956 Aug 22 02:30:15 AM UTC 24 Aug 22 02:50:39 AM UTC 24 19854080531 ps
T113 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_rv_dm_ndm_reset_req.3231712390 Aug 22 02:45:21 AM UTC 24 Aug 22 02:51:20 AM UTC 24 5110943460 ps
T825 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.4172287295 Aug 22 02:48:26 AM UTC 24 Aug 22 02:51:43 AM UTC 24 3579995701 ps
T599 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_smoketest.3109537574 Aug 22 02:48:33 AM UTC 24 Aug 22 02:51:56 AM UTC 24 3133043130 ps
T191 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2486776271 Aug 22 02:49:37 AM UTC 24 Aug 22 02:52:23 AM UTC 24 2736333262 ps
T88 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3217581750 Aug 22 12:27:17 AM UTC 24 Aug 22 02:52:41 AM UTC 24 57457287964 ps
T826 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_usb_ast_clk_calib.602863620 Aug 22 02:50:18 AM UTC 24 Aug 22 02:54:08 AM UTC 24 2865077586 ps
T827 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_flash.1589626092 Aug 22 02:50:59 AM UTC 24 Aug 22 02:54:12 AM UTC 24 2989736840 ps
T253 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.840875174 Aug 22 02:48:40 AM UTC 24 Aug 22 02:54:17 AM UTC 24 5096111600 ps
T130 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.373143918 Aug 22 02:40:24 AM UTC 24 Aug 22 02:57:25 AM UTC 24 9329784224 ps
T828 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_aes_smoketest.4038113808 Aug 22 02:55:30 AM UTC 24 Aug 22 02:57:52 AM UTC 24 2878963060 ps
T829 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_hmac_smoketest.1160363970 Aug 22 02:57:10 AM UTC 24 Aug 22 03:00:36 AM UTC 24 3302586230 ps
T830 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_clkmgr_smoketest.2814370442 Aug 22 02:58:42 AM UTC 24 Aug 22 03:01:48 AM UTC 24 3599114040 ps
T116 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_rv_timer_smoketest.3431048931 Aug 22 03:00:11 AM UTC 24 Aug 22 03:02:58 AM UTC 24 3286892430 ps
T122 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1176380251 Aug 21 11:47:23 PM UTC 24 Aug 22 03:04:47 AM UTC 24 79111806452 ps
T831 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_sram_ctrl_smoketest.1495789690 Aug 22 03:02:52 AM UTC 24 Aug 22 03:05:16 AM UTC 24 2838905400 ps
T832 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_csrng_smoketest.173314456 Aug 22 03:02:45 AM UTC 24 Aug 22 03:06:00 AM UTC 24 2912753978 ps
T313 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sival_flash_info_access.980452882 Aug 22 03:07:56 AM UTC 24 Aug 22 03:11:03 AM UTC 24 2712442576 ps
T55 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx.2816504652 Aug 22 03:04:12 AM UTC 24 Aug 22 03:11:10 AM UTC 24 4751506500 ps
T833 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_kmac_smoketest.3021590406 Aug 22 03:09:57 AM UTC 24 Aug 22 03:13:09 AM UTC 24 2568806090 ps
T211 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_inject_scramble_seed.3603392778 Aug 22 12:22:09 AM UTC 24 Aug 22 03:16:58 AM UTC 24 64193423039 ps
T416 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.326483266 Aug 22 03:13:12 AM UTC 24 Aug 22 03:18:57 AM UTC 24 5074019476 ps
T834 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otp_ctrl_smoketest.1190570670 Aug 22 03:16:14 AM UTC 24 Aug 22 03:19:45 AM UTC 24 2634790394 ps
T180 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_all_escalation_resets.651469215 Aug 22 03:12:57 AM UTC 24 Aug 22 03:19:50 AM UTC 24 5720690640 ps
T123 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx1.4280200576 Aug 22 03:14:14 AM UTC 24 Aug 22 03:21:19 AM UTC 24 3952253328 ps
T835 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_example_manufacturer.1108667861 Aug 22 03:19:02 AM UTC 24 Aug 22 03:21:53 AM UTC 24 3443399140 ps
T233 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2130891678 Aug 22 03:16:59 AM UTC 24 Aug 22 03:22:59 AM UTC 24 4686836590 ps
T20 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_wake.30534853 Aug 22 03:18:34 AM UTC 24 Aug 22 03:23:16 AM UTC 24 5482441250 ps
T34 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.43736222 Aug 22 03:17:06 AM UTC 24 Aug 22 03:24:18 AM UTC 24 4436205532 ps
T48 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_dev.2798556156 Aug 22 03:04:58 AM UTC 24 Aug 22 03:24:40 AM UTC 24 10162292250 ps
T836 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_keymgr_functest.2685107196 Aug 22 03:19:30 AM UTC 24 Aug 22 03:25:22 AM UTC 24 4229814346 ps
T37 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_gpio_smoketest.567349768 Aug 22 03:21:41 AM UTC 24 Aug 22 03:25:32 AM UTC 24 2994230105 ps
T9 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_power_virus.3591133795 Aug 22 03:10:23 AM UTC 24 Aug 22 03:27:13 AM UTC 24 6472329104 ps
T126 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pattgen_ios.3697667584 Aug 22 03:24:19 AM UTC 24 Aug 22 03:27:57 AM UTC 24 3435807178 ps
T14 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.631190864 Aug 22 03:24:47 AM UTC 24 Aug 22 03:28:07 AM UTC 24 3312783694 ps
T280 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_data_integrity_escalation.1911957285 Aug 22 03:21:09 AM UTC 24 Aug 22 03:30:23 AM UTC 24 6027814540 ps
T837 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pwm_pulses.759390448 Aug 22 03:18:11 AM UTC 24 Aug 22 03:31:28 AM UTC 24 9249942744 ps
T57 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3764235268 Aug 22 03:28:04 AM UTC 24 Aug 22 03:36:32 AM UTC 24 5087221184 ps
T838 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_access.3907075003 Aug 22 03:27:09 AM UTC 24 Aug 22 03:36:43 AM UTC 24 5514432270 ps
T164 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2523315534 Aug 22 02:51:17 AM UTC 24 Aug 22 03:37:25 AM UTC 24 24499408345 ps
T312 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_device_tx_rx.1272368486 Aug 22 03:31:27 AM UTC 24 Aug 22 03:37:30 AM UTC 24 4170195732 ps
T205 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through_collision.879339704 Aug 22 03:34:17 AM UTC 24 Aug 22 03:40:39 AM UTC 24 5083401858 ps
T61 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx3.3211420200 Aug 22 03:35:07 AM UTC 24 Aug 22 03:41:26 AM UTC 24 3711033320 ps
T49 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.1256095462 Aug 22 03:20:38 AM UTC 24 Aug 22 03:41:43 AM UTC 24 11428134543 ps
T839 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_rand_baudrate.3900254328 Aug 22 03:36:48 AM UTC 24 Aug 22 03:41:48 AM UTC 24 3830722312 ps
T323 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_ops.2935478318 Aug 22 03:35:22 AM UTC 24 Aug 22 03:41:57 AM UTC 24 4109150530 ps
T317 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx.1831618656 Aug 22 03:35:59 AM UTC 24 Aug 22 03:42:37 AM UTC 24 4761621132 ps
T206 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pass_through.2254807548 Aug 22 03:38:27 AM UTC 24 Aug 22 03:45:22 AM UTC 24 6711217219 ps
T267 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3615082522 Aug 22 03:45:39 AM UTC 24 Aug 22 03:47:08 AM UTC 24 2010878530 ps
T407 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_kmac_entropy.3326719428 Aug 22 03:46:42 AM UTC 24 Aug 22 03:49:38 AM UTC 24 2493104210 ps
T386 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2742837559 Aug 22 03:38:56 AM UTC 24 Aug 22 03:49:59 AM UTC 24 6413742539 ps
T60 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_uart_tx_rx_idx2.866001978 Aug 22 03:42:54 AM UTC 24 Aug 22 03:50:06 AM UTC 24 4418601650 ps
T66 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sleep_pin_retention.1548498855 Aug 22 03:46:22 AM UTC 24 Aug 22 03:50:43 AM UTC 24 4072720072 ps
T353 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3167307895 Aug 22 03:47:19 AM UTC 24 Aug 22 03:51:49 AM UTC 24 3239038180 ps
T50 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_smoke.91723547 Aug 22 03:07:42 AM UTC 24 Aug 22 03:53:26 AM UTC 24 14674883276 ps
T840 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2841674768 Aug 22 03:41:21 AM UTC 24 Aug 22 03:53:38 AM UTC 24 7922393642 ps
T254 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_jtag_debug_rma.1996037068 Aug 22 03:33:32 AM UTC 24 Aug 22 03:56:03 AM UTC 24 10442124067 ps
T841 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_rst.996799017 Aug 22 03:53:13 AM UTC 24 Aug 22 03:56:24 AM UTC 24 3151194080 ps
T59 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2818703605 Aug 22 03:46:57 AM UTC 24 Aug 22 03:56:39 AM UTC 24 5892062934 ps
T236 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_cpu_info.2255302913 Aug 22 03:49:41 AM UTC 24 Aug 22 03:57:03 AM UTC 24 5841648400 ps
T227 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_init.3733008116 Aug 22 03:39:45 AM UTC 24 Aug 22 04:02:15 AM UTC 24 23039751295 ps
T72 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.439887461 Aug 22 03:55:19 AM UTC 24 Aug 22 03:58:56 AM UTC 24 4005306927 ps
T260 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2312459272 Aug 22 03:50:32 AM UTC 24 Aug 22 04:02:34 AM UTC 24 6506275564 ps
T261 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_transition.526259381 Aug 22 03:54:03 AM UTC 24 Aug 22 04:04:45 AM UTC 24 11961253545 ps
T262 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2232804393 Aug 22 04:01:28 AM UTC 24 Aug 22 04:08:40 AM UTC 24 4452653904 ps
T263 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1865392935 Aug 22 03:56:21 AM UTC 24 Aug 22 04:09:02 AM UTC 24 7363829568 ps
T264 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_sw_req.4000522339 Aug 22 04:04:21 AM UTC 24 Aug 22 04:10:05 AM UTC 24 4693857564 ps
T265 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.4123699064 Aug 22 04:07:59 AM UTC 24 Aug 22 04:11:11 AM UTC 24 2759881845 ps
T266 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1253548012 Aug 22 04:04:58 AM UTC 24 Aug 22 04:11:18 AM UTC 24 6983597140 ps
T842 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3112746329 Aug 22 04:07:06 AM UTC 24 Aug 22 04:12:10 AM UTC 24 5289175377 ps
T354 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2536341722 Aug 22 03:59:26 AM UTC 24 Aug 22 04:13:52 AM UTC 24 9708969970 ps
T843 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3907424682 Aug 22 04:00:18 AM UTC 24 Aug 22 04:15:08 AM UTC 24 13064098339 ps
T338 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_irq.3122686407 Aug 22 04:11:21 AM UTC 24 Aug 22 04:15:46 AM UTC 24 3553883744 ps
T415 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_static_critical.4169683836 Aug 22 03:19:51 AM UTC 24 Aug 22 04:16:49 AM UTC 24 17939672480 ps
T268 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2298666346 Aug 22 04:15:34 AM UTC 24 Aug 22 04:16:59 AM UTC 24 2296329336 ps
T844 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_enc_jitter_en.1572099008 Aug 22 04:15:19 AM UTC 24 Aug 22 04:18:04 AM UTC 24 2942243849 ps
T845 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aes_idle.1158486242 Aug 22 04:16:04 AM UTC 24 Aug 22 04:19:16 AM UTC 24 3002463216 ps
T846 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.337766648 Aug 22 04:14:43 AM UTC 24 Aug 22 04:19:48 AM UTC 24 7489023056 ps
T847 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_lc_walkthrough_prodend.2248582397 Aug 22 04:09:17 AM UTC 24 Aug 22 04:20:32 AM UTC 24 9524625725 ps
T324 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rstmgr_alert_info.1304556962 Aug 22 04:02:37 AM UTC 24 Aug 22 04:21:22 AM UTC 24 11642837604 ps
T848 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.1081990619 Aug 22 03:33:03 AM UTC 24 Aug 22 04:22:12 AM UTC 24 15749193816 ps
T196 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_flash_rma_unlocked.146362254 Aug 22 03:21:48 AM UTC 24 Aug 22 04:22:25 AM UTC 24 42538632020 ps
T849 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2185741506 Aug 22 04:12:08 AM UTC 24 Aug 22 04:22:28 AM UTC 24 9695695320 ps
T36 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_reset.2854430752 Aug 22 04:03:22 AM UTC 24 Aug 22 04:23:16 AM UTC 24 24650899696 ps
T408 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.4147113849 Aug 22 04:15:56 AM UTC 24 Aug 22 04:24:16 AM UTC 24 4890637888 ps
T45 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_exception_c.819531174 Aug 22 03:39:24 AM UTC 24 Aug 22 04:24:34 AM UTC 24 13989764530 ps
T117 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_timer_irq.202845091 Aug 22 04:20:51 AM UTC 24 Aug 22 04:24:34 AM UTC 24 3773688446 ps
T850 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1793052325 Aug 22 03:34:47 AM UTC 24 Aug 22 04:24:39 AM UTC 24 15439479140 ps
T95 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3084723290 Aug 22 01:09:55 AM UTC 24 Aug 22 04:27:32 AM UTC 24 255082817072 ps
T851 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2188555544 Aug 22 04:13:38 AM UTC 24 Aug 22 04:28:29 AM UTC 24 13040012371 ps
T129 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2158949249 Aug 22 04:25:24 AM UTC 24 Aug 22 04:30:03 AM UTC 24 18308062114 ps
T852 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_rv_core_ibex_rnd.1138122776 Aug 22 04:21:24 AM UTC 24 Aug 22 04:31:07 AM UTC 24 5368066140 ps
T41 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.560385684 Aug 22 04:28:10 AM UTC 24 Aug 22 04:33:14 AM UTC 24 5660247400 ps
T853 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.391448173 Aug 22 04:25:31 AM UTC 24 Aug 22 04:34:11 AM UTC 24 8870355320 ps
T339 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.883301644 Aug 22 04:31:47 AM UTC 24 Aug 22 04:37:47 AM UTC 24 4558986136 ps
T212 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1977559597 Aug 22 04:37:20 AM UTC 24 Aug 22 04:40:57 AM UTC 24 2997639414 ps
T854 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1528738315 Aug 22 04:38:43 AM UTC 24 Aug 22 04:44:46 AM UTC 24 4835975776 ps
T855 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_hmac_oneshot.2631015542 Aug 22 04:41:33 AM UTC 24 Aug 22 04:45:04 AM UTC 24 3263238750 ps
T213 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3438432044 Aug 22 04:37:57 AM UTC 24 Aug 22 04:45:07 AM UTC 24 4658203215 ps
T46 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/coverage/default/0.rom_e2e_shutdown_output.1337775088 Aug 22 04:01:49 AM UTC 24 Aug 22 04:45:19 AM UTC 24 25771241318 ps
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