Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/chip_earlgrey_asic-sim-vcs/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	486	1			T619	1		T504	1		T569	3
all_values[1]	474	1			T414	1		T495	1		T569	1
all_values[2]	449	1			T569	1		T450	4		T764	1
all_values[3]	446	1			T504	1		T495	1		T505	1
all_values[4]	454	1			T504	3		T495	1		T399	1
all_values[5]	481	1			T414	1		T504	2		T505	1
all_values[6]	470	1			T414	1		T504	1		T495	1
all_values[7]	477	1			T414	2		T504	1		T495	1
all_values[8]	429	1			T414	1		T619	1		T504	1
all_values[9]	471	1			T776	1		T414	1		T505	1
all_values[10]	480	1			T414	1		T569	5		T455	1
all_values[11]	468	1			T505	2		T569	3		T450	2
all_values[12]	459	1			T504	1		T569	2		T455	1
all_values[13]	442	1			T495	1		T399	1		T505	1
all_values[14]	455	1			T499	1		T495	1		T399	1
all_values[15]	434	1			T504	1		T505	1		T569	1
all_values[16]	448	1			T399	1		T569	1		T455	1
all_values[17]	491	1			T504	1		T569	1		T419	1
all_values[18]	454	1			T505	1		T569	2		T455	1
all_values[19]	463	1			T414	1		T504	1		T495	1
all_values[20]	466	1			T414	1		T505	1		T569	1
all_values[21]	467	1			T504	3		T569	1		T601	1
all_values[22]	476	1			T504	1		T495	1		T399	1
all_values[23]	458	1			T504	1		T752	1		T569	2
all_values[24]	471	1			T495	1		T399	1		T716	2
all_values[25]	449	1			T414	1		T495	1		T428	1
all_values[26]	466	1			T619	1		T504	1		T495	1
all_values[27]	420	1			T504	1		T569	1		T455	1
all_values[28]	435	1			T499	1		T505	1		T569	3
all_values[29]	445	1			T414	1		T619	1		T504	3
all_values[30]	438	1			T504	1		T505	1		T569	1
all_values[31]	453	1			T399	1		T569	4		T450	4
all_values[32]	442	1			T504	1		T569	1		T455	2
all_values[33]	426	1			T414	2		T504	3		T495	2
all_values[34]	460	1			T504	3		T495	1		T505	1
all_values[35]	465	1			T414	1		T495	1		T569	1
all_values[36]	458	1			T504	1		T569	1		T450	4
all_values[37]	463	1			T414	1		T505	1		T569	1
all_values[38]	455	1			T504	1		T399	1		T601	1
all_values[39]	431	1			T504	1		T495	1		T505	1
all_values[40]	479	1			T619	1		T504	1		T495	1
all_values[41]	462	1			T504	2		T505	1		T569	2
all_values[42]	456	1			T505	1		T716	1		T601	1
all_values[43]	439	1			T569	2		T716	1		T419	1
all_values[44]	464	1			T504	2		T569	2		T716	1
all_values[45]	434	1			T499	2		T505	1		T450	3
all_values[46]	462	1			T414	1		T495	1		T399	1
all_values[47]	457	1			T504	2		T569	4		T455	1
all_values[48]	464	1			T414	1		T504	1		T569	5
all_values[49]	475	1			T504	1		T505	1		T455	1