Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}
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Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 64 0 64 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 3542 1 T413 1 T504 10 T495 4
all_values[1] 3529 1 T413 4 T494 2 T504 12
all_values[2] 3510 1 T413 4 T494 1 T504 15
all_values[3] 3519 1 T413 4 T494 1 T504 12
all_values[4] 3472 1 T413 2 T494 1 T504 12
all_values[5] 3416 1 T413 1 T494 1 T504 7
all_values[6] 3457 1 T413 1 T494 1 T504 22
all_values[7] 3412 1 T413 1 T504 11 T432 1
all_values[8] 3537 1 T413 4 T494 1 T504 11
all_values[9] 3500 1 T494 1 T504 12 T495 7
all_values[10] 3408 1 T413 1 T504 17 T495 5
all_values[11] 3428 1 T504 13 T495 12 T399 4
all_values[12] 3509 1 T413 3 T494 1 T504 17
all_values[13] 3603 1 T413 3 T504 10 T495 9
all_values[14] 3548 1 T494 1 T504 11 T495 1
all_values[15] 3615 1 T413 2 T494 2 T504 11
all_values[16] 3461 1 T413 3 T494 1 T504 7
all_values[17] 3572 1 T413 6 T494 1 T504 21
all_values[18] 3571 1 T494 2 T504 10 T432 1
all_values[19] 3480 1 T413 3 T494 2 T504 11
all_values[20] 3594 1 T413 2 T494 2 T504 13
all_values[21] 3560 1 T413 3 T494 2 T504 11
all_values[22] 3532 1 T413 3 T504 7 T432 1
all_values[23] 3623 1 T413 1 T494 1 T504 10
all_values[24] 3584 1 T413 2 T494 1 T504 17
all_values[25] 3539 1 T413 2 T494 2 T504 9
all_values[26] 3487 1 T413 5 T494 2 T504 13
all_values[27] 3422 1 T413 3 T494 2 T504 7
all_values[28] 3502 1 T413 2 T494 1 T504 15
all_values[29] 3511 1 T413 2 T504 10 T432 1
all_values[30] 3493 1 T413 2 T504 11 T432 1
all_values[31] 3471 1 T413 2 T504 13 T432 2
all_values[32] 3419 1 T413 2 T494 2 T504 8
all_values[33] 3582 1 T413 1 T494 2 T504 14
all_values[34] 3473 1 T413 2 T494 1 T504 14
all_values[35] 3548 1 T413 5 T494 2 T504 11
all_values[36] 3463 1 T413 1 T504 13 T432 2
all_values[37] 3633 1 T413 3 T494 1 T504 7
all_values[38] 3536 1 T413 1 T494 1 T504 12
all_values[39] 3547 1 T413 3 T494 1 T504 12
all_values[40] 3485 1 T413 2 T494 2 T504 10
all_values[41] 3478 1 T413 2 T504 10 T495 4
all_values[42] 3541 1 T413 1 T504 12 T432 1
all_values[43] 3403 1 T413 2 T504 12 T432 1
all_values[44] 3334 1 T413 4 T504 13 T432 1
all_values[45] 3562 1 T413 6 T494 2 T504 8
all_values[46] 3577 1 T413 3 T504 12 T432 2
all_values[47] 3435 1 T413 1 T494 1 T504 8
all_values[48] 3502 1 T413 2 T494 1 T504 13
all_values[49] 3468 1 T413 2 T494 2 T504 8
all_values[50] 3472 1 T413 1 T494 1 T504 13
all_values[51] 3411 1 T413 1 T494 1 T504 12
all_values[52] 3459 1 T413 3 T494 1 T504 9
all_values[53] 3523 1 T494 1 T504 14 T432 1
all_values[54] 3482 1 T494 1 T504 14 T495 3
all_values[55] 3501 1 T413 4 T494 2 T504 16
all_values[56] 3658 1 T413 3 T504 17 T432 1
all_values[57] 3492 1 T413 3 T494 1 T504 12
all_values[58] 3501 1 T413 2 T494 3 T504 11
all_values[59] 3570 1 T413 3 T494 1 T504 12
all_values[60] 3492 1 T413 2 T494 1 T504 7
all_values[61] 3474 1 T413 2 T494 2 T504 13
all_values[62] 3583 1 T413 8 T504 17 T495 5
all_values[63] 3507 1 T413 2 T504 6 T432 3

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