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757 // define mixed connection to port
758 1/1 assign edn0_edn_req[2] = ast_edn_req_i;
Tests: T1 T2 T3
759 1/1 assign ast_edn_rsp_o = edn0_edn_rsp[2];
Tests: T1 T2 T3
760 1/1 assign ast_lc_dft_en_o = lc_ctrl_lc_dft_en;
Tests: T1 T2 T3
761 0/1 ==> assign ast_obs_ctrl = obs_ctrl_i;
762 0/1 ==> assign ast_ram_1p_cfg = ram_1p_cfg_i;
763 0/1 ==> assign ast_spi_ram_2p_cfg = spi_ram_2p_cfg_i;
764 0/1 ==> assign ast_usb_ram_1p_cfg = usb_ram_1p_cfg_i;
765 0/1 ==> assign ast_rom_cfg = rom_cfg_i;
766
767 // define partial inter-module tie-off
768 otp_ctrl_pkg::sram_otp_key_rsp_t unused_otp_ctrl_sram_otp_key_rsp3;
769 edn_pkg::edn_rsp_t unused_edn1_edn_rsp1;
770 edn_pkg::edn_rsp_t unused_edn1_edn_rsp2;
771 edn_pkg::edn_rsp_t unused_edn1_edn_rsp3;
772 edn_pkg::edn_rsp_t unused_edn1_edn_rsp4;
773 edn_pkg::edn_rsp_t unused_edn1_edn_rsp5;
774 edn_pkg::edn_rsp_t unused_edn1_edn_rsp6;
775 edn_pkg::edn_rsp_t unused_edn1_edn_rsp7;
776
777 // assign partial inter-module tie-off
778 1/1 assign unused_otp_ctrl_sram_otp_key_rsp3 = otp_ctrl_sram_otp_key_rsp[3];
Tests: T1 T2 T3
779 0/1 ==> assign unused_edn1_edn_rsp1 = edn1_edn_rsp[1];
780 0/1 ==> assign unused_edn1_edn_rsp2 = edn1_edn_rsp[2];
781 0/1 ==> assign unused_edn1_edn_rsp3 = edn1_edn_rsp[3];
782 0/1 ==> assign unused_edn1_edn_rsp4 = edn1_edn_rsp[4];
783 0/1 ==> assign unused_edn1_edn_rsp5 = edn1_edn_rsp[5];
784 0/1 ==> assign unused_edn1_edn_rsp6 = edn1_edn_rsp[6];
785 0/1 ==> assign unused_edn1_edn_rsp7 = edn1_edn_rsp[7];
786 assign otp_ctrl_sram_otp_key_req[3] = '0;
787 assign edn1_edn_req[1] = '0;
788 assign edn1_edn_req[2] = '0;
789 assign edn1_edn_req[3] = '0;
790 assign edn1_edn_req[4] = '0;
791 assign edn1_edn_req[5] = '0;
792 assign edn1_edn_req[6] = '0;
793 assign edn1_edn_req[7] = '0;
794
795
796 // OTP HW_CFG* Broadcast signals.
797 // TODO(#6713): The actual struct breakout and mapping currently needs to
798 // be performed by hand.
799 1/1 assign csrng_otp_en_csrng_sw_app_read =
Tests: T1 T2 T3
800 otp_ctrl_otp_broadcast.hw_cfg1_data.en_csrng_sw_app_read;
801 1/1 assign sram_ctrl_main_otp_en_sram_ifetch =
Tests: T1 T2 T3
802 otp_ctrl_otp_broadcast.hw_cfg1_data.en_sram_ifetch;
803 1/1 assign rv_dm_otp_dis_rv_dm_late_debug =
Tests: T1 T2 T3
804 otp_ctrl_otp_broadcast.hw_cfg1_data.dis_rv_dm_late_debug;
805 1/1 assign lc_ctrl_otp_device_id =
Tests: T1 T2 T3
806 otp_ctrl_otp_broadcast.hw_cfg0_data.device_id;
807 1/1 assign lc_ctrl_otp_manuf_state =
Tests: T1 T2 T3
808 otp_ctrl_otp_broadcast.hw_cfg0_data.manuf_state;
809 1/1 assign keymgr_otp_device_id =
Tests: T1 T2 T3
810 otp_ctrl_otp_broadcast.hw_cfg0_data.device_id;
811
812 logic unused_otp_broadcast_bits;
813 1/1 assign unused_otp_broadcast_bits = ^{
Tests: T1 T2 T3
814 otp_ctrl_otp_broadcast.valid,
815 otp_ctrl_otp_broadcast.hw_cfg0_data.hw_cfg0_digest,
816 otp_ctrl_otp_broadcast.hw_cfg1_data.hw_cfg1_digest,
817 otp_ctrl_otp_broadcast.hw_cfg1_data.unallocated
818 };
819
820 // See #7978 This below is a hack.
821 // This is because ast is a comportable-like module that sits outside
822 // of top_earlgrey's boundary.
823 1/1 assign clks_ast_o = clkmgr_aon_clocks;
Tests: T1 T2 T3
824 1/1 assign rsts_ast_o = rstmgr_aon_resets;
Tests: T1 T2 T3
825
826 // ibex specific assignments
827 // TODO: This should be further automated in the future.
828 1/1 assign rv_core_ibex_irq_timer = intr_rv_timer_timer_expired_hart0_timer0;
Tests: T115 T116 T117
829 assign rv_core_ibex_hart_id = '0;
830
831 assign rv_core_ibex_boot_addr = ADDR_SPACE_ROM_CTRL__ROM;
832
833
834 // Struct breakout module tool-inserted DFT TAP signals
835 pinmux_jtag_breakout u_dft_tap_breakout (
836 .req_i (pinmux_aon_dft_jtag_req),
837 .rsp_o (pinmux_aon_dft_jtag_rsp),
838 .tck_o (),
839 .trst_no (),
840 .tms_o (),
841 .tdi_o (),
842 .tdo_i (1'b0),
843 .tdo_oe_i (1'b0)
844 );
845
846 // Wire up alert handler LPGs
847 prim_mubi_pkg::mubi4_t [alert_pkg::NLpg-1:0] lpg_cg_en;
848 prim_mubi_pkg::mubi4_t [alert_pkg::NLpg-1:0] lpg_rst_en;
849
850
851 // peri_lc_io_div4_0
852 1/1 assign lpg_cg_en[0] = clkmgr_aon_cg_en.io_div4_peri;
Tests: T1 T2 T3
853 1/1 assign lpg_rst_en[0] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
854 // peri_spi_device_0
855 1/1 assign lpg_cg_en[1] = clkmgr_aon_cg_en.io_div4_peri;
Tests: T1 T2 T3
856 1/1 assign lpg_rst_en[1] = rstmgr_aon_rst_en.spi_device[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
857 // peri_i2c0_0
858 1/1 assign lpg_cg_en[2] = clkmgr_aon_cg_en.io_div4_peri;
Tests: T1 T2 T3
859 1/1 assign lpg_rst_en[2] = rstmgr_aon_rst_en.i2c0[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
860 // peri_i2c1_0
861 1/1 assign lpg_cg_en[3] = clkmgr_aon_cg_en.io_div4_peri;
Tests: T1 T2 T3
862 1/1 assign lpg_rst_en[3] = rstmgr_aon_rst_en.i2c1[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
863 // peri_i2c2_0
864 1/1 assign lpg_cg_en[4] = clkmgr_aon_cg_en.io_div4_peri;
Tests: T1 T2 T3
865 1/1 assign lpg_rst_en[4] = rstmgr_aon_rst_en.i2c2[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
866 // timers_lc_io_div4_0
867 1/1 assign lpg_cg_en[5] = clkmgr_aon_cg_en.io_div4_timers;
Tests: T1 T2 T3
868 1/1 assign lpg_rst_en[5] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
869 // secure_lc_io_div4_0
870 1/1 assign lpg_cg_en[6] = clkmgr_aon_cg_en.io_div4_secure;
Tests: T1 T2 T3
871 1/1 assign lpg_rst_en[6] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
872 // peri_spi_host0_0
873 1/1 assign lpg_cg_en[7] = clkmgr_aon_cg_en.io_peri;
Tests: T1 T2 T3
874 1/1 assign lpg_rst_en[7] = rstmgr_aon_rst_en.spi_host0[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
875 // peri_spi_host1_0
876 1/1 assign lpg_cg_en[8] = clkmgr_aon_cg_en.io_div2_peri;
Tests: T1 T2 T3
877 1/1 assign lpg_rst_en[8] = rstmgr_aon_rst_en.spi_host1[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
878 // peri_usb_0
879 1/1 assign lpg_cg_en[9] = clkmgr_aon_cg_en.usb_peri;
Tests: T1 T2 T3
880 1/1 assign lpg_rst_en[9] = rstmgr_aon_rst_en.usb[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
881 // powerup_por_io_div4_Aon
882 0/1 ==> assign lpg_cg_en[10] = clkmgr_aon_cg_en.io_div4_powerup;
883 1/1 assign lpg_rst_en[10] = rstmgr_aon_rst_en.por_io_div4[rstmgr_pkg::DomainAonSel];
Tests: T1 T2 T3
884 // powerup_lc_io_div4_Aon
885 0/1 ==> assign lpg_cg_en[11] = clkmgr_aon_cg_en.io_div4_powerup;
886 1/1 assign lpg_rst_en[11] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel];
Tests: T1 T2 T3
887 // secure_lc_io_div4_Aon
888 1/1 assign lpg_cg_en[12] = clkmgr_aon_cg_en.io_div4_secure;
Tests: T1 T2 T3
889 1/1 assign lpg_rst_en[12] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel];
Tests: T1 T2 T3
890 // peri_lc_io_div4_Aon
891 1/1 assign lpg_cg_en[13] = clkmgr_aon_cg_en.io_div4_peri;
Tests: T1 T2 T3
892 1/1 assign lpg_rst_en[13] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel];
Tests: T1 T2 T3
893 // timers_lc_io_div4_Aon
894 1/1 assign lpg_cg_en[14] = clkmgr_aon_cg_en.io_div4_timers;
Tests: T1 T2 T3
895 1/1 assign lpg_rst_en[14] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel];
Tests: T1 T2 T3
896 // infra_lc_io_div4_0
897 1/1 assign lpg_cg_en[15] = clkmgr_aon_cg_en.io_div4_infra;
Tests: T1 T2 T3
898 1/1 assign lpg_rst_en[15] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
899 // infra_lc_io_div4_Aon
900 1/1 assign lpg_cg_en[16] = clkmgr_aon_cg_en.io_div4_infra;
Tests: T1 T2 T3
901 1/1 assign lpg_rst_en[16] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::DomainAonSel];
Tests: T1 T2 T3
902 // infra_lc_0
903 1/1 assign lpg_cg_en[17] = clkmgr_aon_cg_en.main_infra;
Tests: T1 T2 T3
904 1/1 assign lpg_rst_en[17] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
905 // infra_sys_0
906 1/1 assign lpg_cg_en[18] = clkmgr_aon_cg_en.main_infra;
Tests: T1 T2 T3
907 1/1 assign lpg_rst_en[18] = rstmgr_aon_rst_en.sys[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
908 // secure_lc_0
909 1/1 assign lpg_cg_en[19] = clkmgr_aon_cg_en.main_secure;
Tests: T1 T2 T3
910 1/1 assign lpg_rst_en[19] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
911 // aes_trans_lc_0
912 1/1 assign lpg_cg_en[20] = clkmgr_aon_cg_en.main_aes;
Tests: T1 T2 T3
913 1/1 assign lpg_rst_en[20] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
914 // hmac_trans_lc_0
915 1/1 assign lpg_cg_en[21] = clkmgr_aon_cg_en.main_hmac;
Tests: T1 T2 T3
916 1/1 assign lpg_rst_en[21] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
917 // kmac_trans_lc_0
918 1/1 assign lpg_cg_en[22] = clkmgr_aon_cg_en.main_kmac;
Tests: T1 T2 T3
919 1/1 assign lpg_rst_en[22] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
920 // otbn_trans_lc_0
921 1/1 assign lpg_cg_en[23] = clkmgr_aon_cg_en.main_otbn;
Tests: T1 T2 T3
922 1/1 assign lpg_rst_en[23] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel];
Tests: T1 T2 T3
923
924 // tie-off unused connections
925 //VCS coverage off
926 // pragma coverage off
927 prim_mubi_pkg::mubi4_t unused_cg_en_0;
928 unreachable assign unused_cg_en_0 = clkmgr_aon_cg_en.aon_powerup;
929 prim_mubi_pkg::mubi4_t unused_cg_en_1;
930 unreachable assign unused_cg_en_1 = clkmgr_aon_cg_en.main_powerup;
931 prim_mubi_pkg::mubi4_t unused_cg_en_2;
932 unreachable assign unused_cg_en_2 = clkmgr_aon_cg_en.io_powerup;
933 prim_mubi_pkg::mubi4_t unused_cg_en_3;
934 unreachable assign unused_cg_en_3 = clkmgr_aon_cg_en.usb_powerup;
935 prim_mubi_pkg::mubi4_t unused_cg_en_4;
936 unreachable assign unused_cg_en_4 = clkmgr_aon_cg_en.io_div2_powerup;
937 prim_mubi_pkg::mubi4_t unused_cg_en_5;
938 unreachable assign unused_cg_en_5 = clkmgr_aon_cg_en.aon_secure;
939 prim_mubi_pkg::mubi4_t unused_cg_en_6;
940 unreachable assign unused_cg_en_6 = clkmgr_aon_cg_en.aon_peri;
941 prim_mubi_pkg::mubi4_t unused_cg_en_7;
942 unreachable assign unused_cg_en_7 = clkmgr_aon_cg_en.aon_timers;
943 prim_mubi_pkg::mubi4_t unused_cg_en_8;
944 unreachable assign unused_cg_en_8 = clkmgr_aon_cg_en.usb_infra;
945 prim_mubi_pkg::mubi4_t unused_cg_en_9;
946 unreachable assign unused_cg_en_9 = clkmgr_aon_cg_en.io_infra;
947 prim_mubi_pkg::mubi4_t unused_cg_en_10;
948 unreachable assign unused_cg_en_10 = clkmgr_aon_cg_en.io_div2_infra;
949 prim_mubi_pkg::mubi4_t unused_rst_en_0;
950 unreachable assign unused_rst_en_0 = rstmgr_aon_rst_en.por_aon[rstmgr_pkg::DomainAonSel];
951 prim_mubi_pkg::mubi4_t unused_rst_en_1;
952 unreachable assign unused_rst_en_1 = rstmgr_aon_rst_en.por_aon[rstmgr_pkg::Domain0Sel];
953 prim_mubi_pkg::mubi4_t unused_rst_en_2;
954 unreachable assign unused_rst_en_2 = rstmgr_aon_rst_en.por[rstmgr_pkg::DomainAonSel];
955 prim_mubi_pkg::mubi4_t unused_rst_en_3;
956 unreachable assign unused_rst_en_3 = rstmgr_aon_rst_en.por[rstmgr_pkg::Domain0Sel];
957 prim_mubi_pkg::mubi4_t unused_rst_en_4;
958 unreachable assign unused_rst_en_4 = rstmgr_aon_rst_en.por_io[rstmgr_pkg::DomainAonSel];
959 prim_mubi_pkg::mubi4_t unused_rst_en_5;
960 unreachable assign unused_rst_en_5 = rstmgr_aon_rst_en.por_io[rstmgr_pkg::Domain0Sel];
961 prim_mubi_pkg::mubi4_t unused_rst_en_6;
962 unreachable assign unused_rst_en_6 = rstmgr_aon_rst_en.por_io_div2[rstmgr_pkg::DomainAonSel];
963 prim_mubi_pkg::mubi4_t unused_rst_en_7;
964 unreachable assign unused_rst_en_7 = rstmgr_aon_rst_en.por_io_div2[rstmgr_pkg::Domain0Sel];
965 prim_mubi_pkg::mubi4_t unused_rst_en_8;
966 unreachable assign unused_rst_en_8 = rstmgr_aon_rst_en.por_io_div4[rstmgr_pkg::Domain0Sel];
967 prim_mubi_pkg::mubi4_t unused_rst_en_9;
968 unreachable assign unused_rst_en_9 = rstmgr_aon_rst_en.por_usb[rstmgr_pkg::DomainAonSel];
969 prim_mubi_pkg::mubi4_t unused_rst_en_10;
970 unreachable assign unused_rst_en_10 = rstmgr_aon_rst_en.por_usb[rstmgr_pkg::Domain0Sel];
971 prim_mubi_pkg::mubi4_t unused_rst_en_11;
972 unreachable assign unused_rst_en_11 = rstmgr_aon_rst_en.lc_shadowed[rstmgr_pkg::DomainAonSel];
973 prim_mubi_pkg::mubi4_t unused_rst_en_12;
974 unreachable assign unused_rst_en_12 = rstmgr_aon_rst_en.lc[rstmgr_pkg::DomainAonSel];
975 prim_mubi_pkg::mubi4_t unused_rst_en_13;
976 unreachable assign unused_rst_en_13 = rstmgr_aon_rst_en.lc_shadowed[rstmgr_pkg::Domain0Sel];
977 prim_mubi_pkg::mubi4_t unused_rst_en_14;
978 unreachable assign unused_rst_en_14 = rstmgr_aon_rst_en.lc_aon[rstmgr_pkg::DomainAonSel];
979 prim_mubi_pkg::mubi4_t unused_rst_en_15;
980 unreachable assign unused_rst_en_15 = rstmgr_aon_rst_en.lc_aon[rstmgr_pkg::Domain0Sel];
981 prim_mubi_pkg::mubi4_t unused_rst_en_16;
982 unreachable assign unused_rst_en_16 = rstmgr_aon_rst_en.lc_io[rstmgr_pkg::DomainAonSel];
983 prim_mubi_pkg::mubi4_t unused_rst_en_17;
984 unreachable assign unused_rst_en_17 = rstmgr_aon_rst_en.lc_io[rstmgr_pkg::Domain0Sel];
985 prim_mubi_pkg::mubi4_t unused_rst_en_18;
986 unreachable assign unused_rst_en_18 = rstmgr_aon_rst_en.lc_io_div2[rstmgr_pkg::DomainAonSel];
987 prim_mubi_pkg::mubi4_t unused_rst_en_19;
988 unreachable assign unused_rst_en_19 = rstmgr_aon_rst_en.lc_io_div2[rstmgr_pkg::Domain0Sel];
989 prim_mubi_pkg::mubi4_t unused_rst_en_20;
990 unreachable assign unused_rst_en_20 = rstmgr_aon_rst_en.lc_io_div4_shadowed[rstmgr_pkg::DomainAonSel];
991 prim_mubi_pkg::mubi4_t unused_rst_en_21;
992 unreachable assign unused_rst_en_21 = rstmgr_aon_rst_en.lc_io_div4_shadowed[rstmgr_pkg::Domain0Sel];
993 prim_mubi_pkg::mubi4_t unused_rst_en_22;
994 unreachable assign unused_rst_en_22 = rstmgr_aon_rst_en.lc_usb[rstmgr_pkg::DomainAonSel];
995 prim_mubi_pkg::mubi4_t unused_rst_en_23;
996 unreachable assign unused_rst_en_23 = rstmgr_aon_rst_en.lc_usb[rstmgr_pkg::Domain0Sel];
997 prim_mubi_pkg::mubi4_t unused_rst_en_24;
998 unreachable assign unused_rst_en_24 = rstmgr_aon_rst_en.sys[rstmgr_pkg::DomainAonSel];
999 prim_mubi_pkg::mubi4_t unused_rst_en_25;
1000 unreachable assign unused_rst_en_25 = rstmgr_aon_rst_en.sys_io_div4[rstmgr_pkg::DomainAonSel];
1001 prim_mubi_pkg::mubi4_t unused_rst_en_26;
1002 unreachable assign unused_rst_en_26 = rstmgr_aon_rst_en.sys_io_div4[rstmgr_pkg::Domain0Sel];
1003 prim_mubi_pkg::mubi4_t unused_rst_en_27;
1004 unreachable assign unused_rst_en_27 = rstmgr_aon_rst_en.spi_device[rstmgr_pkg::DomainAonSel];
1005 prim_mubi_pkg::mubi4_t unused_rst_en_28;
1006 unreachable assign unused_rst_en_28 = rstmgr_aon_rst_en.spi_host0[rstmgr_pkg::DomainAonSel];
1007 prim_mubi_pkg::mubi4_t unused_rst_en_29;
1008 unreachable assign unused_rst_en_29 = rstmgr_aon_rst_en.spi_host1[rstmgr_pkg::DomainAonSel];
1009 prim_mubi_pkg::mubi4_t unused_rst_en_30;
1010 unreachable assign unused_rst_en_30 = rstmgr_aon_rst_en.usb[rstmgr_pkg::DomainAonSel];
1011 prim_mubi_pkg::mubi4_t unused_rst_en_31;
1012 unreachable assign unused_rst_en_31 = rstmgr_aon_rst_en.usb_aon[rstmgr_pkg::DomainAonSel];
1013 prim_mubi_pkg::mubi4_t unused_rst_en_32;
1014 unreachable assign unused_rst_en_32 = rstmgr_aon_rst_en.usb_aon[rstmgr_pkg::Domain0Sel];
1015 prim_mubi_pkg::mubi4_t unused_rst_en_33;
1016 unreachable assign unused_rst_en_33 = rstmgr_aon_rst_en.i2c0[rstmgr_pkg::DomainAonSel];
1017 prim_mubi_pkg::mubi4_t unused_rst_en_34;
1018 unreachable assign unused_rst_en_34 = rstmgr_aon_rst_en.i2c1[rstmgr_pkg::DomainAonSel];
1019 prim_mubi_pkg::mubi4_t unused_rst_en_35;
1020 unreachable assign unused_rst_en_35 = rstmgr_aon_rst_en.i2c2[rstmgr_pkg::DomainAonSel];
1021 //VCS coverage on
1022 // pragma coverage on
1023
1024 // Peripheral Instantiation
1025
1026
1027 uart #(
1028 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[0:0])
1029 ) u_uart0 (
1030
1031 // Input
1032 .cio_rx_i (cio_uart0_rx_p2d),
1033
1034 // Output
1035 .cio_tx_o (cio_uart0_tx_d2p),
1036 .cio_tx_en_o (cio_uart0_tx_en_d2p),
1037
1038 // Interrupt
1039 .intr_tx_watermark_o (intr_uart0_tx_watermark),
1040 .intr_rx_watermark_o (intr_uart0_rx_watermark),
1041 .intr_tx_done_o (intr_uart0_tx_done),
1042 .intr_rx_overflow_o (intr_uart0_rx_overflow),
1043 .intr_rx_frame_err_o (intr_uart0_rx_frame_err),
1044 .intr_rx_break_err_o (intr_uart0_rx_break_err),
1045 .intr_rx_timeout_o (intr_uart0_rx_timeout),
1046 .intr_rx_parity_err_o (intr_uart0_rx_parity_err),
1047 .intr_tx_empty_o (intr_uart0_tx_empty),
1048 // [0]: fatal_fault
1049 .alert_tx_o ( alert_tx[0:0] ),
1050 .alert_rx_i ( alert_rx[0:0] ),
1051
1052 // Inter-module signals
1053 .tl_i(uart0_tl_req),
1054 .tl_o(uart0_tl_rsp),
1055
1056 // Clock and reset connections
1057 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1058 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
1059 );
1060 uart #(
1061 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[1:1])
1062 ) u_uart1 (
1063
1064 // Input
1065 .cio_rx_i (cio_uart1_rx_p2d),
1066
1067 // Output
1068 .cio_tx_o (cio_uart1_tx_d2p),
1069 .cio_tx_en_o (cio_uart1_tx_en_d2p),
1070
1071 // Interrupt
1072 .intr_tx_watermark_o (intr_uart1_tx_watermark),
1073 .intr_rx_watermark_o (intr_uart1_rx_watermark),
1074 .intr_tx_done_o (intr_uart1_tx_done),
1075 .intr_rx_overflow_o (intr_uart1_rx_overflow),
1076 .intr_rx_frame_err_o (intr_uart1_rx_frame_err),
1077 .intr_rx_break_err_o (intr_uart1_rx_break_err),
1078 .intr_rx_timeout_o (intr_uart1_rx_timeout),
1079 .intr_rx_parity_err_o (intr_uart1_rx_parity_err),
1080 .intr_tx_empty_o (intr_uart1_tx_empty),
1081 // [1]: fatal_fault
1082 .alert_tx_o ( alert_tx[1:1] ),
1083 .alert_rx_i ( alert_rx[1:1] ),
1084
1085 // Inter-module signals
1086 .tl_i(uart1_tl_req),
1087 .tl_o(uart1_tl_rsp),
1088
1089 // Clock and reset connections
1090 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1091 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
1092 );
1093 uart #(
1094 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[2:2])
1095 ) u_uart2 (
1096
1097 // Input
1098 .cio_rx_i (cio_uart2_rx_p2d),
1099
1100 // Output
1101 .cio_tx_o (cio_uart2_tx_d2p),
1102 .cio_tx_en_o (cio_uart2_tx_en_d2p),
1103
1104 // Interrupt
1105 .intr_tx_watermark_o (intr_uart2_tx_watermark),
1106 .intr_rx_watermark_o (intr_uart2_rx_watermark),
1107 .intr_tx_done_o (intr_uart2_tx_done),
1108 .intr_rx_overflow_o (intr_uart2_rx_overflow),
1109 .intr_rx_frame_err_o (intr_uart2_rx_frame_err),
1110 .intr_rx_break_err_o (intr_uart2_rx_break_err),
1111 .intr_rx_timeout_o (intr_uart2_rx_timeout),
1112 .intr_rx_parity_err_o (intr_uart2_rx_parity_err),
1113 .intr_tx_empty_o (intr_uart2_tx_empty),
1114 // [2]: fatal_fault
1115 .alert_tx_o ( alert_tx[2:2] ),
1116 .alert_rx_i ( alert_rx[2:2] ),
1117
1118 // Inter-module signals
1119 .tl_i(uart2_tl_req),
1120 .tl_o(uart2_tl_rsp),
1121
1122 // Clock and reset connections
1123 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1124 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
1125 );
1126 uart #(
1127 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[3:3])
1128 ) u_uart3 (
1129
1130 // Input
1131 .cio_rx_i (cio_uart3_rx_p2d),
1132
1133 // Output
1134 .cio_tx_o (cio_uart3_tx_d2p),
1135 .cio_tx_en_o (cio_uart3_tx_en_d2p),
1136
1137 // Interrupt
1138 .intr_tx_watermark_o (intr_uart3_tx_watermark),
1139 .intr_rx_watermark_o (intr_uart3_rx_watermark),
1140 .intr_tx_done_o (intr_uart3_tx_done),
1141 .intr_rx_overflow_o (intr_uart3_rx_overflow),
1142 .intr_rx_frame_err_o (intr_uart3_rx_frame_err),
1143 .intr_rx_break_err_o (intr_uart3_rx_break_err),
1144 .intr_rx_timeout_o (intr_uart3_rx_timeout),
1145 .intr_rx_parity_err_o (intr_uart3_rx_parity_err),
1146 .intr_tx_empty_o (intr_uart3_tx_empty),
1147 // [3]: fatal_fault
1148 .alert_tx_o ( alert_tx[3:3] ),
1149 .alert_rx_i ( alert_rx[3:3] ),
1150
1151 // Inter-module signals
1152 .tl_i(uart3_tl_req),
1153 .tl_o(uart3_tl_rsp),
1154
1155 // Clock and reset connections
1156 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1157 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
1158 );
1159 gpio #(
1160 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[4:4]),
1161 .GpioAsyncOn(GpioGpioAsyncOn)
1162 ) u_gpio (
1163
1164 // Input
1165 .cio_gpio_i (cio_gpio_gpio_p2d),
1166
1167 // Output
1168 .cio_gpio_o (cio_gpio_gpio_d2p),
1169 .cio_gpio_en_o (cio_gpio_gpio_en_d2p),
1170
1171 // Interrupt
1172 .intr_gpio_o (intr_gpio_gpio),
1173 // [4]: fatal_fault
1174 .alert_tx_o ( alert_tx[4:4] ),
1175 .alert_rx_i ( alert_rx[4:4] ),
1176
1177 // Inter-module signals
1178 .tl_i(gpio_tl_req),
1179 .tl_o(gpio_tl_rsp),
1180
1181 // Clock and reset connections
1182 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1183 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
1184 );
1185 spi_device #(
1186 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[5:5]),
1187 .SramType(SpiDeviceSramType)
1188 ) u_spi_device (
1189
1190 // Input
1191 .cio_sck_i (cio_spi_device_sck_p2d),
1192 .cio_csb_i (cio_spi_device_csb_p2d),
1193 .cio_tpm_csb_i (cio_spi_device_tpm_csb_p2d),
1194 .cio_sd_i (cio_spi_device_sd_p2d),
1195
1196 // Output
1197 .cio_sd_o (cio_spi_device_sd_d2p),
1198 .cio_sd_en_o (cio_spi_device_sd_en_d2p),
1199
1200 // Interrupt
1201 .intr_upload_cmdfifo_not_empty_o (intr_spi_device_upload_cmdfifo_not_empty),
1202 .intr_upload_payload_not_empty_o (intr_spi_device_upload_payload_not_empty),
1203 .intr_upload_payload_overflow_o (intr_spi_device_upload_payload_overflow),
1204 .intr_readbuf_watermark_o (intr_spi_device_readbuf_watermark),
1205 .intr_readbuf_flip_o (intr_spi_device_readbuf_flip),
1206 .intr_tpm_header_not_empty_o (intr_spi_device_tpm_header_not_empty),
1207 .intr_tpm_rdfifo_cmd_end_o (intr_spi_device_tpm_rdfifo_cmd_end),
1208 .intr_tpm_rdfifo_drop_o (intr_spi_device_tpm_rdfifo_drop),
1209 // [5]: fatal_fault
1210 .alert_tx_o ( alert_tx[5:5] ),
1211 .alert_rx_i ( alert_rx[5:5] ),
1212
1213 // Inter-module signals
1214 .ram_cfg_i(ast_spi_ram_2p_cfg),
1215 .passthrough_o(spi_device_passthrough_req),
1216 .passthrough_i(spi_device_passthrough_rsp),
1217 .mbist_en_i('0),
1218 .sck_monitor_o(sck_monitor_o),
1219 .tl_i(spi_device_tl_req),
1220 .tl_o(spi_device_tl_rsp),
1221 .scanmode_i,
1222 .scan_rst_ni,
1223
1224 // Clock and reset connections
1225 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1226 .scan_clk_i (clkmgr_aon_clocks.clk_io_div2_peri),
1227 .rst_ni (rstmgr_aon_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel])
1228 );
1229 i2c #(
1230 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[6:6]),
1231 .InputDelayCycles(I2c0InputDelayCycles)
1232 ) u_i2c0 (
1233
1234 // Input
1235 .cio_sda_i (cio_i2c0_sda_p2d),
1236 .cio_scl_i (cio_i2c0_scl_p2d),
1237
1238 // Output
1239 .cio_sda_o (cio_i2c0_sda_d2p),
1240 .cio_sda_en_o (cio_i2c0_sda_en_d2p),
1241 .cio_scl_o (cio_i2c0_scl_d2p),
1242 .cio_scl_en_o (cio_i2c0_scl_en_d2p),
1243
1244 // Interrupt
1245 .intr_fmt_threshold_o (intr_i2c0_fmt_threshold),
1246 .intr_rx_threshold_o (intr_i2c0_rx_threshold),
1247 .intr_acq_threshold_o (intr_i2c0_acq_threshold),
1248 .intr_rx_overflow_o (intr_i2c0_rx_overflow),
1249 .intr_controller_halt_o (intr_i2c0_controller_halt),
1250 .intr_scl_interference_o (intr_i2c0_scl_interference),
1251 .intr_sda_interference_o (intr_i2c0_sda_interference),
1252 .intr_stretch_timeout_o (intr_i2c0_stretch_timeout),
1253 .intr_sda_unstable_o (intr_i2c0_sda_unstable),
1254 .intr_cmd_complete_o (intr_i2c0_cmd_complete),
1255 .intr_tx_stretch_o (intr_i2c0_tx_stretch),
1256 .intr_tx_threshold_o (intr_i2c0_tx_threshold),
1257 .intr_acq_stretch_o (intr_i2c0_acq_stretch),
1258 .intr_unexp_stop_o (intr_i2c0_unexp_stop),
1259 .intr_host_timeout_o (intr_i2c0_host_timeout),
1260 // [6]: fatal_fault
1261 .alert_tx_o ( alert_tx[6:6] ),
1262 .alert_rx_i ( alert_rx[6:6] ),
1263
1264 // Inter-module signals
1265 .ram_cfg_i(ast_ram_1p_cfg),
1266 .tl_i(i2c0_tl_req),
1267 .tl_o(i2c0_tl_rsp),
1268
1269 // Clock and reset connections
1270 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1271 .rst_ni (rstmgr_aon_resets.rst_i2c0_n[rstmgr_pkg::Domain0Sel])
1272 );
1273 i2c #(
1274 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[7:7]),
1275 .InputDelayCycles(I2c1InputDelayCycles)
1276 ) u_i2c1 (
1277
1278 // Input
1279 .cio_sda_i (cio_i2c1_sda_p2d),
1280 .cio_scl_i (cio_i2c1_scl_p2d),
1281
1282 // Output
1283 .cio_sda_o (cio_i2c1_sda_d2p),
1284 .cio_sda_en_o (cio_i2c1_sda_en_d2p),
1285 .cio_scl_o (cio_i2c1_scl_d2p),
1286 .cio_scl_en_o (cio_i2c1_scl_en_d2p),
1287
1288 // Interrupt
1289 .intr_fmt_threshold_o (intr_i2c1_fmt_threshold),
1290 .intr_rx_threshold_o (intr_i2c1_rx_threshold),
1291 .intr_acq_threshold_o (intr_i2c1_acq_threshold),
1292 .intr_rx_overflow_o (intr_i2c1_rx_overflow),
1293 .intr_controller_halt_o (intr_i2c1_controller_halt),
1294 .intr_scl_interference_o (intr_i2c1_scl_interference),
1295 .intr_sda_interference_o (intr_i2c1_sda_interference),
1296 .intr_stretch_timeout_o (intr_i2c1_stretch_timeout),
1297 .intr_sda_unstable_o (intr_i2c1_sda_unstable),
1298 .intr_cmd_complete_o (intr_i2c1_cmd_complete),
1299 .intr_tx_stretch_o (intr_i2c1_tx_stretch),
1300 .intr_tx_threshold_o (intr_i2c1_tx_threshold),
1301 .intr_acq_stretch_o (intr_i2c1_acq_stretch),
1302 .intr_unexp_stop_o (intr_i2c1_unexp_stop),
1303 .intr_host_timeout_o (intr_i2c1_host_timeout),
1304 // [7]: fatal_fault
1305 .alert_tx_o ( alert_tx[7:7] ),
1306 .alert_rx_i ( alert_rx[7:7] ),
1307
1308 // Inter-module signals
1309 .ram_cfg_i(ast_ram_1p_cfg),
1310 .tl_i(i2c1_tl_req),
1311 .tl_o(i2c1_tl_rsp),
1312
1313 // Clock and reset connections
1314 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1315 .rst_ni (rstmgr_aon_resets.rst_i2c1_n[rstmgr_pkg::Domain0Sel])
1316 );
1317 i2c #(
1318 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[8:8]),
1319 .InputDelayCycles(I2c2InputDelayCycles)
1320 ) u_i2c2 (
1321
1322 // Input
1323 .cio_sda_i (cio_i2c2_sda_p2d),
1324 .cio_scl_i (cio_i2c2_scl_p2d),
1325
1326 // Output
1327 .cio_sda_o (cio_i2c2_sda_d2p),
1328 .cio_sda_en_o (cio_i2c2_sda_en_d2p),
1329 .cio_scl_o (cio_i2c2_scl_d2p),
1330 .cio_scl_en_o (cio_i2c2_scl_en_d2p),
1331
1332 // Interrupt
1333 .intr_fmt_threshold_o (intr_i2c2_fmt_threshold),
1334 .intr_rx_threshold_o (intr_i2c2_rx_threshold),
1335 .intr_acq_threshold_o (intr_i2c2_acq_threshold),
1336 .intr_rx_overflow_o (intr_i2c2_rx_overflow),
1337 .intr_controller_halt_o (intr_i2c2_controller_halt),
1338 .intr_scl_interference_o (intr_i2c2_scl_interference),
1339 .intr_sda_interference_o (intr_i2c2_sda_interference),
1340 .intr_stretch_timeout_o (intr_i2c2_stretch_timeout),
1341 .intr_sda_unstable_o (intr_i2c2_sda_unstable),
1342 .intr_cmd_complete_o (intr_i2c2_cmd_complete),
1343 .intr_tx_stretch_o (intr_i2c2_tx_stretch),
1344 .intr_tx_threshold_o (intr_i2c2_tx_threshold),
1345 .intr_acq_stretch_o (intr_i2c2_acq_stretch),
1346 .intr_unexp_stop_o (intr_i2c2_unexp_stop),
1347 .intr_host_timeout_o (intr_i2c2_host_timeout),
1348 // [8]: fatal_fault
1349 .alert_tx_o ( alert_tx[8:8] ),
1350 .alert_rx_i ( alert_rx[8:8] ),
1351
1352 // Inter-module signals
1353 .ram_cfg_i(ast_ram_1p_cfg),
1354 .tl_i(i2c2_tl_req),
1355 .tl_o(i2c2_tl_rsp),
1356
1357 // Clock and reset connections
1358 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1359 .rst_ni (rstmgr_aon_resets.rst_i2c2_n[rstmgr_pkg::Domain0Sel])
1360 );
1361 pattgen #(
1362 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[9:9])
1363 ) u_pattgen (
1364
1365 // Output
1366 .cio_pda0_tx_o (cio_pattgen_pda0_tx_d2p),
1367 .cio_pda0_tx_en_o (cio_pattgen_pda0_tx_en_d2p),
1368 .cio_pcl0_tx_o (cio_pattgen_pcl0_tx_d2p),
1369 .cio_pcl0_tx_en_o (cio_pattgen_pcl0_tx_en_d2p),
1370 .cio_pda1_tx_o (cio_pattgen_pda1_tx_d2p),
1371 .cio_pda1_tx_en_o (cio_pattgen_pda1_tx_en_d2p),
1372 .cio_pcl1_tx_o (cio_pattgen_pcl1_tx_d2p),
1373 .cio_pcl1_tx_en_o (cio_pattgen_pcl1_tx_en_d2p),
1374
1375 // Interrupt
1376 .intr_done_ch0_o (intr_pattgen_done_ch0),
1377 .intr_done_ch1_o (intr_pattgen_done_ch1),
1378 // [9]: fatal_fault
1379 .alert_tx_o ( alert_tx[9:9] ),
1380 .alert_rx_i ( alert_rx[9:9] ),
1381
1382 // Inter-module signals
1383 .tl_i(pattgen_tl_req),
1384 .tl_o(pattgen_tl_rsp),
1385
1386 // Clock and reset connections
1387 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1388 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
1389 );
1390 rv_timer #(
1391 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[10:10])
1392 ) u_rv_timer (
1393
1394 // Interrupt
1395 .intr_timer_expired_hart0_timer0_o (intr_rv_timer_timer_expired_hart0_timer0),
1396 // [10]: fatal_fault
1397 .alert_tx_o ( alert_tx[10:10] ),
1398 .alert_rx_i ( alert_rx[10:10] ),
1399
1400 // Inter-module signals
1401 .tl_i(rv_timer_tl_req),
1402 .tl_o(rv_timer_tl_rsp),
1403
1404 // Clock and reset connections
1405 .clk_i (clkmgr_aon_clocks.clk_io_div4_timers),
1406 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
1407 );
1408 otp_ctrl #(
1409 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[15:11]),
1410 .MemInitFile(OtpCtrlMemInitFile),
1411 .RndCnstLfsrSeed(RndCnstOtpCtrlLfsrSeed),
1412 .RndCnstLfsrPerm(RndCnstOtpCtrlLfsrPerm),
1413 .RndCnstScrmblKeyInit(RndCnstOtpCtrlScrmblKeyInit)
1414 ) u_otp_ctrl (
1415
1416 // Output
1417 .cio_test_o (cio_otp_ctrl_test_d2p),
1418 .cio_test_en_o (cio_otp_ctrl_test_en_d2p),
1419
1420 // Interrupt
1421 .intr_otp_operation_done_o (intr_otp_ctrl_otp_operation_done),
1422 .intr_otp_error_o (intr_otp_ctrl_otp_error),
1423 // [11]: fatal_macro_error
1424 // [12]: fatal_check_error
1425 // [13]: fatal_bus_integ_error
1426 // [14]: fatal_prim_otp_alert
1427 // [15]: recov_prim_otp_alert
1428 .alert_tx_o ( alert_tx[15:11] ),
1429 .alert_rx_i ( alert_rx[15:11] ),
1430
1431 // Inter-module signals
1432 .otp_ext_voltage_h_io(otp_ext_voltage_h_io),
1433 .otp_ast_pwr_seq_o(otp_ctrl_otp_ast_pwr_seq_o),
1434 .otp_ast_pwr_seq_h_i(otp_ctrl_otp_ast_pwr_seq_h_i),
1435 .edn_o(edn0_edn_req[1]),
1436 .edn_i(edn0_edn_rsp[1]),
1437 .pwr_otp_i(pwrmgr_aon_pwr_otp_req),
1438 .pwr_otp_o(pwrmgr_aon_pwr_otp_rsp),
1439 .lc_otp_vendor_test_i(lc_ctrl_lc_otp_vendor_test_req),
1440 .lc_otp_vendor_test_o(lc_ctrl_lc_otp_vendor_test_rsp),
1441 .lc_otp_program_i(lc_ctrl_lc_otp_program_req),
1442 .lc_otp_program_o(lc_ctrl_lc_otp_program_rsp),
1443 .otp_lc_data_o(otp_ctrl_otp_lc_data),
1444 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
1445 .lc_creator_seed_sw_rw_en_i(lc_ctrl_lc_creator_seed_sw_rw_en),
1446 .lc_owner_seed_sw_rw_en_i(lc_ctrl_pkg::Off),
1447 .lc_seed_hw_rd_en_i(lc_ctrl_lc_seed_hw_rd_en),
1448 .lc_dft_en_i(lc_ctrl_lc_dft_en),
1449 .lc_check_byp_en_i(lc_ctrl_lc_check_byp_en),
1450 .otp_keymgr_key_o(otp_ctrl_otp_keymgr_key),
1451 .flash_otp_key_i(flash_ctrl_otp_req),
1452 .flash_otp_key_o(flash_ctrl_otp_rsp),
1453 .sram_otp_key_i(otp_ctrl_sram_otp_key_req),
1454 .sram_otp_key_o(otp_ctrl_sram_otp_key_rsp),
1455 .otbn_otp_key_i(otp_ctrl_otbn_otp_key_req),
1456 .otbn_otp_key_o(otp_ctrl_otbn_otp_key_rsp),
1457 .otp_broadcast_o(otp_ctrl_otp_broadcast),
1458 .obs_ctrl_i(ast_obs_ctrl),
1459 .otp_obs_o(otp_obs_o),
1460 .core_tl_i(otp_ctrl_core_tl_req),
1461 .core_tl_o(otp_ctrl_core_tl_rsp),
1462 .prim_tl_i(otp_ctrl_prim_tl_req),
1463 .prim_tl_o(otp_ctrl_prim_tl_rsp),
1464 .scanmode_i,
1465 .scan_rst_ni,
1466 .scan_en_i,
1467
1468 // Clock and reset connections
1469 .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
1470 .clk_edn_i (clkmgr_aon_clocks.clk_main_secure),
1471 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
1472 .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
1473 );
1474 lc_ctrl #(
1475 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[18:16]),
1476 .SecVolatileRawUnlockEn(SecLcCtrlVolatileRawUnlockEn),
1477 .RndCnstLcKeymgrDivInvalid(RndCnstLcCtrlLcKeymgrDivInvalid),
1478 .RndCnstLcKeymgrDivTestUnlocked(RndCnstLcCtrlLcKeymgrDivTestUnlocked),
1479 .RndCnstLcKeymgrDivDev(RndCnstLcCtrlLcKeymgrDivDev),
1480 .RndCnstLcKeymgrDivProduction(RndCnstLcCtrlLcKeymgrDivProduction),
1481 .RndCnstLcKeymgrDivRma(RndCnstLcCtrlLcKeymgrDivRma),
1482 .RndCnstInvalidTokens(RndCnstLcCtrlInvalidTokens),
1483 .SiliconCreatorId(LcCtrlSiliconCreatorId),
1484 .ProductId(LcCtrlProductId),
1485 .RevisionId(LcCtrlRevisionId),
1486 .IdcodeValue(LcCtrlIdcodeValue)
1487 ) u_lc_ctrl (
1488 // [16]: fatal_prog_error
1489 // [17]: fatal_state_error
1490 // [18]: fatal_bus_integ_error
1491 .alert_tx_o ( alert_tx[18:16] ),
1492 .alert_rx_i ( alert_rx[18:16] ),
1493
1494 // Inter-module signals
1495 .jtag_i(pinmux_aon_lc_jtag_req),
1496 .jtag_o(pinmux_aon_lc_jtag_rsp),
1497 .esc_scrap_state0_tx_i(alert_handler_esc_tx[1]),
1498 .esc_scrap_state0_rx_o(alert_handler_esc_rx[1]),
1499 .esc_scrap_state1_tx_i(alert_handler_esc_tx[2]),
1500 .esc_scrap_state1_rx_o(alert_handler_esc_rx[2]),
1501 .pwr_lc_i(pwrmgr_aon_pwr_lc_req),
1502 .pwr_lc_o(pwrmgr_aon_pwr_lc_rsp),
1503 .lc_otp_vendor_test_o(lc_ctrl_lc_otp_vendor_test_req),
1504 .lc_otp_vendor_test_i(lc_ctrl_lc_otp_vendor_test_rsp),
1505 .otp_lc_data_i(otp_ctrl_otp_lc_data),
1506 .lc_otp_program_o(lc_ctrl_lc_otp_program_req),
1507 .lc_otp_program_i(lc_ctrl_lc_otp_program_rsp),
1508 .kmac_data_o(kmac_app_req[1]),
1509 .kmac_data_i(kmac_app_rsp[1]),
1510 .lc_dft_en_o(lc_ctrl_lc_dft_en),
1511 .lc_nvm_debug_en_o(lc_ctrl_lc_nvm_debug_en),
1512 .lc_hw_debug_en_o(lc_ctrl_lc_hw_debug_en),
1513 .lc_cpu_en_o(lc_ctrl_lc_cpu_en),
1514 .lc_keymgr_en_o(lc_ctrl_lc_keymgr_en),
1515 .lc_escalate_en_o(lc_ctrl_lc_escalate_en),
1516 .lc_clk_byp_req_o(lc_ctrl_lc_clk_byp_req),
1517 .lc_clk_byp_ack_i(lc_ctrl_lc_clk_byp_ack),
1518 .lc_flash_rma_req_o(lc_ctrl_lc_flash_rma_req),
1519 .lc_flash_rma_ack_i(lc_ctrl_lc_flash_rma_ack),
1520 .lc_flash_rma_seed_o(flash_ctrl_rma_seed),
1521 .lc_check_byp_en_o(lc_ctrl_lc_check_byp_en),
1522 .lc_creator_seed_sw_rw_en_o(lc_ctrl_lc_creator_seed_sw_rw_en),
1523 .lc_owner_seed_sw_rw_en_o(lc_ctrl_lc_owner_seed_sw_rw_en),
1524 .lc_iso_part_sw_rd_en_o(lc_ctrl_lc_iso_part_sw_rd_en),
1525 .lc_iso_part_sw_wr_en_o(lc_ctrl_lc_iso_part_sw_wr_en),
1526 .lc_seed_hw_rd_en_o(lc_ctrl_lc_seed_hw_rd_en),
1527 .lc_keymgr_div_o(lc_ctrl_lc_keymgr_div),
1528 .otp_device_id_i(lc_ctrl_otp_device_id),
1529 .otp_manuf_state_i(lc_ctrl_otp_manuf_state),
1530 .hw_rev_o(),
1531 .strap_en_override_o(lc_ctrl_strap_en_override),
1532 .tl_i(lc_ctrl_tl_req),
1533 .tl_o(lc_ctrl_tl_rsp),
1534 .scanmode_i,
1535 .scan_rst_ni,
1536
1537 // Clock and reset connections
1538 .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
1539 .clk_kmac_i (clkmgr_aon_clocks.clk_main_secure),
1540 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
1541 .rst_kmac_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
1542 );
1543 alert_handler #(
1544 .RndCnstLfsrSeed(RndCnstAlertHandlerLfsrSeed),
1545 .RndCnstLfsrPerm(RndCnstAlertHandlerLfsrPerm)
1546 ) u_alert_handler (
1547
1548 // Interrupt
1549 .intr_classa_o (intr_alert_handler_classa),
1550 .intr_classb_o (intr_alert_handler_classb),
1551 .intr_classc_o (intr_alert_handler_classc),
1552 .intr_classd_o (intr_alert_handler_classd),
1553
1554 // Inter-module signals
1555 .crashdump_o(alert_handler_crashdump),
1556 .edn_o(edn0_edn_req[4]),
1557 .edn_i(edn0_edn_rsp[4]),
1558 .esc_rx_i(alert_handler_esc_rx),
1559 .esc_tx_o(alert_handler_esc_tx),
1560 .tl_i(alert_handler_tl_req),
1561 .tl_o(alert_handler_tl_rsp),
1562 // alert signals
1563 .alert_rx_o ( alert_rx ),
1564 .alert_tx_i ( alert_tx ),
1565 // synchronized clock gated / reset asserted
1566 // indications for each alert
1567 .lpg_cg_en_i ( lpg_cg_en ),
1568 .lpg_rst_en_i ( lpg_rst_en ),
1569
1570 // Clock and reset connections
1571 .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
1572 .clk_edn_i (clkmgr_aon_clocks.clk_main_secure),
1573 .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_io_div4_shadowed_n[rstmgr_pkg::Domain0Sel]),
1574 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
1575 .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
1576 );
1577 spi_host #(
1578 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[19:19])
1579 ) u_spi_host0 (
1580
1581 // Input
1582 .cio_sd_i (cio_spi_host0_sd_p2d),
1583
1584 // Output
1585 .cio_sck_o (cio_spi_host0_sck_d2p),
1586 .cio_sck_en_o (cio_spi_host0_sck_en_d2p),
1587 .cio_csb_o (cio_spi_host0_csb_d2p),
1588 .cio_csb_en_o (cio_spi_host0_csb_en_d2p),
1589 .cio_sd_o (cio_spi_host0_sd_d2p),
1590 .cio_sd_en_o (cio_spi_host0_sd_en_d2p),
1591
1592 // Interrupt
1593 .intr_error_o (intr_spi_host0_error),
1594 .intr_spi_event_o (intr_spi_host0_spi_event),
1595 // [19]: fatal_fault
1596 .alert_tx_o ( alert_tx[19:19] ),
1597 .alert_rx_i ( alert_rx[19:19] ),
1598
1599 // Inter-module signals
1600 .passthrough_i(spi_device_passthrough_req),
1601 .passthrough_o(spi_device_passthrough_rsp),
1602 .tl_i(spi_host0_tl_req),
1603 .tl_o(spi_host0_tl_rsp),
1604
1605 // Clock and reset connections
1606 .clk_i (clkmgr_aon_clocks.clk_io_peri),
1607 .rst_ni (rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel])
1608 );
1609 spi_host #(
1610 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[20:20])
1611 ) u_spi_host1 (
1612
1613 // Input
1614 .cio_sd_i (cio_spi_host1_sd_p2d),
1615
1616 // Output
1617 .cio_sck_o (cio_spi_host1_sck_d2p),
1618 .cio_sck_en_o (cio_spi_host1_sck_en_d2p),
1619 .cio_csb_o (cio_spi_host1_csb_d2p),
1620 .cio_csb_en_o (cio_spi_host1_csb_en_d2p),
1621 .cio_sd_o (cio_spi_host1_sd_d2p),
1622 .cio_sd_en_o (cio_spi_host1_sd_en_d2p),
1623
1624 // Interrupt
1625 .intr_error_o (intr_spi_host1_error),
1626 .intr_spi_event_o (intr_spi_host1_spi_event),
1627 // [20]: fatal_fault
1628 .alert_tx_o ( alert_tx[20:20] ),
1629 .alert_rx_i ( alert_rx[20:20] ),
1630
1631 // Inter-module signals
1632 .passthrough_i(spi_device_pkg::PASSTHROUGH_REQ_DEFAULT),
1633 .passthrough_o(),
1634 .tl_i(spi_host1_tl_req),
1635 .tl_o(spi_host1_tl_rsp),
1636
1637 // Clock and reset connections
1638 .clk_i (clkmgr_aon_clocks.clk_io_div2_peri),
1639 .rst_ni (rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel])
1640 );
1641 usbdev #(
1642 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[21:21]),
1643 .Stub(UsbdevStub),
1644 .RcvrWakeTimeUs(UsbdevRcvrWakeTimeUs)
1645 ) u_usbdev (
1646
1647 // Input
1648 .cio_sense_i (cio_usbdev_sense_p2d),
1649 .cio_usb_dp_i (cio_usbdev_usb_dp_p2d),
1650 .cio_usb_dn_i (cio_usbdev_usb_dn_p2d),
1651
1652 // Output
1653 .cio_usb_dp_o (cio_usbdev_usb_dp_d2p),
1654 .cio_usb_dp_en_o (cio_usbdev_usb_dp_en_d2p),
1655 .cio_usb_dn_o (cio_usbdev_usb_dn_d2p),
1656 .cio_usb_dn_en_o (cio_usbdev_usb_dn_en_d2p),
1657
1658 // Interrupt
1659 .intr_pkt_received_o (intr_usbdev_pkt_received),
1660 .intr_pkt_sent_o (intr_usbdev_pkt_sent),
1661 .intr_disconnected_o (intr_usbdev_disconnected),
1662 .intr_host_lost_o (intr_usbdev_host_lost),
1663 .intr_link_reset_o (intr_usbdev_link_reset),
1664 .intr_link_suspend_o (intr_usbdev_link_suspend),
1665 .intr_link_resume_o (intr_usbdev_link_resume),
1666 .intr_av_out_empty_o (intr_usbdev_av_out_empty),
1667 .intr_rx_full_o (intr_usbdev_rx_full),
1668 .intr_av_overflow_o (intr_usbdev_av_overflow),
1669 .intr_link_in_err_o (intr_usbdev_link_in_err),
1670 .intr_rx_crc_err_o (intr_usbdev_rx_crc_err),
1671 .intr_rx_pid_err_o (intr_usbdev_rx_pid_err),
1672 .intr_rx_bitstuff_err_o (intr_usbdev_rx_bitstuff_err),
1673 .intr_frame_o (intr_usbdev_frame),
1674 .intr_powered_o (intr_usbdev_powered),
1675 .intr_link_out_err_o (intr_usbdev_link_out_err),
1676 .intr_av_setup_empty_o (intr_usbdev_av_setup_empty),
1677 // [21]: fatal_fault
1678 .alert_tx_o ( alert_tx[21:21] ),
1679 .alert_rx_i ( alert_rx[21:21] ),
1680
1681 // Inter-module signals
1682 .usb_rx_d_i(usbdev_usb_rx_d_i),
1683 .usb_tx_d_o(usbdev_usb_tx_d_o),
1684 .usb_tx_se0_o(usbdev_usb_tx_se0_o),
1685 .usb_tx_use_d_se0_o(usbdev_usb_tx_use_d_se0_o),
1686 .usb_dp_pullup_o(usbdev_usb_dp_pullup),
1687 .usb_dn_pullup_o(usbdev_usb_dn_pullup),
1688 .usb_rx_enable_o(usbdev_usb_rx_enable_o),
1689 .usb_ref_val_o(usbdev_usb_ref_val_o),
1690 .usb_ref_pulse_o(usbdev_usb_ref_pulse_o),
1691 .usb_aon_suspend_req_o(usbdev_usb_aon_suspend_req),
1692 .usb_aon_wake_ack_o(usbdev_usb_aon_wake_ack),
1693 .usb_aon_bus_reset_i(usbdev_usb_aon_bus_reset),
1694 .usb_aon_sense_lost_i(usbdev_usb_aon_sense_lost),
1695 .usb_aon_bus_not_idle_i(usbdev_usb_aon_bus_not_idle),
1696 .usb_aon_wake_detect_active_i(pinmux_aon_usbdev_wake_detect_active),
1697 .ram_cfg_i(ast_usb_ram_1p_cfg),
1698 .tl_i(usbdev_tl_req),
1699 .tl_o(usbdev_tl_rsp),
1700
1701 // Clock and reset connections
1702 .clk_i (clkmgr_aon_clocks.clk_usb_peri),
1703 .clk_aon_i (clkmgr_aon_clocks.clk_aon_peri),
1704 .rst_ni (rstmgr_aon_resets.rst_usb_n[rstmgr_pkg::Domain0Sel]),
1705 .rst_aon_ni (rstmgr_aon_resets.rst_usb_aon_n[rstmgr_pkg::Domain0Sel])
1706 );
1707 pwrmgr #(
1708 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[22:22])
1709 ) u_pwrmgr_aon (
1710
1711 // Interrupt
1712 .intr_wakeup_o (intr_pwrmgr_aon_wakeup),
1713 // [22]: fatal_fault
1714 .alert_tx_o ( alert_tx[22:22] ),
1715 .alert_rx_i ( alert_rx[22:22] ),
1716
1717 // Inter-module signals
1718 .pwr_ast_o(pwrmgr_ast_req_o),
1719 .pwr_ast_i(pwrmgr_ast_rsp_i),
1720 .pwr_rst_o(pwrmgr_aon_pwr_rst_req),
1721 .pwr_rst_i(pwrmgr_aon_pwr_rst_rsp),
1722 .pwr_clk_o(pwrmgr_aon_pwr_clk_req),
1723 .pwr_clk_i(pwrmgr_aon_pwr_clk_rsp),
1724 .pwr_otp_o(pwrmgr_aon_pwr_otp_req),
1725 .pwr_otp_i(pwrmgr_aon_pwr_otp_rsp),
1726 .pwr_lc_o(pwrmgr_aon_pwr_lc_req),
1727 .pwr_lc_i(pwrmgr_aon_pwr_lc_rsp),
1728 .pwr_flash_i(pwrmgr_aon_pwr_flash),
1729 .esc_rst_tx_i(alert_handler_esc_tx[3]),
1730 .esc_rst_rx_o(alert_handler_esc_rx[3]),
1731 .pwr_cpu_i(rv_core_ibex_pwrmgr),
1732 .wakeups_i(pwrmgr_aon_wakeups),
1733 .rstreqs_i(pwrmgr_aon_rstreqs),
1734 .ndmreset_req_i(rv_dm_ndmreset_req),
1735 .strap_o(pwrmgr_aon_strap),
1736 .low_power_o(pwrmgr_aon_low_power),
1737 .rom_ctrl_i(rom_ctrl_pwrmgr_data),
1738 .fetch_en_o(pwrmgr_aon_fetch_en),
1739 .lc_dft_en_i(lc_ctrl_lc_dft_en),
1740 .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
1741 .sw_rst_req_i(rstmgr_aon_sw_rst_req),
1742 .tl_i(pwrmgr_aon_tl_req),
1743 .tl_o(pwrmgr_aon_tl_rsp),
1744
1745 // Clock and reset connections
1746 .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup),
1747 .clk_slow_i (clkmgr_aon_clocks.clk_aon_powerup),
1748 .clk_lc_i (clkmgr_aon_clocks.clk_io_div4_powerup),
1749 .clk_esc_i (clkmgr_aon_clocks.clk_io_div4_secure),
1750 .rst_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]),
1751 .rst_main_ni (rstmgr_aon_resets.rst_por_aon_n[rstmgr_pkg::Domain0Sel]),
1752 .rst_lc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
1753 .rst_esc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
1754 .rst_slow_ni (rstmgr_aon_resets.rst_por_aon_n[rstmgr_pkg::DomainAonSel])
1755 );
1756 rstmgr #(
1757 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[24:23]),
1758 .SecCheck(SecRstmgrAonCheck),
1759 .SecMaxSyncDelay(SecRstmgrAonMaxSyncDelay)
1760 ) u_rstmgr_aon (
1761 // [23]: fatal_fault
1762 // [24]: fatal_cnsty_fault
1763 .alert_tx_o ( alert_tx[24:23] ),
1764 .alert_rx_i ( alert_rx[24:23] ),
1765
1766 // Inter-module signals
1767 .por_n_i(por_n_i),
1768 .pwr_i(pwrmgr_aon_pwr_rst_req),
1769 .pwr_o(pwrmgr_aon_pwr_rst_rsp),
1770 .resets_o(rstmgr_aon_resets),
1771 .rst_en_o(rstmgr_aon_rst_en),
1772 .alert_dump_i(alert_handler_crashdump),
1773 .cpu_dump_i(rv_core_ibex_crash_dump),
1774 .sw_rst_req_o(rstmgr_aon_sw_rst_req),
1775 .tl_i(rstmgr_aon_tl_req),
1776 .tl_o(rstmgr_aon_tl_rsp),
1777 .scanmode_i,
1778 .scan_rst_ni,
1779
1780 // Clock and reset connections
1781 .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup),
1782 .clk_por_i (clkmgr_aon_clocks.clk_io_div4_powerup),
1783 .clk_aon_i (clkmgr_aon_clocks.clk_aon_powerup),
1784 .clk_main_i (clkmgr_aon_clocks.clk_main_powerup),
1785 .clk_io_i (clkmgr_aon_clocks.clk_io_powerup),
1786 .clk_usb_i (clkmgr_aon_clocks.clk_usb_powerup),
1787 .clk_io_div2_i (clkmgr_aon_clocks.clk_io_div2_powerup),
1788 .clk_io_div4_i (clkmgr_aon_clocks.clk_io_div4_powerup),
1789 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
1790 .rst_por_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel])
1791 );
1792 clkmgr #(
1793 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[26:25])
1794 ) u_clkmgr_aon (
1795 // [25]: recov_fault
1796 // [26]: fatal_fault
1797 .alert_tx_o ( alert_tx[26:25] ),
1798 .alert_rx_i ( alert_rx[26:25] ),
1799
1800 // Inter-module signals
1801 .clocks_o(clkmgr_aon_clocks),
1802 .cg_en_o(clkmgr_aon_cg_en),
1803 .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
1804 .io_clk_byp_req_o(io_clk_byp_req_o),
1805 .io_clk_byp_ack_i(io_clk_byp_ack_i),
1806 .all_clk_byp_req_o(all_clk_byp_req_o),
1807 .all_clk_byp_ack_i(all_clk_byp_ack_i),
1808 .hi_speed_sel_o(hi_speed_sel_o),
1809 .div_step_down_req_i(div_step_down_req_i),
1810 .lc_clk_byp_req_i(lc_ctrl_lc_clk_byp_req),
1811 .lc_clk_byp_ack_o(lc_ctrl_lc_clk_byp_ack),
1812 .jitter_en_o(clk_main_jitter_en_o),
1813 .pwr_i(pwrmgr_aon_pwr_clk_req),
1814 .pwr_o(pwrmgr_aon_pwr_clk_rsp),
1815 .idle_i(clkmgr_aon_idle),
1816 .calib_rdy_i(calib_rdy_i),
1817 .tl_i(clkmgr_aon_tl_req),
1818 .tl_o(clkmgr_aon_tl_rsp),
1819 .scanmode_i,
1820
1821 // Clock and reset connections
1822 .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup),
1823 .clk_main_i (clk_main_i),
1824 .clk_io_i (clk_io_i),
1825 .clk_usb_i (clk_usb_i),
1826 .clk_aon_i (clk_aon_i),
1827 .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_io_div4_shadowed_n[rstmgr_pkg::DomainAonSel]),
1828 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
1829 .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]),
1830 .rst_io_ni (rstmgr_aon_resets.rst_lc_io_n[rstmgr_pkg::DomainAonSel]),
1831 .rst_io_div2_ni (rstmgr_aon_resets.rst_lc_io_div2_n[rstmgr_pkg::DomainAonSel]),
1832 .rst_io_div4_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
1833 .rst_main_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::DomainAonSel]),
1834 .rst_usb_ni (rstmgr_aon_resets.rst_lc_usb_n[rstmgr_pkg::DomainAonSel]),
1835 .rst_root_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]),
1836 .rst_root_io_ni (rstmgr_aon_resets.rst_por_io_n[rstmgr_pkg::DomainAonSel]),
1837 .rst_root_io_div2_ni (rstmgr_aon_resets.rst_por_io_div2_n[rstmgr_pkg::DomainAonSel]),
1838 .rst_root_io_div4_ni (rstmgr_aon_resets.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel]),
1839 .rst_root_main_ni (rstmgr_aon_resets.rst_por_n[rstmgr_pkg::DomainAonSel]),
1840 .rst_root_usb_ni (rstmgr_aon_resets.rst_por_usb_n[rstmgr_pkg::DomainAonSel])
1841 );
1842 sysrst_ctrl #(
1843 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[27:27])
1844 ) u_sysrst_ctrl_aon (
1845
1846 // Input
1847 .cio_ac_present_i (cio_sysrst_ctrl_aon_ac_present_p2d),
1848 .cio_key0_in_i (cio_sysrst_ctrl_aon_key0_in_p2d),
1849 .cio_key1_in_i (cio_sysrst_ctrl_aon_key1_in_p2d),
1850 .cio_key2_in_i (cio_sysrst_ctrl_aon_key2_in_p2d),
1851 .cio_pwrb_in_i (cio_sysrst_ctrl_aon_pwrb_in_p2d),
1852 .cio_lid_open_i (cio_sysrst_ctrl_aon_lid_open_p2d),
1853 .cio_ec_rst_l_i (cio_sysrst_ctrl_aon_ec_rst_l_p2d),
1854 .cio_flash_wp_l_i (cio_sysrst_ctrl_aon_flash_wp_l_p2d),
1855
1856 // Output
1857 .cio_bat_disable_o (cio_sysrst_ctrl_aon_bat_disable_d2p),
1858 .cio_bat_disable_en_o (cio_sysrst_ctrl_aon_bat_disable_en_d2p),
1859 .cio_key0_out_o (cio_sysrst_ctrl_aon_key0_out_d2p),
1860 .cio_key0_out_en_o (cio_sysrst_ctrl_aon_key0_out_en_d2p),
1861 .cio_key1_out_o (cio_sysrst_ctrl_aon_key1_out_d2p),
1862 .cio_key1_out_en_o (cio_sysrst_ctrl_aon_key1_out_en_d2p),
1863 .cio_key2_out_o (cio_sysrst_ctrl_aon_key2_out_d2p),
1864 .cio_key2_out_en_o (cio_sysrst_ctrl_aon_key2_out_en_d2p),
1865 .cio_pwrb_out_o (cio_sysrst_ctrl_aon_pwrb_out_d2p),
1866 .cio_pwrb_out_en_o (cio_sysrst_ctrl_aon_pwrb_out_en_d2p),
1867 .cio_z3_wakeup_o (cio_sysrst_ctrl_aon_z3_wakeup_d2p),
1868 .cio_z3_wakeup_en_o (cio_sysrst_ctrl_aon_z3_wakeup_en_d2p),
1869 .cio_ec_rst_l_o (cio_sysrst_ctrl_aon_ec_rst_l_d2p),
1870 .cio_ec_rst_l_en_o (cio_sysrst_ctrl_aon_ec_rst_l_en_d2p),
1871 .cio_flash_wp_l_o (cio_sysrst_ctrl_aon_flash_wp_l_d2p),
1872 .cio_flash_wp_l_en_o (cio_sysrst_ctrl_aon_flash_wp_l_en_d2p),
1873
1874 // Interrupt
1875 .intr_event_detected_o (intr_sysrst_ctrl_aon_event_detected),
1876 // [27]: fatal_fault
1877 .alert_tx_o ( alert_tx[27:27] ),
1878 .alert_rx_i ( alert_rx[27:27] ),
1879
1880 // Inter-module signals
1881 .wkup_req_o(pwrmgr_aon_wakeups[0]),
1882 .rst_req_o(pwrmgr_aon_rstreqs[0]),
1883 .tl_i(sysrst_ctrl_aon_tl_req),
1884 .tl_o(sysrst_ctrl_aon_tl_rsp),
1885
1886 // Clock and reset connections
1887 .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
1888 .clk_aon_i (clkmgr_aon_clocks.clk_aon_secure),
1889 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
1890 .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel])
1891 );
1892 adc_ctrl #(
1893 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[28:28])
1894 ) u_adc_ctrl_aon (
1895
1896 // Interrupt
1897 .intr_match_pending_o (intr_adc_ctrl_aon_match_pending),
1898 // [28]: fatal_fault
1899 .alert_tx_o ( alert_tx[28:28] ),
1900 .alert_rx_i ( alert_rx[28:28] ),
1901
1902 // Inter-module signals
1903 .adc_o(adc_req_o),
1904 .adc_i(adc_rsp_i),
1905 .wkup_req_o(pwrmgr_aon_wakeups[1]),
1906 .tl_i(adc_ctrl_aon_tl_req),
1907 .tl_o(adc_ctrl_aon_tl_rsp),
1908
1909 // Clock and reset connections
1910 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1911 .clk_aon_i (clkmgr_aon_clocks.clk_aon_peri),
1912 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
1913 .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel])
1914 );
1915 pwm #(
1916 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[29:29])
1917 ) u_pwm_aon (
1918
1919 // Output
1920 .cio_pwm_o (cio_pwm_aon_pwm_d2p),
1921 .cio_pwm_en_o (cio_pwm_aon_pwm_en_d2p),
1922 // [29]: fatal_fault
1923 .alert_tx_o ( alert_tx[29:29] ),
1924 .alert_rx_i ( alert_rx[29:29] ),
1925
1926 // Inter-module signals
1927 .tl_i(pwm_aon_tl_req),
1928 .tl_o(pwm_aon_tl_rsp),
1929
1930 // Clock and reset connections
1931 .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
1932 .clk_core_i (clkmgr_aon_clocks.clk_aon_peri),
1933 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
1934 .rst_core_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel])
1935 );
1936 pinmux #(
1937 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[30:30]),
1938 .SecVolatileRawUnlockEn(SecPinmuxAonVolatileRawUnlockEn),
1939 .TargetCfg(PinmuxAonTargetCfg)
1940 ) u_pinmux_aon (
1941 // [30]: fatal_fault
1942 .alert_tx_o ( alert_tx[30:30] ),
1943 .alert_rx_i ( alert_rx[30:30] ),
1944
1945 // Inter-module signals
1946 .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
1947 .lc_dft_en_i(lc_ctrl_lc_dft_en),
1948 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
1949 .lc_check_byp_en_i(lc_ctrl_lc_check_byp_en),
1950 .pinmux_hw_debug_en_o(pinmux_aon_pinmux_hw_debug_en),
1951 .lc_jtag_o(pinmux_aon_lc_jtag_req),
1952 .lc_jtag_i(pinmux_aon_lc_jtag_rsp),
1953 .rv_jtag_o(pinmux_aon_rv_jtag_req),
1954 .rv_jtag_i(pinmux_aon_rv_jtag_rsp),
1955 .dft_jtag_o(pinmux_aon_dft_jtag_req),
1956 .dft_jtag_i(pinmux_aon_dft_jtag_rsp),
1957 .dft_strap_test_o(dft_strap_test_o),
1958 .dft_hold_tap_sel_i(dft_hold_tap_sel_i),
1959 .sleep_en_i(pwrmgr_aon_low_power),
1960 .strap_en_i(pwrmgr_aon_strap),
1961 .strap_en_override_i(lc_ctrl_strap_en_override),
1962 .pin_wkup_req_o(pwrmgr_aon_wakeups[2]),
1963 .usbdev_dppullup_en_i(usbdev_usb_dp_pullup),
1964 .usbdev_dnpullup_en_i(usbdev_usb_dn_pullup),
1965 .usb_dppullup_en_o(usb_dp_pullup_en_o),
1966 .usb_dnpullup_en_o(usb_dn_pullup_en_o),
1967 .usb_wkup_req_o(pwrmgr_aon_wakeups[3]),
1968 .usbdev_suspend_req_i(usbdev_usb_aon_suspend_req),
1969 .usbdev_wake_ack_i(usbdev_usb_aon_wake_ack),
1970 .usbdev_bus_not_idle_o(usbdev_usb_aon_bus_not_idle),
1971 .usbdev_bus_reset_o(usbdev_usb_aon_bus_reset),
1972 .usbdev_sense_lost_o(usbdev_usb_aon_sense_lost),
1973 .usbdev_wake_detect_active_o(pinmux_aon_usbdev_wake_detect_active),
1974 .tl_i(pinmux_aon_tl_req),
1975 .tl_o(pinmux_aon_tl_rsp),
1976
1977 .periph_to_mio_i (mio_d2p ),
1978 .periph_to_mio_oe_i (mio_en_d2p ),
1979 .mio_to_periph_o (mio_p2d ),
1980
1981 .mio_attr_o,
1982 .mio_out_o,
1983 .mio_oe_o,
1984 .mio_in_i,
1985
1986 .periph_to_dio_i (dio_d2p ),
1987 .periph_to_dio_oe_i (dio_en_d2p ),
1988 .dio_to_periph_o (dio_p2d ),
1989
1990 .dio_attr_o,
1991 .dio_out_o,
1992 .dio_oe_o,
1993 .dio_in_i,
1994
1995 .scanmode_i,
1996
1997 // Clock and reset connections
1998 .clk_i (clkmgr_aon_clocks.clk_io_div4_powerup),
1999 .clk_aon_i (clkmgr_aon_clocks.clk_aon_powerup),
2000 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
2001 .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]),
2002 .rst_sys_ni (rstmgr_aon_resets.rst_sys_io_div4_n[rstmgr_pkg::DomainAonSel])
2003 );
2004 aon_timer #(
2005 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[31:31])
2006 ) u_aon_timer_aon (
2007
2008 // Interrupt
2009 .intr_wkup_timer_expired_o (intr_aon_timer_aon_wkup_timer_expired),
2010 .intr_wdog_timer_bark_o (intr_aon_timer_aon_wdog_timer_bark),
2011 // [31]: fatal_fault
2012 .alert_tx_o ( alert_tx[31:31] ),
2013 .alert_rx_i ( alert_rx[31:31] ),
2014
2015 // Inter-module signals
2016 .nmi_wdog_timer_bark_o(aon_timer_aon_nmi_wdog_timer_bark),
2017 .wkup_req_o(pwrmgr_aon_wakeups[4]),
2018 .aon_timer_rst_req_o(pwrmgr_aon_rstreqs[1]),
2019 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
2020 .sleep_mode_i(pwrmgr_aon_low_power),
2021 .tl_i(aon_timer_aon_tl_req),
2022 .tl_o(aon_timer_aon_tl_rsp),
2023
2024 // Clock and reset connections
2025 .clk_i (clkmgr_aon_clocks.clk_io_div4_timers),
2026 .clk_aon_i (clkmgr_aon_clocks.clk_aon_timers),
2027 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
2028 .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel])
2029 );
2030 sensor_ctrl #(
2031 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[33:32])
2032 ) u_sensor_ctrl_aon (
2033
2034 // Output
2035 .cio_ast_debug_out_o (cio_sensor_ctrl_aon_ast_debug_out_d2p),
2036 .cio_ast_debug_out_en_o (cio_sensor_ctrl_aon_ast_debug_out_en_d2p),
2037
2038 // Interrupt
2039 .intr_io_status_change_o (intr_sensor_ctrl_aon_io_status_change),
2040 .intr_init_status_change_o (intr_sensor_ctrl_aon_init_status_change),
2041 // [32]: recov_alert
2042 // [33]: fatal_alert
2043 .alert_tx_o ( alert_tx[33:32] ),
2044 .alert_rx_i ( alert_rx[33:32] ),
2045
2046 // Inter-module signals
2047 .ast_alert_i(sensor_ctrl_ast_alert_req_i),
2048 .ast_alert_o(sensor_ctrl_ast_alert_rsp_o),
2049 .ast_status_i(sensor_ctrl_ast_status_i),
2050 .ast_init_done_i(ast_init_done_i),
2051 .ast2pinmux_i(ast2pinmux_i),
2052 .wkup_req_o(pwrmgr_aon_wakeups[5]),
2053 .manual_pad_attr_o(sensor_ctrl_manual_pad_attr_o),
2054 .tl_i(sensor_ctrl_aon_tl_req),
2055 .tl_o(sensor_ctrl_aon_tl_rsp),
2056
2057 // Clock and reset connections
2058 .clk_i (clkmgr_aon_clocks.clk_io_div4_secure),
2059 .clk_aon_i (clkmgr_aon_clocks.clk_aon_secure),
2060 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
2061 .rst_aon_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel])
2062 );
2063 sram_ctrl #(
2064 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[34:34]),
2065 .RndCnstSramKey(RndCnstSramCtrlRetAonSramKey),
2066 .RndCnstSramNonce(RndCnstSramCtrlRetAonSramNonce),
2067 .RndCnstLfsrSeed(RndCnstSramCtrlRetAonLfsrSeed),
2068 .RndCnstLfsrPerm(RndCnstSramCtrlRetAonLfsrPerm),
2069 .MemSizeRam(4096),
2070 .InstrExec(SramCtrlRetAonInstrExec)
2071 ) u_sram_ctrl_ret_aon (
2072 // [34]: fatal_error
2073 .alert_tx_o ( alert_tx[34:34] ),
2074 .alert_rx_i ( alert_rx[34:34] ),
2075
2076 // Inter-module signals
2077 .sram_otp_key_o(otp_ctrl_sram_otp_key_req[1]),
2078 .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[1]),
2079 .cfg_i(ast_ram_1p_cfg),
2080 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
2081 .lc_hw_debug_en_i(lc_ctrl_pkg::Off),
2082 .otp_en_sram_ifetch_i(prim_mubi_pkg::MuBi8False),
2083 .regs_tl_i(sram_ctrl_ret_aon_regs_tl_req),
2084 .regs_tl_o(sram_ctrl_ret_aon_regs_tl_rsp),
2085 .ram_tl_i(sram_ctrl_ret_aon_ram_tl_req),
2086 .ram_tl_o(sram_ctrl_ret_aon_ram_tl_rsp),
2087
2088 // Clock and reset connections
2089 .clk_i (clkmgr_aon_clocks.clk_io_div4_infra),
2090 .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra),
2091 .rst_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel]),
2092 .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel])
2093 );
2094 flash_ctrl #(
2095 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[39:35]),
2096 .RndCnstAddrKey(RndCnstFlashCtrlAddrKey),
2097 .RndCnstDataKey(RndCnstFlashCtrlDataKey),
2098 .RndCnstAllSeeds(RndCnstFlashCtrlAllSeeds),
2099 .RndCnstLfsrSeed(RndCnstFlashCtrlLfsrSeed),
2100 .RndCnstLfsrPerm(RndCnstFlashCtrlLfsrPerm),
2101 .SecScrambleEn(SecFlashCtrlScrambleEn),
2102 .ProgFifoDepth(FlashCtrlProgFifoDepth),
2103 .RdFifoDepth(FlashCtrlRdFifoDepth)
2104 ) u_flash_ctrl (
2105
2106 // Input
2107 .cio_tck_i (cio_flash_ctrl_tck_p2d),
2108 .cio_tms_i (cio_flash_ctrl_tms_p2d),
2109 .cio_tdi_i (cio_flash_ctrl_tdi_p2d),
2110
2111 // Output
2112 .cio_tdo_o (cio_flash_ctrl_tdo_d2p),
2113 .cio_tdo_en_o (cio_flash_ctrl_tdo_en_d2p),
2114
2115 // Interrupt
2116 .intr_prog_empty_o (intr_flash_ctrl_prog_empty),
2117 .intr_prog_lvl_o (intr_flash_ctrl_prog_lvl),
2118 .intr_rd_full_o (intr_flash_ctrl_rd_full),
2119 .intr_rd_lvl_o (intr_flash_ctrl_rd_lvl),
2120 .intr_op_done_o (intr_flash_ctrl_op_done),
2121 .intr_corr_err_o (intr_flash_ctrl_corr_err),
2122 // [35]: recov_err
2123 // [36]: fatal_std_err
2124 // [37]: fatal_err
2125 // [38]: fatal_prim_flash_alert
2126 // [39]: recov_prim_flash_alert
2127 .alert_tx_o ( alert_tx[39:35] ),
2128 .alert_rx_i ( alert_rx[39:35] ),
2129
2130 // Inter-module signals
2131 .otp_o(flash_ctrl_otp_req),
2132 .otp_i(flash_ctrl_otp_rsp),
2133 .lc_nvm_debug_en_i(lc_ctrl_lc_nvm_debug_en),
2134 .flash_bist_enable_i(flash_bist_enable_i),
2135 .flash_power_down_h_i(flash_power_down_h_i),
2136 .flash_power_ready_h_i(flash_power_ready_h_i),
2137 .flash_test_mode_a_io(flash_test_mode_a_io),
2138 .flash_test_voltage_h_io(flash_test_voltage_h_io),
2139 .lc_creator_seed_sw_rw_en_i(lc_ctrl_lc_creator_seed_sw_rw_en),
2140 .lc_owner_seed_sw_rw_en_i(lc_ctrl_lc_owner_seed_sw_rw_en),
2141 .lc_iso_part_sw_rd_en_i(lc_ctrl_lc_iso_part_sw_rd_en),
2142 .lc_iso_part_sw_wr_en_i(lc_ctrl_lc_iso_part_sw_wr_en),
2143 .lc_seed_hw_rd_en_i(lc_ctrl_lc_seed_hw_rd_en),
2144 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
2145 .rma_req_i(lc_ctrl_lc_flash_rma_req),
2146 .rma_ack_o(lc_ctrl_lc_flash_rma_ack[0]),
2147 .rma_seed_i(flash_ctrl_rma_seed),
2148 .pwrmgr_o(pwrmgr_aon_pwr_flash),
2149 .keymgr_o(flash_ctrl_keymgr),
2150 .obs_ctrl_i(ast_obs_ctrl),
2151 .fla_obs_o(flash_obs_o),
2152 .core_tl_i(flash_ctrl_core_tl_req),
2153 .core_tl_o(flash_ctrl_core_tl_rsp),
2154 .prim_tl_i(flash_ctrl_prim_tl_req),
2155 .prim_tl_o(flash_ctrl_prim_tl_rsp),
2156 .mem_tl_i(flash_ctrl_mem_tl_req),
2157 .mem_tl_o(flash_ctrl_mem_tl_rsp),
2158 .scanmode_i,
2159 .scan_rst_ni,
2160 .scan_en_i,
2161
2162 // Clock and reset connections
2163 .clk_i (clkmgr_aon_clocks.clk_main_infra),
2164 .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra),
2165 .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]),
2166 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2167 .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
2168 );
2169 rv_dm #(
2170 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:40]),
2171 .IdcodeValue(RvDmIdcodeValue)
2172 ) u_rv_dm (
2173 // [40]: fatal_fault
2174 .alert_tx_o ( alert_tx[40:40] ),
2175 .alert_rx_i ( alert_rx[40:40] ),
2176
2177 // Inter-module signals
2178 .next_dm_addr_i('0),
2179 .jtag_i(pinmux_aon_rv_jtag_req),
2180 .jtag_o(pinmux_aon_rv_jtag_rsp),
2181 .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
2182 .lc_dft_en_i(lc_ctrl_lc_dft_en),
2183 .pinmux_hw_debug_en_i(pinmux_aon_pinmux_hw_debug_en),
2184 .otp_dis_rv_dm_late_debug_i(rv_dm_otp_dis_rv_dm_late_debug),
2185 .unavailable_i(1'b0),
2186 .ndmreset_req_o(rv_dm_ndmreset_req),
2187 .dmactive_o(),
2188 .debug_req_o(rv_dm_debug_req),
2189 .sba_tl_h_o(main_tl_rv_dm__sba_req),
2190 .sba_tl_h_i(main_tl_rv_dm__sba_rsp),
2191 .regs_tl_d_i(rv_dm_regs_tl_d_req),
2192 .regs_tl_d_o(rv_dm_regs_tl_d_rsp),
2193 .mem_tl_d_i(rv_dm_mem_tl_d_req),
2194 .mem_tl_d_o(rv_dm_mem_tl_d_rsp),
2195 .scanmode_i,
2196 .scan_rst_ni,
2197
2198 // Clock and reset connections
2199 .clk_i (clkmgr_aon_clocks.clk_main_infra),
2200 .clk_lc_i (clkmgr_aon_clocks.clk_main_infra),
2201 .rst_ni (rstmgr_aon_resets.rst_sys_n[rstmgr_pkg::Domain0Sel]),
2202 .rst_lc_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2203 );
2204 rv_plic #(
2205 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[41:41])
2206 ) u_rv_plic (
2207 // [41]: fatal_fault
2208 .alert_tx_o ( alert_tx[41:41] ),
2209 .alert_rx_i ( alert_rx[41:41] ),
2210
2211 // Inter-module signals
2212 .irq_o(rv_plic_irq),
2213 .irq_id_o(),
2214 .msip_o(rv_plic_msip),
2215 .tl_i(rv_plic_tl_req),
2216 .tl_o(rv_plic_tl_rsp),
2217 .intr_src_i (intr_vector),
2218
2219 // Clock and reset connections
2220 .clk_i (clkmgr_aon_clocks.clk_main_secure),
2221 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2222 );
2223 aes #(
2224 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[43:42]),
2225 .AES192Enable(1'b1),
2226 .SecMasking(SecAesMasking),
2227 .SecSBoxImpl(SecAesSBoxImpl),
2228 .SecStartTriggerDelay(SecAesStartTriggerDelay),
2229 .SecAllowForcingMasks(SecAesAllowForcingMasks),
2230 .SecSkipPRNGReseeding(SecAesSkipPRNGReseeding),
2231 .RndCnstClearingLfsrSeed(RndCnstAesClearingLfsrSeed),
2232 .RndCnstClearingLfsrPerm(RndCnstAesClearingLfsrPerm),
2233 .RndCnstClearingSharePerm(RndCnstAesClearingSharePerm),
2234 .RndCnstMaskingLfsrSeed(RndCnstAesMaskingLfsrSeed),
2235 .RndCnstMaskingLfsrPerm(RndCnstAesMaskingLfsrPerm)
2236 ) u_aes (
2237 // [42]: recov_ctrl_update_err
2238 // [43]: fatal_fault
2239 .alert_tx_o ( alert_tx[43:42] ),
2240 .alert_rx_i ( alert_rx[43:42] ),
2241
2242 // Inter-module signals
2243 .idle_o(clkmgr_aon_idle[0]),
2244 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
2245 .edn_o(edn0_edn_req[5]),
2246 .edn_i(edn0_edn_rsp[5]),
2247 .keymgr_key_i(keymgr_aes_key),
2248 .tl_i(aes_tl_req),
2249 .tl_o(aes_tl_rsp),
2250
2251 // Clock and reset connections
2252 .clk_i (clkmgr_aon_clocks.clk_main_aes),
2253 .clk_edn_i (clkmgr_aon_clocks.clk_main_aes),
2254 .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]),
2255 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2256 .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2257 );
2258 hmac #(
2259 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[44:44])
2260 ) u_hmac (
2261
2262 // Interrupt
2263 .intr_hmac_done_o (intr_hmac_hmac_done),
2264 .intr_fifo_empty_o (intr_hmac_fifo_empty),
2265 .intr_hmac_err_o (intr_hmac_hmac_err),
2266 // [44]: fatal_fault
2267 .alert_tx_o ( alert_tx[44:44] ),
2268 .alert_rx_i ( alert_rx[44:44] ),
2269
2270 // Inter-module signals
2271 .idle_o(clkmgr_aon_idle[1]),
2272 .tl_i(hmac_tl_req),
2273 .tl_o(hmac_tl_rsp),
2274
2275 // Clock and reset connections
2276 .clk_i (clkmgr_aon_clocks.clk_main_hmac),
2277 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2278 );
2279 kmac #(
2280 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[46:45]),
2281 .EnMasking(KmacEnMasking),
2282 .SwKeyMasked(KmacSwKeyMasked),
2283 .SecCmdDelay(SecKmacCmdDelay),
2284 .SecIdleAcceptSwMsg(SecKmacIdleAcceptSwMsg),
2285 .RndCnstLfsrSeed(RndCnstKmacLfsrSeed),
2286 .RndCnstLfsrPerm(RndCnstKmacLfsrPerm),
2287 .RndCnstBufferLfsrSeed(RndCnstKmacBufferLfsrSeed),
2288 .RndCnstMsgPerm(RndCnstKmacMsgPerm)
2289 ) u_kmac (
2290
2291 // Interrupt
2292 .intr_kmac_done_o (intr_kmac_kmac_done),
2293 .intr_fifo_empty_o (intr_kmac_fifo_empty),
2294 .intr_kmac_err_o (intr_kmac_kmac_err),
2295 // [45]: recov_operation_err
2296 // [46]: fatal_fault_err
2297 .alert_tx_o ( alert_tx[46:45] ),
2298 .alert_rx_i ( alert_rx[46:45] ),
2299
2300 // Inter-module signals
2301 .keymgr_key_i(keymgr_kmac_key),
2302 .app_i(kmac_app_req),
2303 .app_o(kmac_app_rsp),
2304 .entropy_o(edn0_edn_req[3]),
2305 .entropy_i(edn0_edn_rsp[3]),
2306 .idle_o(clkmgr_aon_idle[2]),
2307 .en_masking_o(kmac_en_masking),
2308 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
2309 .tl_i(kmac_tl_req),
2310 .tl_o(kmac_tl_rsp),
2311
2312 // Clock and reset connections
2313 .clk_i (clkmgr_aon_clocks.clk_main_kmac),
2314 .clk_edn_i (clkmgr_aon_clocks.clk_main_kmac),
2315 .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]),
2316 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2317 .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2318 );
2319 otbn #(
2320 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[48:47]),
2321 .Stub(OtbnStub),
2322 .RegFile(OtbnRegFile),
2323 .RndCnstUrndPrngSeed(RndCnstOtbnUrndPrngSeed),
2324 .SecMuteUrnd(SecOtbnMuteUrnd),
2325 .SecSkipUrndReseedAtStart(SecOtbnSkipUrndReseedAtStart),
2326 .RndCnstOtbnKey(RndCnstOtbnOtbnKey),
2327 .RndCnstOtbnNonce(RndCnstOtbnOtbnNonce)
2328 ) u_otbn (
2329
2330 // Interrupt
2331 .intr_done_o (intr_otbn_done),
2332 // [47]: fatal
2333 // [48]: recov
2334 .alert_tx_o ( alert_tx[48:47] ),
2335 .alert_rx_i ( alert_rx[48:47] ),
2336
2337 // Inter-module signals
2338 .otbn_otp_key_o(otp_ctrl_otbn_otp_key_req),
2339 .otbn_otp_key_i(otp_ctrl_otbn_otp_key_rsp),
2340 .edn_rnd_o(edn1_edn_req[0]),
2341 .edn_rnd_i(edn1_edn_rsp[0]),
2342 .edn_urnd_o(edn0_edn_req[6]),
2343 .edn_urnd_i(edn0_edn_rsp[6]),
2344 .idle_o(clkmgr_aon_idle[3]),
2345 .ram_cfg_i(ast_ram_1p_cfg),
2346 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
2347 .lc_rma_req_i(lc_ctrl_lc_flash_rma_req),
2348 .lc_rma_ack_o(lc_ctrl_lc_flash_rma_ack[1]),
2349 .keymgr_key_i(keymgr_otbn_key),
2350 .tl_i(otbn_tl_req),
2351 .tl_o(otbn_tl_rsp),
2352
2353 // Clock and reset connections
2354 .clk_i (clkmgr_aon_clocks.clk_main_otbn),
2355 .clk_edn_i (clkmgr_aon_clocks.clk_main_secure),
2356 .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_secure),
2357 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2358 .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2359 .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
2360 );
2361 keymgr #(
2362 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[50:49]),
2363 .UseOtpSeedsInsteadOfFlash(KeymgrUseOtpSeedsInsteadOfFlash),
2364 .KmacEnMasking(KeymgrKmacEnMasking),
2365 .RndCnstLfsrSeed(RndCnstKeymgrLfsrSeed),
2366 .RndCnstLfsrPerm(RndCnstKeymgrLfsrPerm),
2367 .RndCnstRandPerm(RndCnstKeymgrRandPerm),
2368 .RndCnstRevisionSeed(RndCnstKeymgrRevisionSeed),
2369 .RndCnstCreatorIdentitySeed(RndCnstKeymgrCreatorIdentitySeed),
2370 .RndCnstOwnerIntIdentitySeed(RndCnstKeymgrOwnerIntIdentitySeed),
2371 .RndCnstOwnerIdentitySeed(RndCnstKeymgrOwnerIdentitySeed),
2372 .RndCnstSoftOutputSeed(RndCnstKeymgrSoftOutputSeed),
2373 .RndCnstHardOutputSeed(RndCnstKeymgrHardOutputSeed),
2374 .RndCnstAesSeed(RndCnstKeymgrAesSeed),
2375 .RndCnstKmacSeed(RndCnstKeymgrKmacSeed),
2376 .RndCnstOtbnSeed(RndCnstKeymgrOtbnSeed),
2377 .RndCnstCdi(RndCnstKeymgrCdi),
2378 .RndCnstNoneSeed(RndCnstKeymgrNoneSeed)
2379 ) u_keymgr (
2380
2381 // Interrupt
2382 .intr_op_done_o (intr_keymgr_op_done),
2383 // [49]: recov_operation_err
2384 // [50]: fatal_fault_err
2385 .alert_tx_o ( alert_tx[50:49] ),
2386 .alert_rx_i ( alert_rx[50:49] ),
2387
2388 // Inter-module signals
2389 .edn_o(edn0_edn_req[0]),
2390 .edn_i(edn0_edn_rsp[0]),
2391 .aes_key_o(keymgr_aes_key),
2392 .kmac_key_o(keymgr_kmac_key),
2393 .otbn_key_o(keymgr_otbn_key),
2394 .kmac_data_o(kmac_app_req[0]),
2395 .kmac_data_i(kmac_app_rsp[0]),
2396 .otp_key_i(otp_ctrl_otp_keymgr_key),
2397 .otp_device_id_i(keymgr_otp_device_id),
2398 .flash_i(flash_ctrl_keymgr),
2399 .lc_keymgr_en_i(lc_ctrl_lc_keymgr_en),
2400 .lc_keymgr_div_i(lc_ctrl_lc_keymgr_div),
2401 .rom_digest_i(rom_ctrl_keymgr_data),
2402 .kmac_en_masking_i(kmac_en_masking),
2403 .tl_i(keymgr_tl_req),
2404 .tl_o(keymgr_tl_rsp),
2405
2406 // Clock and reset connections
2407 .clk_i (clkmgr_aon_clocks.clk_main_secure),
2408 .clk_edn_i (clkmgr_aon_clocks.clk_main_secure),
2409 .rst_shadowed_ni (rstmgr_aon_resets.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel]),
2410 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2411 .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2412 );
2413 csrng #(
2414 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[52:51]),
2415 .RndCnstCsKeymgrDivNonProduction(RndCnstCsrngCsKeymgrDivNonProduction),
2416 .RndCnstCsKeymgrDivProduction(RndCnstCsrngCsKeymgrDivProduction),
2417 .SBoxImpl(CsrngSBoxImpl)
2418 ) u_csrng (
2419
2420 // Interrupt
2421 .intr_cs_cmd_req_done_o (intr_csrng_cs_cmd_req_done),
2422 .intr_cs_entropy_req_o (intr_csrng_cs_entropy_req),
2423 .intr_cs_hw_inst_exc_o (intr_csrng_cs_hw_inst_exc),
2424 .intr_cs_fatal_err_o (intr_csrng_cs_fatal_err),
2425 // [51]: recov_alert
2426 // [52]: fatal_alert
2427 .alert_tx_o ( alert_tx[52:51] ),
2428 .alert_rx_i ( alert_rx[52:51] ),
2429
2430 // Inter-module signals
2431 .csrng_cmd_i(csrng_csrng_cmd_req),
2432 .csrng_cmd_o(csrng_csrng_cmd_rsp),
2433 .entropy_src_hw_if_o(csrng_entropy_src_hw_if_req),
2434 .entropy_src_hw_if_i(csrng_entropy_src_hw_if_rsp),
2435 .cs_aes_halt_i(csrng_cs_aes_halt_req),
2436 .cs_aes_halt_o(csrng_cs_aes_halt_rsp),
2437 .otp_en_csrng_sw_app_read_i(csrng_otp_en_csrng_sw_app_read),
2438 .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
2439 .tl_i(csrng_tl_req),
2440 .tl_o(csrng_tl_rsp),
2441
2442 // Clock and reset connections
2443 .clk_i (clkmgr_aon_clocks.clk_main_secure),
2444 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2445 );
2446 entropy_src #(
2447 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[54:53]),
2448 .EsFifoDepth(EntropySrcEsFifoDepth),
2449 .DistrFifoDepth(EntropySrcDistrFifoDepth),
2450 .Stub(EntropySrcStub)
2451 ) u_entropy_src (
2452
2453 // Interrupt
2454 .intr_es_entropy_valid_o (intr_entropy_src_es_entropy_valid),
2455 .intr_es_health_test_failed_o (intr_entropy_src_es_health_test_failed),
2456 .intr_es_observe_fifo_ready_o (intr_entropy_src_es_observe_fifo_ready),
2457 .intr_es_fatal_err_o (intr_entropy_src_es_fatal_err),
2458 // [53]: recov_alert
2459 // [54]: fatal_alert
2460 .alert_tx_o ( alert_tx[54:53] ),
2461 .alert_rx_i ( alert_rx[54:53] ),
2462
2463 // Inter-module signals
2464 .entropy_src_hw_if_i(csrng_entropy_src_hw_if_req),
2465 .entropy_src_hw_if_o(csrng_entropy_src_hw_if_rsp),
2466 .cs_aes_halt_o(csrng_cs_aes_halt_req),
2467 .cs_aes_halt_i(csrng_cs_aes_halt_rsp),
2468 .entropy_src_rng_o(es_rng_req_o),
2469 .entropy_src_rng_i(es_rng_rsp_i),
2470 .entropy_src_xht_o(),
2471 .entropy_src_xht_i(entropy_src_pkg::ENTROPY_SRC_XHT_RSP_DEFAULT),
2472 .otp_en_entropy_src_fw_read_i(prim_mubi_pkg::MuBi8True),
2473 .otp_en_entropy_src_fw_over_i(prim_mubi_pkg::MuBi8True),
2474 .rng_fips_o(es_rng_fips_o),
2475 .tl_i(entropy_src_tl_req),
2476 .tl_o(entropy_src_tl_rsp),
2477
2478 // Clock and reset connections
2479 .clk_i (clkmgr_aon_clocks.clk_main_secure),
2480 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2481 );
2482 edn #(
2483 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[56:55])
2484 ) u_edn0 (
2485
2486 // Interrupt
2487 .intr_edn_cmd_req_done_o (intr_edn0_edn_cmd_req_done),
2488 .intr_edn_fatal_err_o (intr_edn0_edn_fatal_err),
2489 // [55]: recov_alert
2490 // [56]: fatal_alert
2491 .alert_tx_o ( alert_tx[56:55] ),
2492 .alert_rx_i ( alert_rx[56:55] ),
2493
2494 // Inter-module signals
2495 .csrng_cmd_o(csrng_csrng_cmd_req[0]),
2496 .csrng_cmd_i(csrng_csrng_cmd_rsp[0]),
2497 .edn_i(edn0_edn_req),
2498 .edn_o(edn0_edn_rsp),
2499 .tl_i(edn0_tl_req),
2500 .tl_o(edn0_tl_rsp),
2501
2502 // Clock and reset connections
2503 .clk_i (clkmgr_aon_clocks.clk_main_secure),
2504 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2505 );
2506 edn #(
2507 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[58:57])
2508 ) u_edn1 (
2509
2510 // Interrupt
2511 .intr_edn_cmd_req_done_o (intr_edn1_edn_cmd_req_done),
2512 .intr_edn_fatal_err_o (intr_edn1_edn_fatal_err),
2513 // [57]: recov_alert
2514 // [58]: fatal_alert
2515 .alert_tx_o ( alert_tx[58:57] ),
2516 .alert_rx_i ( alert_rx[58:57] ),
2517
2518 // Inter-module signals
2519 .csrng_cmd_o(csrng_csrng_cmd_req[1]),
2520 .csrng_cmd_i(csrng_csrng_cmd_rsp[1]),
2521 .edn_i(edn1_edn_req),
2522 .edn_o(edn1_edn_rsp),
2523 .tl_i(edn1_tl_req),
2524 .tl_o(edn1_tl_rsp),
2525
2526 // Clock and reset connections
2527 .clk_i (clkmgr_aon_clocks.clk_main_secure),
2528 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2529 );
2530 sram_ctrl #(
2531 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[59:59]),
2532 .RndCnstSramKey(RndCnstSramCtrlMainSramKey),
2533 .RndCnstSramNonce(RndCnstSramCtrlMainSramNonce),
2534 .RndCnstLfsrSeed(RndCnstSramCtrlMainLfsrSeed),
2535 .RndCnstLfsrPerm(RndCnstSramCtrlMainLfsrPerm),
2536 .MemSizeRam(131072),
2537 .InstrExec(SramCtrlMainInstrExec)
2538 ) u_sram_ctrl_main (
2539 // [59]: fatal_error
2540 .alert_tx_o ( alert_tx[59:59] ),
2541 .alert_rx_i ( alert_rx[59:59] ),
2542
2543 // Inter-module signals
2544 .sram_otp_key_o(otp_ctrl_sram_otp_key_req[0]),
2545 .sram_otp_key_i(otp_ctrl_sram_otp_key_rsp[0]),
2546 .cfg_i(ast_ram_1p_cfg),
2547 .lc_escalate_en_i(lc_ctrl_lc_escalate_en),
2548 .lc_hw_debug_en_i(lc_ctrl_lc_hw_debug_en),
2549 .otp_en_sram_ifetch_i(sram_ctrl_main_otp_en_sram_ifetch),
2550 .regs_tl_i(sram_ctrl_main_regs_tl_req),
2551 .regs_tl_o(sram_ctrl_main_regs_tl_rsp),
2552 .ram_tl_i(sram_ctrl_main_ram_tl_req),
2553 .ram_tl_o(sram_ctrl_main_ram_tl_rsp),
2554
2555 // Clock and reset connections
2556 .clk_i (clkmgr_aon_clocks.clk_main_infra),
2557 .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_infra),
2558 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2559 .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
2560 );
2561 rom_ctrl #(
2562 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[60:60]),
2563 .BootRomInitFile(RomCtrlBootRomInitFile),
2564 .RndCnstScrNonce(RndCnstRomCtrlScrNonce),
2565 .RndCnstScrKey(RndCnstRomCtrlScrKey),
2566 .SecDisableScrambling(SecRomCtrlDisableScrambling),
2567 .MemSizeRom(32768)
2568 ) u_rom_ctrl (
2569 // [60]: fatal
2570 .alert_tx_o ( alert_tx[60:60] ),
2571 .alert_rx_i ( alert_rx[60:60] ),
2572
2573 // Inter-module signals
2574 .rom_cfg_i(ast_rom_cfg),
2575 .pwrmgr_data_o(rom_ctrl_pwrmgr_data),
2576 .keymgr_data_o(rom_ctrl_keymgr_data),
2577 .kmac_data_o(kmac_app_req[2]),
2578 .kmac_data_i(kmac_app_rsp[2]),
2579 .regs_tl_i(rom_ctrl_regs_tl_req),
2580 .regs_tl_o(rom_ctrl_regs_tl_rsp),
2581 .rom_tl_i(rom_ctrl_rom_tl_req),
2582 .rom_tl_o(rom_ctrl_rom_tl_rsp),
2583
2584 // Clock and reset connections
2585 .clk_i (clkmgr_aon_clocks.clk_main_infra),
2586 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel])
2587 );
2588 rv_core_ibex #(
2589 .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[64:61]),
2590 .RndCnstLfsrSeed(RndCnstRvCoreIbexLfsrSeed),
2591 .RndCnstLfsrPerm(RndCnstRvCoreIbexLfsrPerm),
2592 .RndCnstIbexKeyDefault(RndCnstRvCoreIbexIbexKeyDefault),
2593 .RndCnstIbexNonceDefault(RndCnstRvCoreIbexIbexNonceDefault),
2594 .PMPEnable(RvCoreIbexPMPEnable),
2595 .PMPGranularity(RvCoreIbexPMPGranularity),
2596 .PMPNumRegions(RvCoreIbexPMPNumRegions),
2597 .MHPMCounterNum(RvCoreIbexMHPMCounterNum),
2598 .MHPMCounterWidth(RvCoreIbexMHPMCounterWidth),
2599 .RV32E(RvCoreIbexRV32E),
2600 .RV32M(RvCoreIbexRV32M),
2601 .RV32B(RvCoreIbexRV32B),
2602 .RegFile(RvCoreIbexRegFile),
2603 .BranchTargetALU(RvCoreIbexBranchTargetALU),
2604 .WritebackStage(RvCoreIbexWritebackStage),
2605 .ICache(RvCoreIbexICache),
2606 .ICacheECC(RvCoreIbexICacheECC),
2607 .ICacheScramble(RvCoreIbexICacheScramble),
2608 .BranchPredictor(RvCoreIbexBranchPredictor),
2609 .DbgTriggerEn(RvCoreIbexDbgTriggerEn),
2610 .DbgHwBreakNum(RvCoreIbexDbgHwBreakNum),
2611 .SecureIbex(RvCoreIbexSecureIbex),
2612 .DmHaltAddr(RvCoreIbexDmHaltAddr),
2613 .DmExceptionAddr(RvCoreIbexDmExceptionAddr),
2614 .PipeLine(RvCoreIbexPipeLine)
2615 ) u_rv_core_ibex (
2616 // [61]: fatal_sw_err
2617 // [62]: recov_sw_err
2618 // [63]: fatal_hw_err
2619 // [64]: recov_hw_err
2620 .alert_tx_o ( alert_tx[64:61] ),
2621 .alert_rx_i ( alert_rx[64:61] ),
2622
2623 // Inter-module signals
2624 .rst_cpu_n_o(),
2625 .ram_cfg_i(ast_ram_1p_cfg),
2626 .hart_id_i(rv_core_ibex_hart_id),
2627 .boot_addr_i(rv_core_ibex_boot_addr),
2628 .irq_software_i(rv_plic_msip),
2629 .irq_timer_i(rv_core_ibex_irq_timer),
2630 .irq_external_i(rv_plic_irq),
2631 .esc_tx_i(alert_handler_esc_tx[0]),
2632 .esc_rx_o(alert_handler_esc_rx[0]),
2633 .debug_req_i(rv_dm_debug_req),
2634 .crash_dump_o(rv_core_ibex_crash_dump),
2635 .lc_cpu_en_i(lc_ctrl_lc_cpu_en),
2636 .pwrmgr_cpu_en_i(pwrmgr_aon_fetch_en),
2637 .pwrmgr_o(rv_core_ibex_pwrmgr),
2638 .nmi_wdog_i(aon_timer_aon_nmi_wdog_timer_bark),
2639 .edn_o(edn0_edn_req[7]),
2640 .edn_i(edn0_edn_rsp[7]),
2641 .icache_otp_key_o(otp_ctrl_sram_otp_key_req[2]),
2642 .icache_otp_key_i(otp_ctrl_sram_otp_key_rsp[2]),
2643 .fpga_info_i(fpga_info_i),
2644 .corei_tl_h_o(main_tl_rv_core_ibex__corei_req),
2645 .corei_tl_h_i(main_tl_rv_core_ibex__corei_rsp),
2646 .cored_tl_h_o(main_tl_rv_core_ibex__cored_req),
2647 .cored_tl_h_i(main_tl_rv_core_ibex__cored_rsp),
2648 .cfg_tl_d_i(rv_core_ibex_cfg_tl_d_req),
2649 .cfg_tl_d_o(rv_core_ibex_cfg_tl_d_rsp),
2650 .scanmode_i,
2651 .scan_rst_ni,
2652
2653 // Clock and reset connections
2654 .clk_i (clkmgr_aon_clocks.clk_main_infra),
2655 .clk_edn_i (clkmgr_aon_clocks.clk_main_infra),
2656 .clk_esc_i (clkmgr_aon_clocks.clk_io_div4_secure),
2657 .clk_otp_i (clkmgr_aon_clocks.clk_io_div4_secure),
2658 .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2659 .rst_edn_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2660 .rst_esc_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
2661 .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel])
2662 );
2663 // interrupt assignments
2664 1/1 assign intr_vector = {
Tests: T1 T3 T4
2665 intr_edn1_edn_fatal_err, // IDs [185 +: 1]
2666 intr_edn1_edn_cmd_req_done, // IDs [184 +: 1]
2667 intr_edn0_edn_fatal_err, // IDs [183 +: 1]
2668 intr_edn0_edn_cmd_req_done, // IDs [182 +: 1]
2669 intr_entropy_src_es_fatal_err, // IDs [181 +: 1]
2670 intr_entropy_src_es_observe_fifo_ready, // IDs [180 +: 1]
2671 intr_entropy_src_es_health_test_failed, // IDs [179 +: 1]
2672 intr_entropy_src_es_entropy_valid, // IDs [178 +: 1]
2673 intr_csrng_cs_fatal_err, // IDs [177 +: 1]
2674 intr_csrng_cs_hw_inst_exc, // IDs [176 +: 1]
2675 intr_csrng_cs_entropy_req, // IDs [175 +: 1]
2676 intr_csrng_cs_cmd_req_done, // IDs [174 +: 1]
2677 intr_keymgr_op_done, // IDs [173 +: 1]
2678 intr_otbn_done, // IDs [172 +: 1]
2679 intr_kmac_kmac_err, // IDs [171 +: 1]
2680 intr_kmac_fifo_empty, // IDs [170 +: 1]
2681 intr_kmac_kmac_done, // IDs [169 +: 1]
2682 intr_hmac_hmac_err, // IDs [168 +: 1]
2683 intr_hmac_fifo_empty, // IDs [167 +: 1]
2684 intr_hmac_hmac_done, // IDs [166 +: 1]
2685 intr_flash_ctrl_corr_err, // IDs [165 +: 1]
2686 intr_flash_ctrl_op_done, // IDs [164 +: 1]
2687 intr_flash_ctrl_rd_lvl, // IDs [163 +: 1]
2688 intr_flash_ctrl_rd_full, // IDs [162 +: 1]
2689 intr_flash_ctrl_prog_lvl, // IDs [161 +: 1]
2690 intr_flash_ctrl_prog_empty, // IDs [160 +: 1]
2691 intr_sensor_ctrl_aon_init_status_change, // IDs [159 +: 1]
2692 intr_sensor_ctrl_aon_io_status_change, // IDs [158 +: 1]
2693 intr_aon_timer_aon_wdog_timer_bark, // IDs [157 +: 1]
2694 intr_aon_timer_aon_wkup_timer_expired, // IDs [156 +: 1]
2695 intr_adc_ctrl_aon_match_pending, // IDs [155 +: 1]
2696 intr_sysrst_ctrl_aon_event_detected, // IDs [154 +: 1]
2697 intr_pwrmgr_aon_wakeup, // IDs [153 +: 1]
2698 intr_usbdev_av_setup_empty, // IDs [152 +: 1]
2699 intr_usbdev_link_out_err, // IDs [151 +: 1]
2700 intr_usbdev_powered, // IDs [150 +: 1]
2701 intr_usbdev_frame, // IDs [149 +: 1]
2702 intr_usbdev_rx_bitstuff_err, // IDs [148 +: 1]
2703 intr_usbdev_rx_pid_err, // IDs [147 +: 1]
2704 intr_usbdev_rx_crc_err, // IDs [146 +: 1]
2705 intr_usbdev_link_in_err, // IDs [145 +: 1]
2706 intr_usbdev_av_overflow, // IDs [144 +: 1]
2707 intr_usbdev_rx_full, // IDs [143 +: 1]
2708 intr_usbdev_av_out_empty, // IDs [142 +: 1]
2709 intr_usbdev_link_resume, // IDs [141 +: 1]
2710 intr_usbdev_link_suspend, // IDs [140 +: 1]
2711 intr_usbdev_link_reset, // IDs [139 +: 1]
2712 intr_usbdev_host_lost, // IDs [138 +: 1]
2713 intr_usbdev_disconnected, // IDs [137 +: 1]
2714 intr_usbdev_pkt_sent, // IDs [136 +: 1]
2715 intr_usbdev_pkt_received, // IDs [135 +: 1]
2716 intr_spi_host1_spi_event, // IDs [134 +: 1]
2717 intr_spi_host1_error, // IDs [133 +: 1]
2718 intr_spi_host0_spi_event, // IDs [132 +: 1]
2719 intr_spi_host0_error, // IDs [131 +: 1]
2720 intr_alert_handler_classd, // IDs [130 +: 1]
2721 intr_alert_handler_classc, // IDs [129 +: 1]
2722 intr_alert_handler_classb, // IDs [128 +: 1]
2723 intr_alert_handler_classa, // IDs [127 +: 1]
2724 intr_otp_ctrl_otp_error, // IDs [126 +: 1]
2725 intr_otp_ctrl_otp_operation_done, // IDs [125 +: 1]
2726 intr_rv_timer_timer_expired_hart0_timer0, // IDs [124 +: 1]
2727 intr_pattgen_done_ch1, // IDs [123 +: 1]
2728 intr_pattgen_done_ch0, // IDs [122 +: 1]
2729 intr_i2c2_host_timeout, // IDs [121 +: 1]
2730 intr_i2c2_unexp_stop, // IDs [120 +: 1]
2731 intr_i2c2_acq_stretch, // IDs [119 +: 1]
2732 intr_i2c2_tx_threshold, // IDs [118 +: 1]
2733 intr_i2c2_tx_stretch, // IDs [117 +: 1]
2734 intr_i2c2_cmd_complete, // IDs [116 +: 1]
2735 intr_i2c2_sda_unstable, // IDs [115 +: 1]
2736 intr_i2c2_stretch_timeout, // IDs [114 +: 1]
2737 intr_i2c2_sda_interference, // IDs [113 +: 1]
2738 intr_i2c2_scl_interference, // IDs [112 +: 1]
2739 intr_i2c2_controller_halt, // IDs [111 +: 1]
2740 intr_i2c2_rx_overflow, // IDs [110 +: 1]
2741 intr_i2c2_acq_threshold, // IDs [109 +: 1]
2742 intr_i2c2_rx_threshold, // IDs [108 +: 1]
2743 intr_i2c2_fmt_threshold, // IDs [107 +: 1]
2744 intr_i2c1_host_timeout, // IDs [106 +: 1]
2745 intr_i2c1_unexp_stop, // IDs [105 +: 1]
2746 intr_i2c1_acq_stretch, // IDs [104 +: 1]
2747 intr_i2c1_tx_threshold, // IDs [103 +: 1]
2748 intr_i2c1_tx_stretch, // IDs [102 +: 1]
2749 intr_i2c1_cmd_complete, // IDs [101 +: 1]
2750 intr_i2c1_sda_unstable, // IDs [100 +: 1]
2751 intr_i2c1_stretch_timeout, // IDs [99 +: 1]
2752 intr_i2c1_sda_interference, // IDs [98 +: 1]
2753 intr_i2c1_scl_interference, // IDs [97 +: 1]
2754 intr_i2c1_controller_halt, // IDs [96 +: 1]
2755 intr_i2c1_rx_overflow, // IDs [95 +: 1]
2756 intr_i2c1_acq_threshold, // IDs [94 +: 1]
2757 intr_i2c1_rx_threshold, // IDs [93 +: 1]
2758 intr_i2c1_fmt_threshold, // IDs [92 +: 1]
2759 intr_i2c0_host_timeout, // IDs [91 +: 1]
2760 intr_i2c0_unexp_stop, // IDs [90 +: 1]
2761 intr_i2c0_acq_stretch, // IDs [89 +: 1]
2762 intr_i2c0_tx_threshold, // IDs [88 +: 1]
2763 intr_i2c0_tx_stretch, // IDs [87 +: 1]
2764 intr_i2c0_cmd_complete, // IDs [86 +: 1]
2765 intr_i2c0_sda_unstable, // IDs [85 +: 1]
2766 intr_i2c0_stretch_timeout, // IDs [84 +: 1]
2767 intr_i2c0_sda_interference, // IDs [83 +: 1]
2768 intr_i2c0_scl_interference, // IDs [82 +: 1]
2769 intr_i2c0_controller_halt, // IDs [81 +: 1]
2770 intr_i2c0_rx_overflow, // IDs [80 +: 1]
2771 intr_i2c0_acq_threshold, // IDs [79 +: 1]
2772 intr_i2c0_rx_threshold, // IDs [78 +: 1]
2773 intr_i2c0_fmt_threshold, // IDs [77 +: 1]
2774 intr_spi_device_tpm_rdfifo_drop, // IDs [76 +: 1]
2775 intr_spi_device_tpm_rdfifo_cmd_end, // IDs [75 +: 1]
2776 intr_spi_device_tpm_header_not_empty, // IDs [74 +: 1]
2777 intr_spi_device_readbuf_flip, // IDs [73 +: 1]
2778 intr_spi_device_readbuf_watermark, // IDs [72 +: 1]
2779 intr_spi_device_upload_payload_overflow, // IDs [71 +: 1]
2780 intr_spi_device_upload_payload_not_empty, // IDs [70 +: 1]
2781 intr_spi_device_upload_cmdfifo_not_empty, // IDs [69 +: 1]
2782 intr_gpio_gpio, // IDs [37 +: 32]
2783 intr_uart3_tx_empty, // IDs [36 +: 1]
2784 intr_uart3_rx_parity_err, // IDs [35 +: 1]
2785 intr_uart3_rx_timeout, // IDs [34 +: 1]
2786 intr_uart3_rx_break_err, // IDs [33 +: 1]
2787 intr_uart3_rx_frame_err, // IDs [32 +: 1]
2788 intr_uart3_rx_overflow, // IDs [31 +: 1]
2789 intr_uart3_tx_done, // IDs [30 +: 1]
2790 intr_uart3_rx_watermark, // IDs [29 +: 1]
2791 intr_uart3_tx_watermark, // IDs [28 +: 1]
2792 intr_uart2_tx_empty, // IDs [27 +: 1]
2793 intr_uart2_rx_parity_err, // IDs [26 +: 1]
2794 intr_uart2_rx_timeout, // IDs [25 +: 1]
2795 intr_uart2_rx_break_err, // IDs [24 +: 1]
2796 intr_uart2_rx_frame_err, // IDs [23 +: 1]
2797 intr_uart2_rx_overflow, // IDs [22 +: 1]
2798 intr_uart2_tx_done, // IDs [21 +: 1]
2799 intr_uart2_rx_watermark, // IDs [20 +: 1]
2800 intr_uart2_tx_watermark, // IDs [19 +: 1]
2801 intr_uart1_tx_empty, // IDs [18 +: 1]
2802 intr_uart1_rx_parity_err, // IDs [17 +: 1]
2803 intr_uart1_rx_timeout, // IDs [16 +: 1]
2804 intr_uart1_rx_break_err, // IDs [15 +: 1]
2805 intr_uart1_rx_frame_err, // IDs [14 +: 1]
2806 intr_uart1_rx_overflow, // IDs [13 +: 1]
2807 intr_uart1_tx_done, // IDs [12 +: 1]
2808 intr_uart1_rx_watermark, // IDs [11 +: 1]
2809 intr_uart1_tx_watermark, // IDs [10 +: 1]
2810 intr_uart0_tx_empty, // IDs [9 +: 1]
2811 intr_uart0_rx_parity_err, // IDs [8 +: 1]
2812 intr_uart0_rx_timeout, // IDs [7 +: 1]
2813 intr_uart0_rx_break_err, // IDs [6 +: 1]
2814 intr_uart0_rx_frame_err, // IDs [5 +: 1]
2815 intr_uart0_rx_overflow, // IDs [4 +: 1]
2816 intr_uart0_tx_done, // IDs [3 +: 1]
2817 intr_uart0_rx_watermark, // IDs [2 +: 1]
2818 intr_uart0_tx_watermark, // IDs [1 +: 1]
2819 1'b 0 // ID [0 +: 1] is a special case and tied to zero.
2820 };
2821
2822 // TL-UL Crossbar
2823 xbar_main u_xbar_main (
2824 .clk_main_i (clkmgr_aon_clocks.clk_main_infra),
2825 .clk_fixed_i (clkmgr_aon_clocks.clk_io_div4_infra),
2826 .clk_usb_i (clkmgr_aon_clocks.clk_usb_infra),
2827 .clk_spi_host0_i (clkmgr_aon_clocks.clk_io_infra),
2828 .clk_spi_host1_i (clkmgr_aon_clocks.clk_io_div2_infra),
2829 .rst_main_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
2830 .rst_fixed_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
2831 .rst_usb_ni (rstmgr_aon_resets.rst_lc_usb_n[rstmgr_pkg::Domain0Sel]),
2832 .rst_spi_host0_ni (rstmgr_aon_resets.rst_lc_io_n[rstmgr_pkg::Domain0Sel]),
2833 .rst_spi_host1_ni (rstmgr_aon_resets.rst_lc_io_div2_n[rstmgr_pkg::Domain0Sel]),
2834
2835 // port: tl_rv_core_ibex__corei
2836 .tl_rv_core_ibex__corei_i(main_tl_rv_core_ibex__corei_req),
2837 .tl_rv_core_ibex__corei_o(main_tl_rv_core_ibex__corei_rsp),
2838
2839 // port: tl_rv_core_ibex__cored
2840 .tl_rv_core_ibex__cored_i(main_tl_rv_core_ibex__cored_req),
2841 .tl_rv_core_ibex__cored_o(main_tl_rv_core_ibex__cored_rsp),
2842
2843 // port: tl_rv_dm__sba
2844 .tl_rv_dm__sba_i(main_tl_rv_dm__sba_req),
2845 .tl_rv_dm__sba_o(main_tl_rv_dm__sba_rsp),
2846
2847 // port: tl_rv_dm__regs
2848 .tl_rv_dm__regs_o(rv_dm_regs_tl_d_req),
2849 .tl_rv_dm__regs_i(rv_dm_regs_tl_d_rsp),
2850
2851 // port: tl_rv_dm__mem
2852 .tl_rv_dm__mem_o(rv_dm_mem_tl_d_req),
2853 .tl_rv_dm__mem_i(rv_dm_mem_tl_d_rsp),
2854
2855 // port: tl_rom_ctrl__rom
2856 .tl_rom_ctrl__rom_o(rom_ctrl_rom_tl_req),
2857 .tl_rom_ctrl__rom_i(rom_ctrl_rom_tl_rsp),
2858
2859 // port: tl_rom_ctrl__regs
2860 .tl_rom_ctrl__regs_o(rom_ctrl_regs_tl_req),
2861 .tl_rom_ctrl__regs_i(rom_ctrl_regs_tl_rsp),
2862
2863 // port: tl_peri
2864 .tl_peri_o(main_tl_peri_req),
2865 .tl_peri_i(main_tl_peri_rsp),
2866
2867 // port: tl_spi_host0
2868 .tl_spi_host0_o(spi_host0_tl_req),
2869 .tl_spi_host0_i(spi_host0_tl_rsp),
2870
2871 // port: tl_spi_host1
2872 .tl_spi_host1_o(spi_host1_tl_req),
2873 .tl_spi_host1_i(spi_host1_tl_rsp),
2874
2875 // port: tl_usbdev
2876 .tl_usbdev_o(usbdev_tl_req),
2877 .tl_usbdev_i(usbdev_tl_rsp),
2878
2879 // port: tl_flash_ctrl__core
2880 .tl_flash_ctrl__core_o(flash_ctrl_core_tl_req),
2881 .tl_flash_ctrl__core_i(flash_ctrl_core_tl_rsp),
2882
2883 // port: tl_flash_ctrl__prim
2884 .tl_flash_ctrl__prim_o(flash_ctrl_prim_tl_req),
2885 .tl_flash_ctrl__prim_i(flash_ctrl_prim_tl_rsp),
2886
2887 // port: tl_flash_ctrl__mem
2888 .tl_flash_ctrl__mem_o(flash_ctrl_mem_tl_req),
2889 .tl_flash_ctrl__mem_i(flash_ctrl_mem_tl_rsp),
2890
2891 // port: tl_hmac
2892 .tl_hmac_o(hmac_tl_req),
2893 .tl_hmac_i(hmac_tl_rsp),
2894
2895 // port: tl_kmac
2896 .tl_kmac_o(kmac_tl_req),
2897 .tl_kmac_i(kmac_tl_rsp),
2898
2899 // port: tl_aes
2900 .tl_aes_o(aes_tl_req),
2901 .tl_aes_i(aes_tl_rsp),
2902
2903 // port: tl_entropy_src
2904 .tl_entropy_src_o(entropy_src_tl_req),
2905 .tl_entropy_src_i(entropy_src_tl_rsp),
2906
2907 // port: tl_csrng
2908 .tl_csrng_o(csrng_tl_req),
2909 .tl_csrng_i(csrng_tl_rsp),
2910
2911 // port: tl_edn0
2912 .tl_edn0_o(edn0_tl_req),
2913 .tl_edn0_i(edn0_tl_rsp),
2914
2915 // port: tl_edn1
2916 .tl_edn1_o(edn1_tl_req),
2917 .tl_edn1_i(edn1_tl_rsp),
2918
2919 // port: tl_rv_plic
2920 .tl_rv_plic_o(rv_plic_tl_req),
2921 .tl_rv_plic_i(rv_plic_tl_rsp),
2922
2923 // port: tl_otbn
2924 .tl_otbn_o(otbn_tl_req),
2925 .tl_otbn_i(otbn_tl_rsp),
2926
2927 // port: tl_keymgr
2928 .tl_keymgr_o(keymgr_tl_req),
2929 .tl_keymgr_i(keymgr_tl_rsp),
2930
2931 // port: tl_rv_core_ibex__cfg
2932 .tl_rv_core_ibex__cfg_o(rv_core_ibex_cfg_tl_d_req),
2933 .tl_rv_core_ibex__cfg_i(rv_core_ibex_cfg_tl_d_rsp),
2934
2935 // port: tl_sram_ctrl_main__regs
2936 .tl_sram_ctrl_main__regs_o(sram_ctrl_main_regs_tl_req),
2937 .tl_sram_ctrl_main__regs_i(sram_ctrl_main_regs_tl_rsp),
2938
2939 // port: tl_sram_ctrl_main__ram
2940 .tl_sram_ctrl_main__ram_o(sram_ctrl_main_ram_tl_req),
2941 .tl_sram_ctrl_main__ram_i(sram_ctrl_main_ram_tl_rsp),
2942
2943
2944 .scanmode_i
2945 );
2946 xbar_peri u_xbar_peri (
2947 .clk_peri_i (clkmgr_aon_clocks.clk_io_div4_infra),
2948 .rst_peri_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
2949
2950 // port: tl_main
2951 .tl_main_i(main_tl_peri_req),
2952 .tl_main_o(main_tl_peri_rsp),
2953
2954 // port: tl_uart0
2955 .tl_uart0_o(uart0_tl_req),
2956 .tl_uart0_i(uart0_tl_rsp),
2957
2958 // port: tl_uart1
2959 .tl_uart1_o(uart1_tl_req),
2960 .tl_uart1_i(uart1_tl_rsp),
2961
2962 // port: tl_uart2
2963 .tl_uart2_o(uart2_tl_req),
2964 .tl_uart2_i(uart2_tl_rsp),
2965
2966 // port: tl_uart3
2967 .tl_uart3_o(uart3_tl_req),
2968 .tl_uart3_i(uart3_tl_rsp),
2969
2970 // port: tl_i2c0
2971 .tl_i2c0_o(i2c0_tl_req),
2972 .tl_i2c0_i(i2c0_tl_rsp),
2973
2974 // port: tl_i2c1
2975 .tl_i2c1_o(i2c1_tl_req),
2976 .tl_i2c1_i(i2c1_tl_rsp),
2977
2978 // port: tl_i2c2
2979 .tl_i2c2_o(i2c2_tl_req),
2980 .tl_i2c2_i(i2c2_tl_rsp),
2981
2982 // port: tl_pattgen
2983 .tl_pattgen_o(pattgen_tl_req),
2984 .tl_pattgen_i(pattgen_tl_rsp),
2985
2986 // port: tl_pwm_aon
2987 .tl_pwm_aon_o(pwm_aon_tl_req),
2988 .tl_pwm_aon_i(pwm_aon_tl_rsp),
2989
2990 // port: tl_gpio
2991 .tl_gpio_o(gpio_tl_req),
2992 .tl_gpio_i(gpio_tl_rsp),
2993
2994 // port: tl_spi_device
2995 .tl_spi_device_o(spi_device_tl_req),
2996 .tl_spi_device_i(spi_device_tl_rsp),
2997
2998 // port: tl_rv_timer
2999 .tl_rv_timer_o(rv_timer_tl_req),
3000 .tl_rv_timer_i(rv_timer_tl_rsp),
3001
3002 // port: tl_pwrmgr_aon
3003 .tl_pwrmgr_aon_o(pwrmgr_aon_tl_req),
3004 .tl_pwrmgr_aon_i(pwrmgr_aon_tl_rsp),
3005
3006 // port: tl_rstmgr_aon
3007 .tl_rstmgr_aon_o(rstmgr_aon_tl_req),
3008 .tl_rstmgr_aon_i(rstmgr_aon_tl_rsp),
3009
3010 // port: tl_clkmgr_aon
3011 .tl_clkmgr_aon_o(clkmgr_aon_tl_req),
3012 .tl_clkmgr_aon_i(clkmgr_aon_tl_rsp),
3013
3014 // port: tl_pinmux_aon
3015 .tl_pinmux_aon_o(pinmux_aon_tl_req),
3016 .tl_pinmux_aon_i(pinmux_aon_tl_rsp),
3017
3018 // port: tl_otp_ctrl__core
3019 .tl_otp_ctrl__core_o(otp_ctrl_core_tl_req),
3020 .tl_otp_ctrl__core_i(otp_ctrl_core_tl_rsp),
3021
3022 // port: tl_otp_ctrl__prim
3023 .tl_otp_ctrl__prim_o(otp_ctrl_prim_tl_req),
3024 .tl_otp_ctrl__prim_i(otp_ctrl_prim_tl_rsp),
3025
3026 // port: tl_lc_ctrl
3027 .tl_lc_ctrl_o(lc_ctrl_tl_req),
3028 .tl_lc_ctrl_i(lc_ctrl_tl_rsp),
3029
3030 // port: tl_sensor_ctrl_aon
3031 .tl_sensor_ctrl_aon_o(sensor_ctrl_aon_tl_req),
3032 .tl_sensor_ctrl_aon_i(sensor_ctrl_aon_tl_rsp),
3033
3034 // port: tl_alert_handler
3035 .tl_alert_handler_o(alert_handler_tl_req),
3036 .tl_alert_handler_i(alert_handler_tl_rsp),
3037
3038 // port: tl_sram_ctrl_ret_aon__regs
3039 .tl_sram_ctrl_ret_aon__regs_o(sram_ctrl_ret_aon_regs_tl_req),
3040 .tl_sram_ctrl_ret_aon__regs_i(sram_ctrl_ret_aon_regs_tl_rsp),
3041
3042 // port: tl_sram_ctrl_ret_aon__ram
3043 .tl_sram_ctrl_ret_aon__ram_o(sram_ctrl_ret_aon_ram_tl_req),
3044 .tl_sram_ctrl_ret_aon__ram_i(sram_ctrl_ret_aon_ram_tl_rsp),
3045
3046 // port: tl_aon_timer_aon
3047 .tl_aon_timer_aon_o(aon_timer_aon_tl_req),
3048 .tl_aon_timer_aon_i(aon_timer_aon_tl_rsp),
3049
3050 // port: tl_sysrst_ctrl_aon
3051 .tl_sysrst_ctrl_aon_o(sysrst_ctrl_aon_tl_req),
3052 .tl_sysrst_ctrl_aon_i(sysrst_ctrl_aon_tl_rsp),
3053
3054 // port: tl_adc_ctrl_aon
3055 .tl_adc_ctrl_aon_o(adc_ctrl_aon_tl_req),
3056 .tl_adc_ctrl_aon_i(adc_ctrl_aon_tl_rsp),
3057
3058 // port: tl_ast
3059 .tl_ast_o(ast_tl_req_o),
3060 .tl_ast_i(ast_tl_rsp_i),
3061
3062
3063 .scanmode_i
3064 );
3065
3066 // Pinmux connections
3067 // All muxed inputs
3068 1/1 assign cio_gpio_gpio_p2d[0] = mio_p2d[MioInGpioGpio0];
Tests: T1 T4 T37
3069 1/1 assign cio_gpio_gpio_p2d[1] = mio_p2d[MioInGpioGpio1];
Tests: T4 T22 T37
3070 1/1 assign cio_gpio_gpio_p2d[2] = mio_p2d[MioInGpioGpio2];
Tests: T4 T22 T37
3071 1/1 assign cio_gpio_gpio_p2d[3] = mio_p2d[MioInGpioGpio3];
Tests: T4 T22 T37
3072 1/1 assign cio_gpio_gpio_p2d[4] = mio_p2d[MioInGpioGpio4];
Tests: T4 T22 T37
3073 1/1 assign cio_gpio_gpio_p2d[5] = mio_p2d[MioInGpioGpio5];
Tests: T4 T22 T37
3074 1/1 assign cio_gpio_gpio_p2d[6] = mio_p2d[MioInGpioGpio6];
Tests: T4 T22 T37
3075 1/1 assign cio_gpio_gpio_p2d[7] = mio_p2d[MioInGpioGpio7];
Tests: T4 T22 T37
3076 1/1 assign cio_gpio_gpio_p2d[8] = mio_p2d[MioInGpioGpio8];
Tests: T4 T22 T37
3077 1/1 assign cio_gpio_gpio_p2d[9] = mio_p2d[MioInGpioGpio9];
Tests: T4 T37 T51
3078 1/1 assign cio_gpio_gpio_p2d[10] = mio_p2d[MioInGpioGpio10];
Tests: T4 T37 T51
3079 1/1 assign cio_gpio_gpio_p2d[11] = mio_p2d[MioInGpioGpio11];
Tests: T4 T37 T51
3080 1/1 assign cio_gpio_gpio_p2d[12] = mio_p2d[MioInGpioGpio12];
Tests: T4 T37 T51
3081 1/1 assign cio_gpio_gpio_p2d[13] = mio_p2d[MioInGpioGpio13];
Tests: T4 T37 T51
3082 1/1 assign cio_gpio_gpio_p2d[14] = mio_p2d[MioInGpioGpio14];
Tests: T4 T37 T51
3083 1/1 assign cio_gpio_gpio_p2d[15] = mio_p2d[MioInGpioGpio15];
Tests: T4 T37 T51
3084 1/1 assign cio_gpio_gpio_p2d[16] = mio_p2d[MioInGpioGpio16];
Tests: T4 T37 T51
3085 1/1 assign cio_gpio_gpio_p2d[17] = mio_p2d[MioInGpioGpio17];
Tests: T4 T37 T51
3086 1/1 assign cio_gpio_gpio_p2d[18] = mio_p2d[MioInGpioGpio18];
Tests: T4 T37 T51
3087 1/1 assign cio_gpio_gpio_p2d[19] = mio_p2d[MioInGpioGpio19];
Tests: T4 T37 T51
3088 1/1 assign cio_gpio_gpio_p2d[20] = mio_p2d[MioInGpioGpio20];
Tests: T4 T37 T51
3089 1/1 assign cio_gpio_gpio_p2d[21] = mio_p2d[MioInGpioGpio21];
Tests: T4 T37 T51
3090 1/1 assign cio_gpio_gpio_p2d[22] = mio_p2d[MioInGpioGpio22];
Tests: T2 T3 T4
3091 1/1 assign cio_gpio_gpio_p2d[23] = mio_p2d[MioInGpioGpio23];
Tests: T2 T3 T4
3092 1/1 assign cio_gpio_gpio_p2d[24] = mio_p2d[MioInGpioGpio24];
Tests: T2 T3 T4
3093 1/1 assign cio_gpio_gpio_p2d[25] = mio_p2d[MioInGpioGpio25];
Tests: T4 T37 T51
3094 1/1 assign cio_gpio_gpio_p2d[26] = mio_p2d[MioInGpioGpio26];
Tests: T4 T37 T51
3095 1/1 assign cio_gpio_gpio_p2d[27] = mio_p2d[MioInGpioGpio27];
Tests: T4 T37 T51
3096 1/1 assign cio_gpio_gpio_p2d[28] = mio_p2d[MioInGpioGpio28];
Tests: T4 T37 T51
3097 1/1 assign cio_gpio_gpio_p2d[29] = mio_p2d[MioInGpioGpio29];
Tests: T4 T37 T51
3098 1/1 assign cio_gpio_gpio_p2d[30] = mio_p2d[MioInGpioGpio30];
Tests: T4 T37 T51
3099 1/1 assign cio_gpio_gpio_p2d[31] = mio_p2d[MioInGpioGpio31];
Tests: T4 T37 T51
3100 1/1 assign cio_i2c0_sda_p2d = mio_p2d[MioInI2c0Sda];
Tests: T53 T54 T55
3101 1/1 assign cio_i2c0_scl_p2d = mio_p2d[MioInI2c0Scl];
Tests: T53 T54 T55
3102 1/1 assign cio_i2c1_sda_p2d = mio_p2d[MioInI2c1Sda];
Tests: T56 T9 T57
3103 1/1 assign cio_i2c1_scl_p2d = mio_p2d[MioInI2c1Scl];
Tests: T56 T9 T57
3104 1/1 assign cio_i2c2_sda_p2d = mio_p2d[MioInI2c2Sda];
Tests: T58 T9 T59
3105 1/1 assign cio_i2c2_scl_p2d = mio_p2d[MioInI2c2Scl];
Tests: T58 T9 T59
3106 1/1 assign cio_spi_host1_sd_p2d[0] = mio_p2d[MioInSpiHost1Sd0];
Tests: T25 T9 T44
3107 1/1 assign cio_spi_host1_sd_p2d[1] = mio_p2d[MioInSpiHost1Sd1];
Tests: T25 T9 T44
3108 1/1 assign cio_spi_host1_sd_p2d[2] = mio_p2d[MioInSpiHost1Sd2];
Tests: T25 T9 T44
3109 1/1 assign cio_spi_host1_sd_p2d[3] = mio_p2d[MioInSpiHost1Sd3];
Tests: T3 T8 T25
3110 1/1 assign cio_uart0_rx_p2d = mio_p2d[MioInUart0Rx];
Tests: T1 T2 T3
3111 1/1 assign cio_uart1_rx_p2d = mio_p2d[MioInUart1Rx];
Tests: T1 T2 T3
3112 1/1 assign cio_uart2_rx_p2d = mio_p2d[MioInUart2Rx];
Tests: T23 T9 T60
3113 1/1 assign cio_uart3_rx_p2d = mio_p2d[MioInUart3Rx];
Tests: T34 T9 T61
3114 1/1 assign cio_spi_device_tpm_csb_p2d = mio_p2d[MioInSpiDeviceTpmCsb];
Tests: T11 T43 T16
3115 1/1 assign cio_flash_ctrl_tck_p2d = mio_p2d[MioInFlashCtrlTck];
Tests: T16 T17 T18
3116 1/1 assign cio_flash_ctrl_tms_p2d = mio_p2d[MioInFlashCtrlTms];
Tests: T16 T17 T18
3117 1/1 assign cio_flash_ctrl_tdi_p2d = mio_p2d[MioInFlashCtrlTdi];
Tests: T62 T16 T17
3118 1/1 assign cio_sysrst_ctrl_aon_ac_present_p2d = mio_p2d[MioInSysrstCtrlAonAcPresent];
Tests: T26 T63 T36
3119 1/1 assign cio_sysrst_ctrl_aon_key0_in_p2d = mio_p2d[MioInSysrstCtrlAonKey0In];
Tests: T64 T26 T65
3120 1/1 assign cio_sysrst_ctrl_aon_key1_in_p2d = mio_p2d[MioInSysrstCtrlAonKey1In];
Tests: T26 T63 T12
3121 1/1 assign cio_sysrst_ctrl_aon_key2_in_p2d = mio_p2d[MioInSysrstCtrlAonKey2In];
Tests: T26 T63 T12
3122 1/1 assign cio_sysrst_ctrl_aon_pwrb_in_p2d = mio_p2d[MioInSysrstCtrlAonPwrbIn];
Tests: T26 T63 T12
3123 1/1 assign cio_sysrst_ctrl_aon_lid_open_p2d = mio_p2d[MioInSysrstCtrlAonLidOpen];
Tests: T26 T15 T36
3124 1/1 assign cio_usbdev_sense_p2d = mio_p2d[MioInUsbdevSense];
Tests: T5 T6 T7
3125
3126 // All muxed outputs
3127 1/1 assign mio_d2p[MioOutGpioGpio0] = cio_gpio_gpio_d2p[0];
Tests: T4 T22 T37
3128 1/1 assign mio_d2p[MioOutGpioGpio1] = cio_gpio_gpio_d2p[1];
Tests: T4 T22 T37
3129 1/1 assign mio_d2p[MioOutGpioGpio2] = cio_gpio_gpio_d2p[2];
Tests: T4 T22 T118
3130 1/1 assign mio_d2p[MioOutGpioGpio3] = cio_gpio_gpio_d2p[3];
Tests: T4 T22 T37
3131 1/1 assign mio_d2p[MioOutGpioGpio4] = cio_gpio_gpio_d2p[4];
Tests: T4 T22 T37
3132 1/1 assign mio_d2p[MioOutGpioGpio5] = cio_gpio_gpio_d2p[5];
Tests: T4 T22 T37
3133 1/1 assign mio_d2p[MioOutGpioGpio6] = cio_gpio_gpio_d2p[6];
Tests: T4 T22 T37
3134 1/1 assign mio_d2p[MioOutGpioGpio7] = cio_gpio_gpio_d2p[7];
Tests: T4 T22 T37
3135 1/1 assign mio_d2p[MioOutGpioGpio8] = cio_gpio_gpio_d2p[8];
Tests: T4 T37 T51
3136 1/1 assign mio_d2p[MioOutGpioGpio9] = cio_gpio_gpio_d2p[9];
Tests: T4 T37 T51
3137 1/1 assign mio_d2p[MioOutGpioGpio10] = cio_gpio_gpio_d2p[10];
Tests: T4 T37 T51
3138 1/1 assign mio_d2p[MioOutGpioGpio11] = cio_gpio_gpio_d2p[11];
Tests: T4 T37 T51
3139 1/1 assign mio_d2p[MioOutGpioGpio12] = cio_gpio_gpio_d2p[12];
Tests: T4 T37 T51
3140 1/1 assign mio_d2p[MioOutGpioGpio13] = cio_gpio_gpio_d2p[13];
Tests: T4 T37 T51
3141 1/1 assign mio_d2p[MioOutGpioGpio14] = cio_gpio_gpio_d2p[14];
Tests: T4 T37 T51
3142 1/1 assign mio_d2p[MioOutGpioGpio15] = cio_gpio_gpio_d2p[15];
Tests: T4 T37 T51
3143 1/1 assign mio_d2p[MioOutGpioGpio16] = cio_gpio_gpio_d2p[16];
Tests: T4 T37 T51
3144 1/1 assign mio_d2p[MioOutGpioGpio17] = cio_gpio_gpio_d2p[17];
Tests: T4 T37 T51
3145 1/1 assign mio_d2p[MioOutGpioGpio18] = cio_gpio_gpio_d2p[18];
Tests: T4 T37 T51
3146 1/1 assign mio_d2p[MioOutGpioGpio19] = cio_gpio_gpio_d2p[19];
Tests: T4 T37 T51
3147 1/1 assign mio_d2p[MioOutGpioGpio20] = cio_gpio_gpio_d2p[20];
Tests: T4 T37 T51
3148 1/1 assign mio_d2p[MioOutGpioGpio21] = cio_gpio_gpio_d2p[21];
Tests: T4 T37 T51
3149 1/1 assign mio_d2p[MioOutGpioGpio22] = cio_gpio_gpio_d2p[22];
Tests: T4 T37 T51
3150 1/1 assign mio_d2p[MioOutGpioGpio23] = cio_gpio_gpio_d2p[23];
Tests: T4 T37 T51
3151 1/1 assign mio_d2p[MioOutGpioGpio24] = cio_gpio_gpio_d2p[24];
Tests: T4 T37 T51
3152 1/1 assign mio_d2p[MioOutGpioGpio25] = cio_gpio_gpio_d2p[25];
Tests: T4 T37 T51
3153 1/1 assign mio_d2p[MioOutGpioGpio26] = cio_gpio_gpio_d2p[26];
Tests: T4 T37 T51
3154 1/1 assign mio_d2p[MioOutGpioGpio27] = cio_gpio_gpio_d2p[27];
Tests: T4 T37 T51
3155 1/1 assign mio_d2p[MioOutGpioGpio28] = cio_gpio_gpio_d2p[28];
Tests: T4 T37 T51
3156 1/1 assign mio_d2p[MioOutGpioGpio29] = cio_gpio_gpio_d2p[29];
Tests: T4 T37 T51
3157 1/1 assign mio_d2p[MioOutGpioGpio30] = cio_gpio_gpio_d2p[30];
Tests: T4 T37 T51
3158 1/1 assign mio_d2p[MioOutGpioGpio31] = cio_gpio_gpio_d2p[31];
Tests: T4 T37 T51
3159 unreachable assign mio_d2p[MioOutI2c0Sda] = cio_i2c0_sda_d2p;
3160 unreachable assign mio_d2p[MioOutI2c0Scl] = cio_i2c0_scl_d2p;
3161 unreachable assign mio_d2p[MioOutI2c1Sda] = cio_i2c1_sda_d2p;
3162 unreachable assign mio_d2p[MioOutI2c1Scl] = cio_i2c1_scl_d2p;
3163 unreachable assign mio_d2p[MioOutI2c2Sda] = cio_i2c2_sda_d2p;
3164 unreachable assign mio_d2p[MioOutI2c2Scl] = cio_i2c2_scl_d2p;
3165 1/1 assign mio_d2p[MioOutSpiHost1Sd0] = cio_spi_host1_sd_d2p[0];
Tests: T25
3166 1/1 assign mio_d2p[MioOutSpiHost1Sd1] = cio_spi_host1_sd_d2p[1];
Tests: T9 T44 T119
3167 0/1 ==> assign mio_d2p[MioOutSpiHost1Sd2] = cio_spi_host1_sd_d2p[2];
3168 1/1 assign mio_d2p[MioOutSpiHost1Sd3] = cio_spi_host1_sd_d2p[3];
Tests: T9 T44 T119
3169 1/1 assign mio_d2p[MioOutUart0Tx] = cio_uart0_tx_d2p;
Tests: T120 T121 T48
3170 1/1 assign mio_d2p[MioOutUart1Tx] = cio_uart1_tx_d2p;
Tests: T24 T122 T123
3171 1/1 assign mio_d2p[MioOutUart2Tx] = cio_uart2_tx_d2p;
Tests: T23 T60 T124
3172 1/1 assign mio_d2p[MioOutUart3Tx] = cio_uart3_tx_d2p;
Tests: T34 T61 T125
3173 1/1 assign mio_d2p[MioOutPattgenPda0Tx] = cio_pattgen_pda0_tx_d2p;
Tests: T27 T9 T126
3174 1/1 assign mio_d2p[MioOutPattgenPcl0Tx] = cio_pattgen_pcl0_tx_d2p;
Tests: T27 T9 T126
3175 1/1 assign mio_d2p[MioOutPattgenPda1Tx] = cio_pattgen_pda1_tx_d2p;
Tests: T9 T44 T119
3176 1/1 assign mio_d2p[MioOutPattgenPcl1Tx] = cio_pattgen_pcl1_tx_d2p;
Tests: T9 T44 T119
3177 1/1 assign mio_d2p[MioOutSpiHost1Sck] = cio_spi_host1_sck_d2p;
Tests: T25 T9 T44
3178 1/1 assign mio_d2p[MioOutSpiHost1Csb] = cio_spi_host1_csb_d2p;
Tests: T25 T9 T44
3179 0/1 ==> assign mio_d2p[MioOutFlashCtrlTdo] = cio_flash_ctrl_tdo_d2p;
3180 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut0] = cio_sensor_ctrl_aon_ast_debug_out_d2p[0];
3181 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut1] = cio_sensor_ctrl_aon_ast_debug_out_d2p[1];
3182 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut2] = cio_sensor_ctrl_aon_ast_debug_out_d2p[2];
3183 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut3] = cio_sensor_ctrl_aon_ast_debug_out_d2p[3];
3184 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut4] = cio_sensor_ctrl_aon_ast_debug_out_d2p[4];
3185 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut5] = cio_sensor_ctrl_aon_ast_debug_out_d2p[5];
3186 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut6] = cio_sensor_ctrl_aon_ast_debug_out_d2p[6];
3187 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut7] = cio_sensor_ctrl_aon_ast_debug_out_d2p[7];
3188 unreachable assign mio_d2p[MioOutSensorCtrlAonAstDebugOut8] = cio_sensor_ctrl_aon_ast_debug_out_d2p[8];
3189 1/1 assign mio_d2p[MioOutPwmAonPwm0] = cio_pwm_aon_pwm_d2p[0];
Tests: T28 T32 T118
3190 1/1 assign mio_d2p[MioOutPwmAonPwm1] = cio_pwm_aon_pwm_d2p[1];
Tests: T28 T32 T118
3191 1/1 assign mio_d2p[MioOutPwmAonPwm2] = cio_pwm_aon_pwm_d2p[2];
Tests: T28 T118 T127
3192 1/1 assign mio_d2p[MioOutPwmAonPwm3] = cio_pwm_aon_pwm_d2p[3];
Tests: T28 T118 T127
3193 1/1 assign mio_d2p[MioOutPwmAonPwm4] = cio_pwm_aon_pwm_d2p[4];
Tests: T28 T118 T127
3194 1/1 assign mio_d2p[MioOutPwmAonPwm5] = cio_pwm_aon_pwm_d2p[5];
Tests: T28 T32 T118
3195 0/1 ==> assign mio_d2p[MioOutOtpCtrlTest0] = cio_otp_ctrl_test_d2p[0];
3196 1/1 assign mio_d2p[MioOutSysrstCtrlAonBatDisable] = cio_sysrst_ctrl_aon_bat_disable_d2p;
Tests: T64 T65 T128
3197 1/1 assign mio_d2p[MioOutSysrstCtrlAonKey0Out] = cio_sysrst_ctrl_aon_key0_out_d2p;
Tests: T64 T26 T65
3198 1/1 assign mio_d2p[MioOutSysrstCtrlAonKey1Out] = cio_sysrst_ctrl_aon_key1_out_d2p;
Tests: T26 T63 T12
3199 1/1 assign mio_d2p[MioOutSysrstCtrlAonKey2Out] = cio_sysrst_ctrl_aon_key2_out_d2p;
Tests: T26 T63 T12
3200 1/1 assign mio_d2p[MioOutSysrstCtrlAonPwrbOut] = cio_sysrst_ctrl_aon_pwrb_out_d2p;
Tests: T26 T63 T12
3201 1/1 assign mio_d2p[MioOutSysrstCtrlAonZ3Wakeup] = cio_sysrst_ctrl_aon_z3_wakeup_d2p;
Tests: T15 T12 T13
3202
3203 // All muxed output enables
3204 1/1 assign mio_en_d2p[MioOutGpioGpio0] = cio_gpio_gpio_en_d2p[0];
Tests: T1 T4 T22
3205 1/1 assign mio_en_d2p[MioOutGpioGpio1] = cio_gpio_gpio_en_d2p[1];
Tests: T4 T22 T37
3206 1/1 assign mio_en_d2p[MioOutGpioGpio2] = cio_gpio_gpio_en_d2p[2];
Tests: T4 T22 T118
3207 1/1 assign mio_en_d2p[MioOutGpioGpio3] = cio_gpio_gpio_en_d2p[3];
Tests: T4 T22 T37
3208 1/1 assign mio_en_d2p[MioOutGpioGpio4] = cio_gpio_gpio_en_d2p[4];
Tests: T4 T22 T37
3209 1/1 assign mio_en_d2p[MioOutGpioGpio5] = cio_gpio_gpio_en_d2p[5];
Tests: T4 T22 T37
3210 1/1 assign mio_en_d2p[MioOutGpioGpio6] = cio_gpio_gpio_en_d2p[6];
Tests: T4 T22 T37
3211 1/1 assign mio_en_d2p[MioOutGpioGpio7] = cio_gpio_gpio_en_d2p[7];
Tests: T4 T22 T37
3212 1/1 assign mio_en_d2p[MioOutGpioGpio8] = cio_gpio_gpio_en_d2p[8];
Tests: T4 T37 T51
3213 1/1 assign mio_en_d2p[MioOutGpioGpio9] = cio_gpio_gpio_en_d2p[9];
Tests: T4 T37 T51
3214 1/1 assign mio_en_d2p[MioOutGpioGpio10] = cio_gpio_gpio_en_d2p[10];
Tests: T4 T37 T51
3215 1/1 assign mio_en_d2p[MioOutGpioGpio11] = cio_gpio_gpio_en_d2p[11];
Tests: T4 T37 T51
3216 1/1 assign mio_en_d2p[MioOutGpioGpio12] = cio_gpio_gpio_en_d2p[12];
Tests: T4 T37 T51
3217 1/1 assign mio_en_d2p[MioOutGpioGpio13] = cio_gpio_gpio_en_d2p[13];
Tests: T4 T37 T51
3218 1/1 assign mio_en_d2p[MioOutGpioGpio14] = cio_gpio_gpio_en_d2p[14];
Tests: T4 T37 T51
3219 1/1 assign mio_en_d2p[MioOutGpioGpio15] = cio_gpio_gpio_en_d2p[15];
Tests: T4 T37 T51
3220 1/1 assign mio_en_d2p[MioOutGpioGpio16] = cio_gpio_gpio_en_d2p[16];
Tests: T4 T37 T51
3221 1/1 assign mio_en_d2p[MioOutGpioGpio17] = cio_gpio_gpio_en_d2p[17];
Tests: T4 T37 T51
3222 1/1 assign mio_en_d2p[MioOutGpioGpio18] = cio_gpio_gpio_en_d2p[18];
Tests: T4 T37 T51
3223 1/1 assign mio_en_d2p[MioOutGpioGpio19] = cio_gpio_gpio_en_d2p[19];
Tests: T4 T37 T51
3224 1/1 assign mio_en_d2p[MioOutGpioGpio20] = cio_gpio_gpio_en_d2p[20];
Tests: T4 T37 T51
3225 1/1 assign mio_en_d2p[MioOutGpioGpio21] = cio_gpio_gpio_en_d2p[21];
Tests: T4 T37 T51
3226 1/1 assign mio_en_d2p[MioOutGpioGpio22] = cio_gpio_gpio_en_d2p[22];
Tests: T4 T37 T51
3227 1/1 assign mio_en_d2p[MioOutGpioGpio23] = cio_gpio_gpio_en_d2p[23];
Tests: T4 T37 T51
3228 1/1 assign mio_en_d2p[MioOutGpioGpio24] = cio_gpio_gpio_en_d2p[24];
Tests: T4 T37 T51
3229 1/1 assign mio_en_d2p[MioOutGpioGpio25] = cio_gpio_gpio_en_d2p[25];
Tests: T4 T37 T51
3230 1/1 assign mio_en_d2p[MioOutGpioGpio26] = cio_gpio_gpio_en_d2p[26];
Tests: T4 T37 T51
3231 1/1 assign mio_en_d2p[MioOutGpioGpio27] = cio_gpio_gpio_en_d2p[27];
Tests: T4 T37 T51
3232 1/1 assign mio_en_d2p[MioOutGpioGpio28] = cio_gpio_gpio_en_d2p[28];
Tests: T4 T37 T51
3233 1/1 assign mio_en_d2p[MioOutGpioGpio29] = cio_gpio_gpio_en_d2p[29];
Tests: T4 T37 T51
3234 1/1 assign mio_en_d2p[MioOutGpioGpio30] = cio_gpio_gpio_en_d2p[30];
Tests: T4 T37 T51
3235 1/1 assign mio_en_d2p[MioOutGpioGpio31] = cio_gpio_gpio_en_d2p[31];
Tests: T4 T37 T51
3236 1/1 assign mio_en_d2p[MioOutI2c0Sda] = cio_i2c0_sda_en_d2p;
Tests: T53 T54 T55
3237 1/1 assign mio_en_d2p[MioOutI2c0Scl] = cio_i2c0_scl_en_d2p;
Tests: T54 T55 T9
3238 1/1 assign mio_en_d2p[MioOutI2c1Sda] = cio_i2c1_sda_en_d2p;
Tests: T56 T9 T57
3239 1/1 assign mio_en_d2p[MioOutI2c1Scl] = cio_i2c1_scl_en_d2p;
Tests: T56 T9 T57
3240 1/1 assign mio_en_d2p[MioOutI2c2Sda] = cio_i2c2_sda_en_d2p;
Tests: T58 T9 T59
3241 1/1 assign mio_en_d2p[MioOutI2c2Scl] = cio_i2c2_scl_en_d2p;
Tests: T58 T9 T59
3242 1/1 assign mio_en_d2p[MioOutSpiHost1Sd0] = cio_spi_host1_sd_en_d2p[0];
Tests: T25 T9 T44
3243 1/1 assign mio_en_d2p[MioOutSpiHost1Sd1] = cio_spi_host1_sd_en_d2p[1];
Tests: T9 T44 T119
3244 1/1 assign mio_en_d2p[MioOutSpiHost1Sd2] = cio_spi_host1_sd_en_d2p[2];
Tests: T9 T44 T119
3245 1/1 assign mio_en_d2p[MioOutSpiHost1Sd3] = cio_spi_host1_sd_en_d2p[3];
Tests: T9 T44 T119
3246 unreachable assign mio_en_d2p[MioOutUart0Tx] = cio_uart0_tx_en_d2p;
3247 unreachable assign mio_en_d2p[MioOutUart1Tx] = cio_uart1_tx_en_d2p;
3248 unreachable assign mio_en_d2p[MioOutUart2Tx] = cio_uart2_tx_en_d2p;
3249 unreachable assign mio_en_d2p[MioOutUart3Tx] = cio_uart3_tx_en_d2p;
3250 unreachable assign mio_en_d2p[MioOutPattgenPda0Tx] = cio_pattgen_pda0_tx_en_d2p;
3251 unreachable assign mio_en_d2p[MioOutPattgenPcl0Tx] = cio_pattgen_pcl0_tx_en_d2p;
3252 unreachable assign mio_en_d2p[MioOutPattgenPda1Tx] = cio_pattgen_pda1_tx_en_d2p;
3253 unreachable assign mio_en_d2p[MioOutPattgenPcl1Tx] = cio_pattgen_pcl1_tx_en_d2p;
3254 1/1 assign mio_en_d2p[MioOutSpiHost1Sck] = cio_spi_host1_sck_en_d2p;
Tests: T25 T9 T44
3255 1/1 assign mio_en_d2p[MioOutSpiHost1Csb] = cio_spi_host1_csb_en_d2p;
Tests: T25 T9 T44
3256 0/1 ==> assign mio_en_d2p[MioOutFlashCtrlTdo] = cio_flash_ctrl_tdo_en_d2p;
3257 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut0] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[0];
3258 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut1] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[1];
3259 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut2] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[2];
3260 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut3] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[3];
3261 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut4] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[4];
3262 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut5] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[5];
3263 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut6] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[6];
3264 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut7] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[7];
3265 unreachable assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut8] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[8];
3266 unreachable assign mio_en_d2p[MioOutPwmAonPwm0] = cio_pwm_aon_pwm_en_d2p[0];
3267 unreachable assign mio_en_d2p[MioOutPwmAonPwm1] = cio_pwm_aon_pwm_en_d2p[1];
3268 unreachable assign mio_en_d2p[MioOutPwmAonPwm2] = cio_pwm_aon_pwm_en_d2p[2];
3269 unreachable assign mio_en_d2p[MioOutPwmAonPwm3] = cio_pwm_aon_pwm_en_d2p[3];
3270 unreachable assign mio_en_d2p[MioOutPwmAonPwm4] = cio_pwm_aon_pwm_en_d2p[4];
3271 unreachable assign mio_en_d2p[MioOutPwmAonPwm5] = cio_pwm_aon_pwm_en_d2p[5];
3272 1/1 assign mio_en_d2p[MioOutOtpCtrlTest0] = cio_otp_ctrl_test_en_d2p[0];
Tests: T1 T2 T3
3273 unreachable assign mio_en_d2p[MioOutSysrstCtrlAonBatDisable] = cio_sysrst_ctrl_aon_bat_disable_en_d2p;
3274 unreachable assign mio_en_d2p[MioOutSysrstCtrlAonKey0Out] = cio_sysrst_ctrl_aon_key0_out_en_d2p;
3275 unreachable assign mio_en_d2p[MioOutSysrstCtrlAonKey1Out] = cio_sysrst_ctrl_aon_key1_out_en_d2p;
3276 unreachable assign mio_en_d2p[MioOutSysrstCtrlAonKey2Out] = cio_sysrst_ctrl_aon_key2_out_en_d2p;
3277 unreachable assign mio_en_d2p[MioOutSysrstCtrlAonPwrbOut] = cio_sysrst_ctrl_aon_pwrb_out_en_d2p;
3278 unreachable assign mio_en_d2p[MioOutSysrstCtrlAonZ3Wakeup] = cio_sysrst_ctrl_aon_z3_wakeup_en_d2p;
3279
3280 // All dedicated inputs
3281 logic [15:0] unused_dio_p2d;
3282 1/1 assign unused_dio_p2d = dio_p2d;
Tests: T1 T3 T11
3283 1/1 assign cio_usbdev_usb_dp_p2d = dio_p2d[DioUsbdevUsbDp];
Tests: T5 T6 T7
3284 1/1 assign cio_usbdev_usb_dn_p2d = dio_p2d[DioUsbdevUsbDn];
Tests: T5 T6 T7
3285 1/1 assign cio_spi_host0_sd_p2d[0] = dio_p2d[DioSpiHost0Sd0];
Tests: T3 T8 T10
3286 1/1 assign cio_spi_host0_sd_p2d[1] = dio_p2d[DioSpiHost0Sd1];
Tests: T3 T8 T10
3287 1/1 assign cio_spi_host0_sd_p2d[2] = dio_p2d[DioSpiHost0Sd2];
Tests: T3 T8 T10
3288 1/1 assign cio_spi_host0_sd_p2d[3] = dio_p2d[DioSpiHost0Sd3];
Tests: T3 T8 T10
3289 1/1 assign cio_spi_device_sd_p2d[0] = dio_p2d[DioSpiDeviceSd0];
Tests: T1 T3 T11
3290 1/1 assign cio_spi_device_sd_p2d[1] = dio_p2d[DioSpiDeviceSd1];
Tests: T1 T3 T11
3291 1/1 assign cio_spi_device_sd_p2d[2] = dio_p2d[DioSpiDeviceSd2];
Tests: T1 T3 T11
3292 1/1 assign cio_spi_device_sd_p2d[3] = dio_p2d[DioSpiDeviceSd3];
Tests: T1 T3 T11
3293 1/1 assign cio_sysrst_ctrl_aon_ec_rst_l_p2d = dio_p2d[DioSysrstCtrlAonEcRstL];
Tests: T19 T26 T63
3294 1/1 assign cio_sysrst_ctrl_aon_flash_wp_l_p2d = dio_p2d[DioSysrstCtrlAonFlashWpL];
Tests: T19 T26 T15
3295 1/1 assign cio_spi_device_sck_p2d = dio_p2d[DioSpiDeviceSck];
Tests: T1 T3 T11
3296 1/1 assign cio_spi_device_csb_p2d = dio_p2d[DioSpiDeviceCsb];
Tests: T1 T3 T8
3297
3298 // All dedicated outputs
3299 1/1 assign dio_d2p[DioUsbdevUsbDp] = cio_usbdev_usb_dp_d2p;
Tests: T5 T6 T7
3300 1/1 assign dio_d2p[DioUsbdevUsbDn] = cio_usbdev_usb_dn_d2p;
Tests: T5 T6 T7
3301 1/1 assign dio_d2p[DioSpiHost0Sd0] = cio_spi_host0_sd_d2p[0];
Tests: T3 T8 T9
3302 1/1 assign dio_d2p[DioSpiHost0Sd1] = cio_spi_host0_sd_d2p[1];
Tests: T3 T8 T9
3303 1/1 assign dio_d2p[DioSpiHost0Sd2] = cio_spi_host0_sd_d2p[2];
Tests: T3 T8 T9
3304 1/1 assign dio_d2p[DioSpiHost0Sd3] = cio_spi_host0_sd_d2p[3];
Tests: T3 T8 T9
3305 1/1 assign dio_d2p[DioSpiDeviceSd0] = cio_spi_device_sd_d2p[0];
Tests: T3 T8 T9
3306 1/1 assign dio_d2p[DioSpiDeviceSd1] = cio_spi_device_sd_d2p[1];
Tests: T3 T11 T8
3307 1/1 assign dio_d2p[DioSpiDeviceSd2] = cio_spi_device_sd_d2p[2];
Tests: T3 T8 T9
3308 1/1 assign dio_d2p[DioSpiDeviceSd3] = cio_spi_device_sd_d2p[3];
Tests: T3 T8 T9
3309 1/1 assign dio_d2p[DioSysrstCtrlAonEcRstL] = cio_sysrst_ctrl_aon_ec_rst_l_d2p;
Tests: T12 T13 T36
3310 1/1 assign dio_d2p[DioSysrstCtrlAonFlashWpL] = cio_sysrst_ctrl_aon_flash_wp_l_d2p;
Tests: T15 T12 T13
3311 assign dio_d2p[DioSpiDeviceSck] = 1'b0;
3312 assign dio_d2p[DioSpiDeviceCsb] = 1'b0;
3313 1/1 assign dio_d2p[DioSpiHost0Sck] = cio_spi_host0_sck_d2p;
Tests: T3 T8 T9
3314 1/1 assign dio_d2p[DioSpiHost0Csb] = cio_spi_host0_csb_d2p;
Tests: T3 T8 T9
3315
3316 // All dedicated output enables
3317 1/1 assign dio_en_d2p[DioUsbdevUsbDp] = cio_usbdev_usb_dp_en_d2p;
Tests: T6 T7 T35
3318 1/1 assign dio_en_d2p[DioUsbdevUsbDn] = cio_usbdev_usb_dn_en_d2p;
Tests: T6 T7 T35
3319 1/1 assign dio_en_d2p[DioSpiHost0Sd0] = cio_spi_host0_sd_en_d2p[0];
Tests: T3 T8 T9
3320 0/1 ==> assign dio_en_d2p[DioSpiHost0Sd1] = cio_spi_host0_sd_en_d2p[1];
3321 0/1 ==> assign dio_en_d2p[DioSpiHost0Sd2] = cio_spi_host0_sd_en_d2p[2];
3322 0/1 ==> assign dio_en_d2p[DioSpiHost0Sd3] = cio_spi_host0_sd_en_d2p[3];
3323 1/1 assign dio_en_d2p[DioSpiDeviceSd0] = cio_spi_device_sd_en_d2p[0];
Tests: T3 T10 T9
3324 1/1 assign dio_en_d2p[DioSpiDeviceSd1] = cio_spi_device_sd_en_d2p[1];
Tests: T3 T11 T8
3325 1/1 assign dio_en_d2p[DioSpiDeviceSd2] = cio_spi_device_sd_en_d2p[2];
Tests: T3 T10 T9
3326 1/1 assign dio_en_d2p[DioSpiDeviceSd3] = cio_spi_device_sd_en_d2p[3];
Tests: T3 T10 T9
3327 unreachable assign dio_en_d2p[DioSysrstCtrlAonEcRstL] = cio_sysrst_ctrl_aon_ec_rst_l_en_d2p;
3328 unreachable assign dio_en_d2p[DioSysrstCtrlAonFlashWpL] = cio_sysrst_ctrl_aon_flash_wp_l_en_d2p;
3329 assign dio_en_d2p[DioSpiDeviceSck] = 1'b0;
3330 assign dio_en_d2p[DioSpiDeviceCsb] = 1'b0;
3331 1/1 assign dio_en_d2p[DioSpiHost0Sck] = cio_spi_host0_sck_en_d2p;
Tests: T3 T8 T9
3332 1/1 assign dio_en_d2p[DioSpiHost0Csb] = cio_spi_host0_csb_en_d2p;
Tests: T3 T8 T9