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 LINE       16856
 SUB-EXPRESSION (addr_hit[91] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T53,T311,T168
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[92] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T56,T311,T57
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[93] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T56,T311,T57
1	1	Covered	T379,T519,T159

 LINE       16856
 SUB-EXPRESSION (addr_hit[94] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[95] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T56,T311,T57
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[96] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T56,T311,T57
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[97] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T56,T311,T57
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[98] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T56,T311,T57
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[99] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T56,T311,T57
1	1	Covered	T379,T519,T159

 LINE       16856
 SUB-EXPRESSION (addr_hit[100] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[101] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T56,T311,T57
1	1	Covered	T379,T520,T383

 LINE       16856
 SUB-EXPRESSION (addr_hit[102] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T312,T168
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[103] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[104] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T312,T168
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[105] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T312,T168
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[106] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T312,T168
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[107] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T58,T311,T59
1	1	Covered	T379,T519,T520

 LINE       16856
 SUB-EXPRESSION (addr_hit[108] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T58,T311,T59
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[109] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[110] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T58,T311,T59
1	1	Covered	T379,T519,T371

 LINE       16856
 SUB-EXPRESSION (addr_hit[111] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T58,T311,T59
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[112] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T58,T311,T59
1	1	Covered	T379,T519,T159

 LINE       16856
 SUB-EXPRESSION (addr_hit[113] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T58,T311,T59
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[114] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T58,T311,T59
1	1	Covered	T379,T519,T520

 LINE       16856
 SUB-EXPRESSION (addr_hit[115] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[116] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T58,T311,T59
1	1	Covered	T379,T519,T520

 LINE       16856
 SUB-EXPRESSION (addr_hit[117] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[118] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[119] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T520

 LINE       16856
 SUB-EXPRESSION (addr_hit[120] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[121] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[122] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T27,T311,T126
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[123] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T27,T311,T126
1	1	Covered	T379,T519,T159

 LINE       16856
 SUB-EXPRESSION (addr_hit[124] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T520

 LINE       16856
 SUB-EXPRESSION (addr_hit[125] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[126] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[127] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T39,T75,T76
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[128] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T39,T75,T76
1	1	Covered	T379,T519,T520

 LINE       16856
 SUB-EXPRESSION (addr_hit[129] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T39,T75,T76
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[130] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T39,T75,T76
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[131] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T8,T311
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[132] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T8,T311
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[133] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[134] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T159

 LINE       16856
 SUB-EXPRESSION (addr_hit[135] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T371

 LINE       16856
 SUB-EXPRESSION (addr_hit[136] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[137] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[138] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[139] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[140] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T520

 LINE       16856
 SUB-EXPRESSION (addr_hit[141] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T520

 LINE       16856
 SUB-EXPRESSION (addr_hit[142] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T371

 LINE       16856
 SUB-EXPRESSION (addr_hit[143] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[144] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[145] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[146] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[147] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T520

 LINE       16856
 SUB-EXPRESSION (addr_hit[148] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[149] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T371

 LINE       16856
 SUB-EXPRESSION (addr_hit[150] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[151] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[152] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[153] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T22,T19
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[154] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T63,T311,T213
1	1	Covered	T379,T519,T520

 LINE       16856
 SUB-EXPRESSION (addr_hit[155] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T129,T168
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[156] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T39,T75,T76
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[157] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T39,T75,T76
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[158] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T161,T311,T162
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[159] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[160] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T178,T311,T313
1	1	Covered	T519,T153,T159

 LINE       16856
 SUB-EXPRESSION (addr_hit[161] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T178,T311,T313
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[162] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T178,T311,T313
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[163] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T178,T311,T313
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[164] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T178,T311,T313
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[165] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T520

 LINE       16856
 SUB-EXPRESSION (addr_hit[166] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T314,T311,T315
1	1	Covered	T379,T519,T371

 LINE       16856
 SUB-EXPRESSION (addr_hit[167] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T314,T311,T315
1	1	Covered	T379,T519,T520

 LINE       16856
 SUB-EXPRESSION (addr_hit[168] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T371

 LINE       16856
 SUB-EXPRESSION (addr_hit[169] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T159

 LINE       16856
 SUB-EXPRESSION (addr_hit[170] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[171] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[172] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T147,T163,T311
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[173] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[174] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[175] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T316,T311,T168
1	1	Covered	T379,T519,T520

 LINE       16856
 SUB-EXPRESSION (addr_hit[176] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[177] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[178] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[179] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T9,T168
1	1	Covered	T379,T519,T371

 LINE       16856
 SUB-EXPRESSION (addr_hit[180] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T371

 LINE       16856
 SUB-EXPRESSION (addr_hit[181] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T96,T379,T153