Unified Coverage Report :: Cond split page

Go back

 LINE       16856
 SUB-EXPRESSION (addr_hit[182] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T316,T311,T168
1	1	Covered	T519,T520,T383

 LINE       16856
 SUB-EXPRESSION (addr_hit[183] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[184] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T316,T311,T168
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[185] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T311,T168,T251
1	1	Covered	T379,T519,T159

 LINE       16856
 SUB-EXPRESSION (addr_hit[186] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T96,T153,T159
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[187] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T96,T153,T159
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[188] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T96,T153,T159
1	1	Covered	T379,T519,T520

 LINE       16856
 SUB-EXPRESSION (addr_hit[189] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T96,T153,T159
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[190] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T588,T96,T153
1	1	Covered	T379,T519,T520

 LINE       16856
 SUB-EXPRESSION (addr_hit[191] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T96,T153,T159
1	1	Covered	T379,T519,T159

 LINE       16856
 SUB-EXPRESSION (addr_hit[192] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T24,T23,T120
1	1	Covered	T379,T519,T159

 LINE       16856
 SUB-EXPRESSION (addr_hit[193] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T4,T311,T34
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[194] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T3,T4,T11
1	1	Covered	T379,T519,T159

 LINE       16856
 SUB-EXPRESSION (addr_hit[195] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T39,T27,T75
1	1	Covered	T379,T519,T153

 LINE       16856
 SUB-EXPRESSION (addr_hit[196] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T39
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[197] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T178,T147,T316
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[198] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T4,T39
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[199] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T519,T159,T520

 LINE       16856
 SUB-EXPRESSION (addr_hit[200] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T251,T252,T96
1	1	Covered	T96,T379,T519

 LINE       16856
 SUB-EXPRESSION (addr_hit[201] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T69,T70,T246
1	1	Covered	T379,T519,T153

 LINE       17062
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T520,T518,T517
1	1	1	Covered	T251,T96,T153

 LINE       17065
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T515,T521
1	1	1	Covered	T120,T121,T311

 LINE       17068
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T519,T515
1	1	1	Covered	T120,T121,T311

 LINE       17071
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T518,T521
1	1	1	Covered	T120,T121,T311

 LINE       17074
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T515,T518
1	1	1	Covered	T120,T121,T311

 LINE       17077
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T520,T515
1	1	1	Covered	T120,T121,T311

 LINE       17080
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T519,T153
1	1	0	Covered	T519,T515,T521
1	1	1	Covered	T120,T121,T311

 LINE       17083
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T520,T521
1	1	1	Covered	T120,T121,T311

 LINE       17086
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T519,T153
1	1	0	Covered	T379,T519,T520
1	1	1	Covered	T120,T121,T311

 LINE       17089
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T525,T521
1	1	1	Covered	T120,T121,T311

 LINE       17092
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T518,T522
1	1	1	Covered	T24,T311,T122

 LINE       17095
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T516,T528
1	1	1	Covered	T24,T311,T122

 LINE       17098
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T515,T518
1	1	1	Covered	T24,T311,T122

 LINE       17101
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T520,T515
1	1	1	Covered	T24,T311,T122

 LINE       17104
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T519,T153
1	1	0	Covered	T519,T515,T521
1	1	1	Covered	T24,T311,T122

 LINE       17107
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T520,T515,T516
1	1	1	Covered	T24,T311,T122

 LINE       17110
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T519,T515
1	1	1	Covered	T24,T311,T122

 LINE       17113
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T520,T515
1	1	1	Covered	T24,T311,T122

 LINE       17116
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T515,T516
1	1	1	Covered	T24,T311,T122

 LINE       17119
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T515,T518
1	1	1	Covered	T23,T311,T60

 LINE       17122
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T519,T153
1	1	0	Covered	T379,T515,T516
1	1	1	Covered	T23,T311,T60

 LINE       17125
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T515,T522
1	1	1	Covered	T23,T311,T60

 LINE       17128
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T520,T525
1	1	1	Covered	T23,T311,T60

 LINE       17131
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T517,T525,T522
1	1	1	Covered	T23,T311,T60

 LINE       17134
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T515,T516
1	1	1	Covered	T23,T311,T60

 LINE       17137
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T516,T517
1	1	1	Covered	T23,T311,T60

 LINE       17140
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T521,T522
1	1	1	Covered	T23,T311,T60

 LINE       17143
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T520,T516
1	1	1	Covered	T23,T311,T60

 LINE       17146
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T520,T516,T517
1	1	1	Covered	T311,T34,T61

 LINE       17149
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T521,T522
1	1	1	Covered	T311,T34,T61

 LINE       17152
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T520,T515
1	1	1	Covered	T311,T34,T61

 LINE       17155
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T153
1	1	0	Covered	T519,T515,T518
1	1	1	Covered	T311,T34,T61

 LINE       17158
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T520,T518,T517
1	1	1	Covered	T311,T34,T61

 LINE       17161
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T520,T515,T517
1	1	1	Covered	T311,T34,T61

 LINE       17164
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T519,T153
1	1	0	Covered	T519,T520,T518
1	1	1	Covered	T311,T34,T61

 LINE       17167
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T516,T522
1	1	1	Covered	T311,T34,T61

 LINE       17170
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T520,T518
1	1	1	Covered	T311,T34,T61

 LINE       17173
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T520,T517,T521
1	1	1	Covered	T4,T311,T168

 LINE       17176
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T520,T517
1	1	1	Covered	T4,T311,T168

 LINE       17179
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T153
1	1	0	Covered	T379,T519,T515
1	1	1	Covered	T4,T311,T168

 LINE       17182
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T516,T521
1	1	1	Covered	T4,T311,T168

 LINE       17185
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T516,T522
1	1	1	Covered	T4,T311,T168

 LINE       17188
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T517,T521,T522
1	1	1	Covered	T4,T311,T168

 LINE       17191
 EXPRESSION (addr_hit[43] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T521,T528
1	1	1	Covered	T4,T311,T168

 LINE       17194
 EXPRESSION (addr_hit[44] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T520,T516
1	1	1	Covered	T4,T311,T168

 LINE       17197
 EXPRESSION (addr_hit[45] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T516,T535
1	1	1	Covered	T4,T311,T168

 LINE       17200
 EXPRESSION (addr_hit[46] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T519,T153
1	1	0	Covered	T379,T515,T516
1	1	1	Covered	T4,T311,T168

 LINE       17203
 EXPRESSION (addr_hit[47] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T516,T517
1	1	1	Covered	T4,T311,T168

 LINE       17206
 EXPRESSION (addr_hit[48] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T519,T153
1	1	0	Covered	T525,T521,T526
1	1	1	Covered	T4,T311,T168

 LINE       17209
 EXPRESSION (addr_hit[49] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T522,T535
1	1	1	Covered	T4,T311,T168

 LINE       17212
 EXPRESSION (addr_hit[50] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T519,T516
1	1	1	Covered	T4,T311,T168

 LINE       17215
 EXPRESSION (addr_hit[51] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T516,T528
1	1	1	Covered	T4,T311,T168

 LINE       17218
 EXPRESSION (addr_hit[52] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T153
1	1	0	Covered	T519,T520,T516
1	1	1	Covered	T4,T311,T168

 LINE       17221
 EXPRESSION (addr_hit[53] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T515,T525
1	1	1	Covered	T4,T311,T168

 LINE       17224
 EXPRESSION (addr_hit[54] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T519,T153
1	1	0	Covered	T379,T515,T516
1	1	1	Covered	T4,T311,T168