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 LINE       17437
 EXPRESSION (addr_hit[125] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T520,T515,T516
1	1	1	Covered	T311,T168,T251

 LINE       17440
 EXPRESSION (addr_hit[126] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T516,T518
1	1	1	Covered	T311,T168,T251

 LINE       17443
 EXPRESSION (addr_hit[127] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T516,T517
1	1	1	Covered	T39,T75,T76

 LINE       17446
 EXPRESSION (addr_hit[128] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T515,T516
1	1	1	Covered	T39,T75,T76

 LINE       17449
 EXPRESSION (addr_hit[129] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T520,T515,T525
1	1	1	Covered	T39,T75,T76

 LINE       17452
 EXPRESSION (addr_hit[130] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T515,T516
1	1	1	Covered	T39,T75,T76

 LINE       17455
 EXPRESSION (addr_hit[131] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T515,T516
1	1	1	Covered	T3,T8,T311

 LINE       17458
 EXPRESSION (addr_hit[132] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T518,T522
1	1	1	Covered	T3,T8,T311

 LINE       17461
 EXPRESSION (addr_hit[133] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T518,T525
1	1	1	Covered	T311,T168,T251

 LINE       17464
 EXPRESSION (addr_hit[134] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T520,T515,T521
1	1	1	Covered	T311,T168,T251

 LINE       17467
 EXPRESSION (addr_hit[135] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T519,T153
1	1	0	Covered	T379,T519,T520
1	1	1	Covered	T311,T168,T251

 LINE       17470
 EXPRESSION (addr_hit[136] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T519,T153
1	1	0	Covered	T379,T519,T515
1	1	1	Covered	T311,T168,T251

 LINE       17473
 EXPRESSION (addr_hit[137] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T515,T525
1	1	1	Covered	T311,T168,T251

 LINE       17476
 EXPRESSION (addr_hit[138] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T520,T515,T528
1	1	1	Covered	T311,T168,T251

 LINE       17479
 EXPRESSION (addr_hit[139] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T521,T535
1	1	1	Covered	T311,T168,T251

 LINE       17482
 EXPRESSION (addr_hit[140] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T515,T521
1	1	1	Covered	T311,T168,T251

 LINE       17485
 EXPRESSION (addr_hit[141] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T515,T518
1	1	1	Covered	T311,T168,T251

 LINE       17488
 EXPRESSION (addr_hit[142] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T517,T538
1	1	1	Covered	T311,T168,T251

 LINE       17491
 EXPRESSION (addr_hit[143] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T538,T557,T590
1	1	1	Covered	T311,T168,T251

 LINE       17494
 EXPRESSION (addr_hit[144] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T516,T518
1	1	1	Covered	T311,T168,T251

 LINE       17497
 EXPRESSION (addr_hit[145] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T153
1	1	0	Covered	T519,T515,T521
1	1	1	Covered	T311,T168,T251

 LINE       17500
 EXPRESSION (addr_hit[146] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T520,T515
1	1	1	Covered	T311,T168,T251

 LINE       17503
 EXPRESSION (addr_hit[147] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T515,T517
1	1	1	Covered	T311,T168,T251

 LINE       17506
 EXPRESSION (addr_hit[148] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T519,T520
1	1	1	Covered	T311,T168,T251

 LINE       17509
 EXPRESSION (addr_hit[149] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T520,T516,T517
1	1	1	Covered	T311,T168,T251

 LINE       17512
 EXPRESSION (addr_hit[150] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T515,T516
1	1	1	Covered	T311,T168,T251

 LINE       17515
 EXPRESSION (addr_hit[151] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T520,T515,T516
1	1	1	Covered	T311,T168,T251

 LINE       17518
 EXPRESSION (addr_hit[152] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T536,T589
1	1	1	Covered	T311,T168,T251

 LINE       17521
 EXPRESSION (addr_hit[153] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T515,T525
1	1	1	Covered	T1,T22,T19

 LINE       17524
 EXPRESSION (addr_hit[154] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T520,T515
1	1	1	Covered	T63,T311,T213

 LINE       17527
 EXPRESSION (addr_hit[155] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T521,T526
1	1	1	Covered	T311,T129,T168

 LINE       17530
 EXPRESSION (addr_hit[156] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T515,T516
1	1	1	Covered	T39,T75,T76

 LINE       17533
 EXPRESSION (addr_hit[157] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T515,T516
1	1	1	Covered	T39,T75,T76

 LINE       17536
 EXPRESSION (addr_hit[158] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T521,T528
1	1	1	Covered	T161,T311,T162

 LINE       17539
 EXPRESSION (addr_hit[159] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T519,T153
1	1	0	Covered	T379,T520,T515
1	1	1	Covered	T311,T168,T251

 LINE       17542
 EXPRESSION (addr_hit[160] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T519,T153
1	1	0	Covered	T519,T515,T517
1	1	1	Covered	T178,T311,T313

 LINE       17545
 EXPRESSION (addr_hit[161] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T516,T518,T517
1	1	1	Covered	T178,T311,T313

 LINE       17548
 EXPRESSION (addr_hit[162] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T519,T153
1	1	0	Covered	T379,T515,T525
1	1	1	Covered	T178,T311,T313

 LINE       17551
 EXPRESSION (addr_hit[163] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T525,T521
1	1	1	Covered	T178,T311,T313

 LINE       17554
 EXPRESSION (addr_hit[164] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T515,T521
1	1	1	Covered	T178,T311,T313

 LINE       17557
 EXPRESSION (addr_hit[165] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T515,T558
1	1	1	Covered	T311,T168,T251

 LINE       17560
 EXPRESSION (addr_hit[166] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T515,T516
1	1	1	Covered	T314,T311,T315

 LINE       17563
 EXPRESSION (addr_hit[167] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T515,T526
1	1	1	Covered	T314,T311,T315

 LINE       17566
 EXPRESSION (addr_hit[168] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T519,T520,T516
1	1	1	Covered	T311,T168,T251

 LINE       17569
 EXPRESSION (addr_hit[169] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T519,T153
1	1	0	Covered	T379,T521,T526
1	1	1	Covered	T311,T168,T251

 LINE       17572
 EXPRESSION (addr_hit[170] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T153
1	1	0	Covered	T519,T520,T515
1	1	1	Covered	T311,T168,T251

 LINE       17575
 EXPRESSION (addr_hit[171] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T519,T153
1	1	0	Covered	T379,T515,T517
1	1	1	Covered	T311,T168,T251

 LINE       17578
 EXPRESSION (addr_hit[172] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T519,T515
1	1	1	Covered	T147,T163,T311

 LINE       17581
 EXPRESSION (addr_hit[173] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T520,T515,T516
1	1	1	Covered	T311,T168,T251

 LINE       17584
 EXPRESSION (addr_hit[174] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T519,T520
1	1	1	Covered	T311,T168,T251

 LINE       17587
 EXPRESSION (addr_hit[175] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T516,T521,T522
1	1	1	Covered	T316,T311,T168

 LINE       17590
 EXPRESSION (addr_hit[176] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T520,T516,T521
1	1	1	Covered	T311,T168,T251

 LINE       17593
 EXPRESSION (addr_hit[177] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T517,T521
1	1	1	Covered	T311,T168,T251

 LINE       17596
 EXPRESSION (addr_hit[178] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T516,T525,T528
1	1	1	Covered	T311,T168,T251

 LINE       17599
 EXPRESSION (addr_hit[179] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T519,T515
1	1	1	Covered	T311,T9,T168

 LINE       17602
 EXPRESSION (addr_hit[180] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T515,T521
1	1	1	Covered	T311,T168,T251

 LINE       17605
 EXPRESSION (addr_hit[181] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T153
1	1	0	Covered	T520,T515,T516
1	1	1	Covered	T311,T168,T251

 LINE       17608
 EXPRESSION (addr_hit[182] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T519,T153
1	1	0	Covered	T519,T520,T515
1	1	1	Covered	T316,T311,T168

 LINE       17611
 EXPRESSION (addr_hit[183] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T515,T516,T517
1	1	1	Covered	T311,T168,T251

 LINE       17614
 EXPRESSION (addr_hit[184] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T520,T515,T516
1	1	1	Covered	T316,T311,T168

 LINE       17617
 EXPRESSION (addr_hit[185] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T520,T515
1	1	1	Covered	T311,T168,T251

 LINE       17620
 EXPRESSION (addr_hit[192] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T24,T23,T120
1	1	0	Covered	T515,T591,T592
1	1	1	Covered	T24,T23,T120

 LINE       17685
 EXPRESSION (addr_hit[193] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T4,T311,T34
1	1	0	Covered	T519,T515,T521
1	1	1	Covered	T4,T311,T34

 LINE       17750
 EXPRESSION (addr_hit[194] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T3,T4,T11
1	1	0	Covered	T520,T515,T516
1	1	1	Covered	T3,T4,T11

 LINE       17815
 EXPRESSION (addr_hit[195] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T39,T27,T75
1	1	0	Covered	T519,T520,T516
1	1	1	Covered	T39,T27,T75

 LINE       17880
 EXPRESSION (addr_hit[196] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T39
1	1	0	Covered	T521,T528,T589
1	1	1	Covered	T1,T3,T39

 LINE       17945
 EXPRESSION (addr_hit[197] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T178,T147,T316
1	1	0	Covered	T379,T519,T520
1	1	1	Covered	T178,T147,T316

 LINE       17998
 EXPRESSION (addr_hit[198] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T96,T379,T519
1	1	0	Covered	T379,T520,T516
1	1	1	Covered	T1,T4,T39

 LINE       18001
 EXPRESSION (addr_hit[199] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       18002
 EXPRESSION (addr_hit[199] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T3,T4
1	1	0	Covered	T515,T518,T517
1	1	1	Covered	T1,T3,T4