LINE 18005
EXPRESSION (addr_hit[200] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | 1 | Covered | T252,T96,T379 |
| 1 | 1 | 0 | Covered | T379,T519,T520 |
| 1 | 1 | 1 | Covered | T251,T252,T96 |
LINE 18008
EXPRESSION (addr_hit[201] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | 1 | Covered | T96,T379,T519 |
| 1 | 1 | 0 | Covered | T379,T520,T515 |
| 1 | 1 | 1 | Covered | T69,T70,T246 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |