Unified Coverage Report :: Cond split page

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 LINE       32988
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T187,T32

 LINE       32989
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T187,T32

 LINE       32990
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T187,T32

 LINE       32991
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T187,T32

 LINE       32992
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T187,T32

 LINE       32993
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T187,T32

 LINE       32994
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       32995
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       32996
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       32997
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       32998
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       32999
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33000
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33001
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33002
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33003
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33004
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33005
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33006
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33007
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33008
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33009
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33010
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33011
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33012
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33013
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33014
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33015
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33016
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33017
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33018
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T32

 LINE       33019
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T32

 LINE       33020
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T32

 LINE       33021
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T32

 LINE       33022
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33023
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33024
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33025
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33026
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33027
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET)
            ---------------------------------1---------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33028
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33029
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33030
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33031
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33032
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33033
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33034
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T32

 LINE       33035
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T32

 LINE       33036
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T32

 LINE       33037
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T32

 LINE       33038
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33039
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33040
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33041
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33042
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33043
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33044
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T32,T14

 LINE       33045
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T75,T76

 LINE       33046
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T11,T75

 LINE       33047
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T11,T75

 LINE       33048
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T188,T187

 LINE       33049
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T39,T75,T76

 LINE       33050
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T39,T75

 LINE       33051
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T39,T75

 LINE       33052
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T188

 LINE       33053
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET)
            --------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T10,T188

 LINE       33054
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T188,T187

 LINE       33055
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T188,T187

 LINE       33056
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T188,T187

 LINE       33057
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T10,T188

 LINE       33058
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T10,T188

 LINE       33059
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET)
            --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T188,T187

 LINE       33060
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T22,T188

 LINE       33061
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33062
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33063
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33064
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33065
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33066
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33067
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33068
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_0_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33069
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_1_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33070
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_2_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33071
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_3_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33072
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_4_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33073
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_5_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33074
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_6_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33075
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_EN_7_OFFSET)
            -------------------------------1------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33076
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_0_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33077
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_1_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33078
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_2_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33079
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_3_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33080
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_4_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33081
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_5_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33082
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_6_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33083
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_7_OFFSET)
            -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33084
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33085
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33086
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33087
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33088
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33089
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33090
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33091
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33092
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33093
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33094
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33095
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33096
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33097
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33098
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33099
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33100
 EXPRESSION (reg_addr == pinmux_reg_pkg::PINMUX_WKUP_CAUSE_OFFSET)
            ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33103
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       33103
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       33107
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be))))) | (addr_hit[28] & ((|(4'b1 & (~reg_be))))) | (addr_hit[29] & ((|(4'b1 & (~reg_be))))) | (addr_hit[30] & ((|(4'b1 & (~reg_be))))) | (addr_hit[31] & ((|(4'b1 & (~reg_be))))) | (addr_hit[32] & ((|(4'b1 & (~reg_be))))) | (addr_hit[33] & ((|(4'b1 & (~reg_be))))) | (addr_hit[34] & ((|(4'b1 & (~reg_be))))) | (addr_hit[35] & ((|(4'b1 & (~reg_be))))) | (addr_hit[36] & ((|(4'b1 & (~reg_be))))) | (addr_hit[37] & ((|(4'b1 & (~reg_be))))) | (addr_hit[38] & ((|(4'b1 & (~reg_be))))) | (addr_hit[39] & ((|(4'b1 & (~reg_be))))) | (addr_hit[40] & ((|(4'b1 & (~reg_be))))) | (addr_hit[41] & ((|(4'b1 & (~reg_be))))) | (addr_hit[42] & ((|(4'b1 & (~reg_be))))) | (addr_hit[43] & ((|(4'b1 & (~reg_be))))) | (addr_hit[44] & ((|(4'b1 & (~reg_be))))) | (addr_hit[45] & ((|(4'b1 & (~reg_be))))) | (addr_hit[46] & ((|(4'b1 & (~reg_be))))) | (addr_hit[47] & ((|(4'b1 & (~reg_be))))) | (addr_hit[48] & ((|(4'b1 & (~reg_be))))) | (addr_hit[49] & ((|(4'b1 & (~reg_be))))) | (addr_hit[50] & ((|(4'b1 & (~reg_be))))) | (addr_hit[51] & ((|(4'b1 & (~reg_be))))) | (addr_hit[52] & ((|(4'b1 & (~reg_be))))) | (addr_hit[53] & ((|(4'b1 & (~reg_be))))) | (addr_hit[54] & ((|(4'b1 & (~reg_be))))) | (addr_hit[55] & ((|(4'b1 & (~reg_be))))) | (addr_hit[56] & ((|(4'b1 & (~reg_be))))) | (addr_hit[57] & ((|(4'b1 & (~reg_be))))) | (addr_hit[58] & ((|(4'b1 & (~reg_be))))) | (addr_hit[59] & ((|(4'b1 & (~reg_be))))) | (addr_hit[60] & ((|(4'b1 & (~reg_be))))) | (addr_hit[61] & ((|(4'b1 & (~reg_be))))) | (addr_hit[62] & ((|(4'b1 & (~reg_be))))) | (addr_hit[63] & ((|(4'b1 & (~reg_be))))) | (addr_hit[64] & ((|(4'b1 & (~reg_be))))) | (addr_hit[65] & ((|(4'b1 & (~reg_be))))) | (addr_hit[66] & ((|(4'b1 & (~reg_be))))) | (addr_hit[67] & ((|(4'b1 & (~reg_be))))) | (addr_hit[68] & ((|(4'b1 & (~reg_be))))) | (addr_hit[69] & ((|(4'b1 & (~reg_be))))) | (addr_hit[70] & ((|(4'b1 & (~reg_be))))) | (addr_hit[71] & ((|(4'b1 & (~reg_be))))) | (addr_hit[72] & ((|(4'b1 & (~reg_be))))) | (addr_hit[73] & ((|(4'b1 & (~reg_be))))) | (addr_hit[74] & ((|(4'b1 & (~reg_be))))) | (addr_hit[75] & ((|(4'b1 & (~reg_be))))) | (addr_hit[76] & ((|(4'b1 & (~reg_be))))) | (addr_hit[77] & ((|(4'b1 & (~reg_be))))) | (addr_hit[78] & ((|(4'b1 & (~reg_be))))) | (addr_hit[79] & ((|(4'b1 & (~reg_be))))) | (addr_hit[80] & ((|(4'b1 & (~reg_be))))) | (addr_hit[81] & ((|(4'b1 & (~reg_be))))) | (addr_hit[82] & ((|(4'b1 & (~reg_be))))) | (addr_hit[83] & ((|(4'b1 & (~reg_be))))) | (addr_hit[84] & ((|(4'b1 & (~reg_be))))) | (addr_hit[85] & ((|(4'b1 & (~reg_be))))) | (addr_hit[86] & ((|(4'b1 & (~reg_be))))) | (addr_hit[87] & ((|(4'b1 & (~reg_be))))) | (addr_hit[88] & ((|(4'b1 & (~reg_be))))) | (addr_hit[89] & ((|(4'b1 & (~reg_be))))) | (addr_hit[90] & ((|(4'b1 & (~reg_be))))) | (addr_hit[91] & ((|(4'b1 & (~reg_be))))) | (addr_hit[92] & ((|(4'b1 & (~reg_be))))) | (addr_hit[93] & ((|(4'b1 & (~reg_be))))) | (addr_hit[94] & ((|(4'b1 & (~reg_be))))) | (addr_hit[95] & ((|(4'b1 & (~reg_be))))) | (addr_hit[96] & ((|(4'b1 & (~reg_be))))) | (addr_hit[97] & ((|(4'b1 & (~reg_be))))) | (addr_hit[98] & ((|(4'b1 & (~reg_be))))) | (addr_hit[99] & ((|(4'b1 & (~reg_be))))) | (addr_hit[100] & ((|(4'b1 & (~reg_be))))) | (addr_hit[101] & ((|(4'b1 & (~reg_be))))) | (addr_hit[102] & ((|(4'b1 & (~reg_be))))) | (addr_hit[103] & ((|(4'b1 & (~reg_be))))) | (addr_hit[104] & ((|(4'b1 & (~reg_be))))) | (addr_hit[105] & ((|(4'b1 & (~reg_be))))) | (addr_hit[106] & ((|(4'b1 & (~reg_be))))) | (addr_hit[107] & ((|(4'b1 & (~reg_be))))) | (addr_hit[108] & ((|(4'b1 & (~reg_be))))) | (addr_hit[109] & ((|(4'b1 & (~reg_be))))) | (addr_hit[110] & ((|(4'b1 & (~reg_be))))) | (addr_hit[111] & ((|(4'b1 & (~reg_be))))) | (addr_hit[112] & ((|(4'b1 & (~reg_be))))) | (addr_hit[113] & ((|(4'b1 & (~reg_be))))) | (addr_hit[114] & ((|(4'b1 & (~reg_be))))) | (addr_hit[115] & ((|(4'b1 & (~reg_be))))) | (addr_hit[116] & ((|(4'b1 & (~reg_be))))) | (addr_hit[117] & ((|(4'b1 & (~reg_be))))) | (addr_hit[118] & ((|(4'b1 & (~reg_be))))) | (addr_hit[119] & ((|(4'b1 & (~reg_be))))) | (addr_hit[120] & ((|(4'b1 & (~reg_be))))) | (addr_hit[121] & ((|(4'b1 & (~reg_be))))) | (addr_hit[122] & ((|(4'b1 & (~reg_be))))) | (addr_hit[123] & ((|(4'b1 & (~reg_be))))) | (addr_hit[124] & ((|(4'b1 & (~reg_be))))) | (addr_hit[125] & ((|(4'b1 & (~reg_be))))) | (addr_hit[126] & ((|(4'b1 & (~reg_be))))) | (addr_hit[127] & ((|(4'b1 & (~reg_be))))) | (addr_hit[128] & ((|(4'b1 & (~reg_be))))) | (addr_hit[129] & ((|(4'b1 & (~reg_be))))) | (addr_hit[130] & ((|(4'b1 & (~reg_be))))) | (addr_hit[131] & ((|(4'b1 & (~reg_be))))) | (addr_hit[132] & ((|(4'b1 & (~reg_be))))) | (addr_hit[133] & ((|(4'b1 & (~reg_be))))) | (addr_hit[134] & ((|(4'b1 & (~reg_be))))) | (addr_hit[135] & ((|(4'b1 & (~reg_be))))) | (addr_hit[136] & ((|(4'b1 & (~reg_be))))) | (addr_hit[137] & ((|(4'b1 & (~reg_be))))) | (addr_hit[138] & ((|(4'b1 & (~reg_be))))) | (addr_hit[139] & ((|(4'b1 & (~reg_be))))) | (addr_hit[140] & ((|(4'b1 & (~reg_be))))) | (addr_hit[141] & ((|(4'b1 & (~reg_be))))) | (addr_hit[142] & ((|(4'b1 & (~reg_be))))) | (addr_hit[143] & ((|(4'b1 & (~reg_be))))) | (addr_hit[144] & ((|(4'b1 & (~reg_be))))) | (addr_hit[145] & ((|(4'b1 & (~reg_be))))) | (addr_hit[146] & ((|(4'b1 & (~reg_be))))) | (addr_hit[147] & ((|(4'b1 & (~reg_be))))) | (addr_hit[148] & ((|(4'b1 & (~reg_be))))) | (addr_hit[149] & ((|(4'b1 & (~reg_be))))) | (addr_hit[150] & ((|(4'b1 & (~reg_be))))) | (addr_hit[151] & ((|(4'b1 & (~reg_be))))) | (addr_hit[152] & ((|(4'b1 & (~reg_be))))) | (addr_hit[153] & ((|(4'b1 & (~reg_be))))) | (addr_hit[154] & ((|(4'b1 & (~reg_be))))) | (addr_hit[155] & ((|(4'b1 & (~reg_be))))) | (addr_hit[156] & ((|(4'b1 & (~reg_be))))) | (addr_hit[157] & ((|(4'b1 & (~reg_be))))) | (addr_hit[158] & ((|(4'b1 & (~reg_be))))) | (addr_hit[159] & ((|(4'b1 & (~reg_be))))) | (addr_hit[160] & ((|(4'b1 & (~reg_be))))) | (addr_hit[161] & ((|(4'b1 & (~reg_be))))) | (addr_hit[162] & ((|(4'b1 & (~reg_be))))) | (addr_hit[163] & ((|(4'b1 & (~reg_be))))) | (addr_hit[164] & ((|(4'b1 & (~reg_be))))) | (addr_hit[165] & ((|(4'b1 & (~reg_be))))) | (addr_hit[166] & ((|(4'b1 & (~reg_be))))) | (addr_hit[167] & ((|(4'b1 & (~reg_be))))) | (addr_hit[168] & ((|(4'b1 & (~reg_be))))) | (addr_hit[169] & ((|(4'b1 & (~reg_be))))) | (addr_hit[170] & ((|(4'b1 & (~reg_be))))) | (addr_hit[171] & ((|(4'b1 & (~reg_be))))) | (addr_hit[172] & ((|(4'b1 & (~reg_be))))) | (addr_hit[173] & ((|(4'b1 & (~reg_be))))) | (addr_hit[174] & ((|(4'b1 & (~reg_be))))) | (addr_hit[175] & ((|(4'b1 & (~reg_be))))) | (addr_hit[176] & ((|(4'b1 & (~reg_be))))) | (addr_hit[177] & ((|(4'b1 & (~reg_be))))) | (addr_hit[178] & ((|(4'b1 & (~reg_be))))) | (addr_hit[179] & ((|(4'b1 & (~reg_be))))) | (addr_hit[180] & ((|(4'b1 & (~reg_be))))) | (addr_hit[181] & ((|(4'b1 & (~reg_be))))) | (addr_hit[182] & ((|(4'b1 & (~reg_be))))) | (addr_hit[183] & ((|(4'b1 & (~reg_be))))) | (addr_hit[184] & ((|(4'b1 & (~reg_be))))) | (addr_hit[185] & ((|(4'b1 & (~reg_be))))) | (addr_hit[186] & ((|(4'b1 & (~reg_be))))) | (addr_hit[187] & ((|(4'b1 & (~reg_be))))) | (addr_hit[188] & ((|(4'b1 & (~reg_be))))) | (addr_hit[189] & ((|(4'b1 & (~reg_be))))) | (addr_hit[190] & ((|(4'b1 & (~reg_be))))) | (addr_hit[191] & ((|(4'b1 & (~reg_be))))) | (addr_hit[192] & ((|(4'b1 & (~reg_be))))) | (addr_hit[193] & ((|(4'b1 & (~reg_be))))) | (addr_hit[194] & ((|(4'b1 & (~reg_be))))) | (addr_hit[195] & ((|(4'b1 & (~reg_be))))) | (addr_hit[196] & ((|(4'b1 & (~reg_be))))) | (addr_hit[197] & ((|(4'b1 & (~reg_be))))) | (addr_hit[198] & ((|(4'b1 & (~reg_be))))) | (addr_hit[199] & ((|(4'b1 & (~reg_be))))) | (addr_hit[200] & ((|(4'b1 & (~reg_be))))) | (addr_hit[201] & ((|(4'b1 & (~reg_be))))) | (addr_hit[202] & ((|(4'b1 & (~reg_be))))) | (addr_hit[203] & ((|(4'b1 & (~reg_be))))) | (addr_hit[204] & ((|(4'b1 & (~reg_be))))) | (addr_hit[205] & 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((|(4'b1 & (~reg_be))))) | (addr_hit[541] & ((|(4'b1 & (~reg_be))))) | (addr_hit[542] & ((|(4'b1 & (~reg_be))))) | (addr_hit[543] & ((|(4'b1 & (~reg_be))))) | (addr_hit[544] & ((|(4'b1 & (~reg_be))))) | (addr_hit[545] & ((|(4'b1 & (~reg_be))))) | (addr_hit[546] & ((|(4'b1 & (~reg_be))))) | (addr_hit[547] & ((|(4'b1 & (~reg_be))))) | (addr_hit[548] & ((|(4'b1 & (~reg_be))))) | (addr_hit[549] & ((|(4'b1 & (~reg_be))))) | (addr_hit[550] & ((|(4'b1 & (~reg_be))))) | (addr_hit[551] & ((|(4'b1 & (~reg_be))))) | (addr_hit[552] & ((|(4'b1 & (~reg_be))))) | (addr_hit[553] & ((|(4'b1 & (~reg_be))))) | (addr_hit[554] & ((|(4'b1 & (~reg_be))))) | (addr_hit[555] & ((|(4'b1 & (~reg_be))))) | (addr_hit[556] & ((|(4'b1 & (~reg_be))))) | (addr_hit[557] & ((|(4'b1 & (~reg_be))))) | (addr_hit[558] & ((|(4'b1 & (~reg_be))))) | (addr_hit[559] & ((|(4'b1 & (~reg_be))))) | (addr_hit[560] & ((|(4'b1 & (~reg_be))))) | (addr_hit[561] & ((|(4'b1 & (~reg_be))))) | (addr_hit[562] & ((|(4'b1 & (~reg_be))))) | (addr_hit[563] & ((|(4'b1 & (~reg_be))))) | (addr_hit[564] & ((|(4'b1 & (~reg_be))))) | (addr_hit[565] & ((|(4'b1 & (~reg_be))))) | (addr_hit[566] & ((|(4'b1 & (~reg_be))))) | (addr_hit[567] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T89,T250,T417